Commit | Line | Data |
---|---|---|
2c8086a5 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h |
2c8086a5 | 3 | * |
4 | * PXA3xx specific register definitions | |
5 | * | |
6 | * Copyright (C) 2007 Marvell International Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARCH_PXA3XX_REGS_H | |
14 | #define __ASM_ARCH_PXA3XX_REGS_H | |
dcc88a17 | 15 | |
51c62982 EM |
16 | #include <mach/hardware.h> |
17 | ||
dcc88a17 MB |
18 | /* |
19 | * Oscillator Configuration Register (OSCC) | |
20 | */ | |
21 | #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ | |
22 | ||
23 | #define OSCC_PEN (1 << 11) /* 13MHz POUT */ | |
24 | ||
25 | ||
c4d1fb62 | 26 | /* |
27 | * Service Power Management Unit (MPMU) | |
28 | */ | |
29 | #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ | |
30 | #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ | |
31 | #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ | |
32 | #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ | |
33 | #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ | |
34 | #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ | |
35 | #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ | |
36 | #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ | |
37 | #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ | |
38 | #define PCMD(x) __REG(0x40F50110 + ((x) << 2)) | |
2c8086a5 | 39 | |
7b5dea12 | 40 | /* |
25985edc | 41 | * Slave Power Management Unit |
7b5dea12 RK |
42 | */ |
43 | #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ | |
44 | #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ | |
45 | #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ | |
46 | #define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ | |
47 | #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ | |
48 | #define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ | |
49 | #define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ | |
50 | #define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ | |
51 | #define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ | |
52 | #define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ | |
53 | #define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ | |
54 | #define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ | |
55 | #define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ | |
56 | #define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ | |
57 | ||
58 | /* | |
59 | * Application Subsystem Configuration bits. | |
60 | */ | |
61 | #define ASCR_RDH (1 << 31) | |
62 | #define ASCR_D1S (1 << 2) | |
63 | #define ASCR_D2S (1 << 1) | |
64 | #define ASCR_D3S (1 << 0) | |
65 | ||
66 | /* | |
67 | * Application Reset Status bits. | |
68 | */ | |
69 | #define ARSR_GPR (1 << 3) | |
70 | #define ARSR_LPMR (1 << 2) | |
71 | #define ARSR_WDT (1 << 1) | |
72 | #define ARSR_HWR (1 << 0) | |
73 | ||
74 | /* | |
75 | * Application Subsystem Wake-Up bits. | |
76 | */ | |
77 | #define ADXER_WRTC (1 << 31) /* RTC */ | |
78 | #define ADXER_WOST (1 << 30) /* OS Timer */ | |
79 | #define ADXER_WTSI (1 << 29) /* Touchscreen */ | |
80 | #define ADXER_WUSBH (1 << 28) /* USB host */ | |
81 | #define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ | |
82 | #define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ | |
83 | #define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ | |
84 | #define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ | |
85 | #define ADXER_WKP (1 << 21) /* Keypad */ | |
86 | #define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ | |
87 | #define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ | |
88 | #define ADXER_WOTG (1 << 16) /* USBOTG input */ | |
89 | #define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ | |
90 | #define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ | |
91 | #define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ | |
92 | #define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ | |
93 | #define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ | |
94 | #define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ | |
95 | #define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ | |
96 | #define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ | |
97 | #define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ | |
98 | #define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ | |
99 | #define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ | |
100 | #define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ | |
101 | #define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ | |
102 | #define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ | |
103 | #define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ | |
104 | #define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ | |
105 | ||
106 | /* | |
107 | * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. | |
108 | */ | |
109 | #define ADXR_L2 (1 << 8) | |
110 | #define ADXR_R5 (1 << 5) | |
111 | #define ADXR_R4 (1 << 4) | |
112 | #define ADXR_R3 (1 << 3) | |
113 | #define ADXR_R2 (1 << 2) | |
114 | #define ADXR_R1 (1 << 1) | |
115 | #define ADXR_R0 (1 << 0) | |
116 | ||
117 | /* | |
118 | * Values for PWRMODE CP15 register | |
119 | */ | |
120 | #define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ | |
121 | #define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ | |
122 | #define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ | |
123 | #define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ | |
124 | #define PXA3xx_PM_S0D0C1 0x01 | |
125 | ||
2c8086a5 | 126 | /* |
127 | * Application Subsystem Clock | |
128 | */ | |
129 | #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ | |
130 | #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ | |
131 | #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ | |
132 | #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ | |
133 | #define CKENB __REG(0x41340010) /* B Clock Enable Register */ | |
d8bbb552 | 134 | #define CKENC __REG(0x41340024) /* C Clock Enable Register */ |
2c8086a5 | 135 | #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ |
136 | ||
5c52de4a EM |
137 | #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ |
138 | #define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ | |
139 | #define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ | |
140 | #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ | |
141 | #define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ | |
142 | ||
143 | #define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ | |
144 | #define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ | |
145 | #define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ | |
146 | #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ | |
147 | #define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ | |
148 | #define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ | |
149 | #define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ | |
150 | ||
151 | #define ACCR_SMCFS(x) (((x) & 0x7) << 23) | |
152 | #define ACCR_SFLFS(x) (((x) & 0x3) << 18) | |
153 | #define ACCR_XSPCLK(x) (((x) & 0x3) << 16) | |
154 | #define ACCR_HSS(x) (((x) & 0x3) << 14) | |
155 | #define ACCR_DMCFS(x) (((x) & 0x3) << 12) | |
156 | #define ACCR_XN(x) (((x) & 0x7) << 8) | |
157 | #define ACCR_XL(x) ((x) & 0x1f) | |
158 | ||
2c8086a5 | 159 | /* |
160 | * Clock Enable Bit | |
161 | */ | |
162 | #define CKEN_LCD 1 /* < LCD Clock Enable */ | |
163 | #define CKEN_USBH 2 /* < USB host clock enable */ | |
164 | #define CKEN_CAMERA 3 /* < Camera interface clock enable */ | |
165 | #define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ | |
166 | #define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ | |
167 | #define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ | |
168 | #define CKEN_SMC 9 /* < Static Memory Controller clock enable */ | |
169 | #define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ | |
170 | #define CKEN_BOOT 11 /* < Boot rom clock enable */ | |
171 | #define CKEN_MMC1 12 /* < MMC1 Clock enable */ | |
172 | #define CKEN_MMC2 13 /* < MMC2 clock enable */ | |
173 | #define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ | |
174 | #define CKEN_CIR 15 /* < Consumer IR Clock Enable */ | |
175 | #define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ | |
176 | #define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ | |
177 | #define CKEN_TPM 19 /* < TPM clock enable */ | |
178 | #define CKEN_UDC 20 /* < UDC clock enable */ | |
179 | #define CKEN_BTUART 21 /* < BTUART clock enable */ | |
180 | #define CKEN_FFUART 22 /* < FFUART clock enable */ | |
181 | #define CKEN_STUART 23 /* < STUART clock enable */ | |
182 | #define CKEN_AC97 24 /* < AC97 clock enable */ | |
183 | #define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ | |
184 | #define CKEN_SSP1 26 /* < SSP1 clock enable */ | |
185 | #define CKEN_SSP2 27 /* < SSP2 clock enable */ | |
186 | #define CKEN_SSP3 28 /* < SSP3 clock enable */ | |
187 | #define CKEN_SSP4 29 /* < SSP4 clock enable */ | |
188 | #define CKEN_MSL0 30 /* < MSL0 clock enable */ | |
189 | #define CKEN_PWM0 32 /* < PWM[0] clock enable */ | |
190 | #define CKEN_PWM1 33 /* < PWM[1] clock enable */ | |
191 | #define CKEN_I2C 36 /* < I2C clock enable */ | |
192 | #define CKEN_INTC 38 /* < Interrupt controller clock enable */ | |
193 | #define CKEN_GPIO 39 /* < GPIO clock enable */ | |
194 | #define CKEN_1WIRE 40 /* < 1-wire clock enable */ | |
195 | #define CKEN_HSIO2 41 /* < HSIO2 clock enable */ | |
196 | #define CKEN_MINI_IM 48 /* < Mini-IM */ | |
197 | #define CKEN_MINI_LCD 49 /* < Mini LCD */ | |
198 | ||
2c8086a5 | 199 | #define CKEN_MMC3 5 /* < MMC3 Clock Enable */ |
200 | #define CKEN_MVED 43 /* < MVED clock enable */ | |
2c8086a5 | 201 | |
202 | /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ | |
f0f04f08 DM |
203 | #define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ |
204 | #define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ | |
2c8086a5 | 205 | |
206 | #endif /* __ASM_ARCH_PXA3XX_REGS_H */ |