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e1d9b953 | 1 | /* |
2 | * linux/arch/arm/mach-pxa/littleton.c | |
3 | * | |
4 | * Support for the Marvell Littleton Development Platform. | |
5 | * | |
6 | * Author: Jason Chagas (largely modified code) | |
7 | * Created: Nov 20, 2006 | |
8 | * Copyright: (C) Copyright 2006 Marvell International Ltd. | |
9 | * | |
10 | * 2007-11-22 modified to align with latest kernel | |
11 | * eric miao <eric.miao@marvell.com> | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * publishhed by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/clk.h> | |
e1719da6 | 23 | #include <linux/smc91x.h> |
e1d9b953 | 24 | |
25 | #include <asm/types.h> | |
26 | #include <asm/setup.h> | |
27 | #include <asm/memory.h> | |
28 | #include <asm/mach-types.h> | |
a09e64fb | 29 | #include <mach/hardware.h> |
e1d9b953 | 30 | #include <asm/irq.h> |
31 | ||
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/map.h> | |
34 | #include <asm/mach/irq.h> | |
35 | ||
a09e64fb RK |
36 | #include <mach/pxa-regs.h> |
37 | #include <mach/mfp-pxa300.h> | |
38 | #include <mach/gpio.h> | |
39 | #include <mach/pxafb.h> | |
40 | #include <mach/ssp.h> | |
41 | #include <mach/pxa27x_keypad.h> | |
42 | #include <mach/pxa3xx_nand.h> | |
43 | #include <mach/littleton.h> | |
e1d9b953 | 44 | |
45 | #include "generic.h" | |
46 | ||
e1d9b953 | 47 | /* Littleton MFP configurations */ |
48 | static mfp_cfg_t littleton_mfp_cfg[] __initdata = { | |
49 | /* LCD */ | |
50 | GPIO54_LCD_LDD_0, | |
51 | GPIO55_LCD_LDD_1, | |
52 | GPIO56_LCD_LDD_2, | |
53 | GPIO57_LCD_LDD_3, | |
54 | GPIO58_LCD_LDD_4, | |
55 | GPIO59_LCD_LDD_5, | |
56 | GPIO60_LCD_LDD_6, | |
57 | GPIO61_LCD_LDD_7, | |
58 | GPIO62_LCD_LDD_8, | |
59 | GPIO63_LCD_LDD_9, | |
60 | GPIO64_LCD_LDD_10, | |
61 | GPIO65_LCD_LDD_11, | |
62 | GPIO66_LCD_LDD_12, | |
63 | GPIO67_LCD_LDD_13, | |
64 | GPIO68_LCD_LDD_14, | |
65 | GPIO69_LCD_LDD_15, | |
66 | GPIO70_LCD_LDD_16, | |
67 | GPIO71_LCD_LDD_17, | |
68 | GPIO72_LCD_FCLK, | |
69 | GPIO73_LCD_LCLK, | |
70 | GPIO74_LCD_PCLK, | |
71 | GPIO75_LCD_BIAS, | |
72 | ||
73 | /* SSP2 */ | |
74 | GPIO25_SSP2_SCLK, | |
75 | GPIO17_SSP2_FRM, | |
76 | GPIO27_SSP2_TXD, | |
77 | ||
78 | /* Debug Ethernet */ | |
79 | GPIO90_GPIO, | |
5fa41510 | 80 | |
81 | /* Keypad */ | |
82 | GPIO107_KP_DKIN_0, | |
83 | GPIO108_KP_DKIN_1, | |
84 | GPIO115_KP_MKIN_0, | |
85 | GPIO116_KP_MKIN_1, | |
86 | GPIO117_KP_MKIN_2, | |
87 | GPIO118_KP_MKIN_3, | |
88 | GPIO119_KP_MKIN_4, | |
89 | GPIO120_KP_MKIN_5, | |
90 | GPIO121_KP_MKOUT_0, | |
91 | GPIO122_KP_MKOUT_1, | |
92 | GPIO123_KP_MKOUT_2, | |
93 | GPIO124_KP_MKOUT_3, | |
94 | GPIO125_KP_MKOUT_4, | |
e1d9b953 | 95 | }; |
96 | ||
97 | static struct resource smc91x_resources[] = { | |
98 | [0] = { | |
99 | .start = (LITTLETON_ETH_PHYS + 0x300), | |
100 | .end = (LITTLETON_ETH_PHYS + 0xfffff), | |
101 | .flags = IORESOURCE_MEM, | |
102 | }, | |
103 | [1] = { | |
104 | .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), | |
105 | .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), | |
8a6e8873 | 106 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, |
e1d9b953 | 107 | } |
108 | }; | |
109 | ||
e1719da6 EM |
110 | static struct smc91x_platdata littleton_smc91x_info = { |
111 | .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | | |
112 | SMC91X_NOWAIT | SMC91X_USE_DMA, | |
113 | }; | |
114 | ||
e1d9b953 | 115 | static struct platform_device smc91x_device = { |
116 | .name = "smc91x", | |
117 | .id = 0, | |
118 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
119 | .resource = smc91x_resources, | |
e1719da6 EM |
120 | .dev = { |
121 | .platform_data = &littleton_smc91x_info, | |
122 | }, | |
e1d9b953 | 123 | }; |
124 | ||
36caeb4e | 125 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) |
e1d9b953 | 126 | /* use bit 30, 31 as the indicator of command parameter number */ |
127 | #define CMD0(x) ((0x00000000) | ((x) << 9)) | |
128 | #define CMD1(x, x1) ((0x40000000) | ((x) << 9) | 0x100 | (x1)) | |
129 | #define CMD2(x, x1, x2) ((0x80000000) | ((x) << 18) | 0x20000 |\ | |
130 | ((x1) << 9) | 0x100 | (x2)) | |
131 | ||
132 | static uint32_t lcd_panel_reset[] = { | |
133 | CMD0(0x1), /* reset */ | |
134 | CMD0(0x0), /* nop */ | |
135 | CMD0(0x0), /* nop */ | |
136 | CMD0(0x0), /* nop */ | |
137 | }; | |
138 | ||
139 | static uint32_t lcd_panel_on[] = { | |
140 | CMD0(0x29), /* Display ON */ | |
141 | CMD2(0xB8, 0xFF, 0xF9), /* Output Control */ | |
142 | CMD0(0x11), /* Sleep out */ | |
143 | CMD1(0xB0, 0x16), /* Wake */ | |
144 | }; | |
145 | ||
146 | static uint32_t lcd_panel_off[] = { | |
147 | CMD0(0x28), /* Display OFF */ | |
148 | CMD2(0xB8, 0x80, 0x02), /* Output Control */ | |
149 | CMD0(0x10), /* Sleep in */ | |
150 | CMD1(0xB0, 0x00), /* Deep stand by in */ | |
151 | }; | |
152 | ||
153 | static uint32_t lcd_vga_pass_through[] = { | |
154 | CMD1(0xB0, 0x16), | |
155 | CMD1(0xBC, 0x80), | |
156 | CMD1(0xE1, 0x00), | |
157 | CMD1(0x36, 0x50), | |
158 | CMD1(0x3B, 0x00), | |
159 | }; | |
160 | ||
161 | static uint32_t lcd_qvga_pass_through[] = { | |
162 | CMD1(0xB0, 0x16), | |
163 | CMD1(0xBC, 0x81), | |
164 | CMD1(0xE1, 0x00), | |
165 | CMD1(0x36, 0x50), | |
166 | CMD1(0x3B, 0x22), | |
167 | }; | |
168 | ||
169 | static uint32_t lcd_vga_transfer[] = { | |
170 | CMD1(0xcf, 0x02), /* Blanking period control (1) */ | |
171 | CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */ | |
172 | CMD1(0xd1, 0x01), /* CKV timing control on/off */ | |
173 | CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */ | |
174 | CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */ | |
175 | CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */ | |
176 | CMD1(0xd5, 0x14), /* ASW timing control (2) */ | |
177 | CMD0(0x21), /* Invert for normally black display */ | |
178 | CMD0(0x29), /* Display on */ | |
179 | }; | |
180 | ||
181 | static uint32_t lcd_qvga_transfer[] = { | |
182 | CMD1(0xd6, 0x02), /* Blanking period control (1) */ | |
183 | CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */ | |
184 | CMD1(0xd8, 0x01), /* CKV timing control on/off */ | |
185 | CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */ | |
186 | CMD2(0xde, 0x05, 0x0a), /* OEV timing control */ | |
187 | CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */ | |
188 | CMD1(0xe0, 0x0a), /* ASW timing control (2) */ | |
189 | CMD0(0x21), /* Invert for normally black display */ | |
190 | CMD0(0x29), /* Display on */ | |
191 | }; | |
192 | ||
193 | static uint32_t lcd_panel_config[] = { | |
194 | CMD2(0xb8, 0xff, 0xf9), /* Output control */ | |
195 | CMD0(0x11), /* sleep out */ | |
196 | CMD1(0xba, 0x01), /* Display mode (1) */ | |
197 | CMD1(0xbb, 0x00), /* Display mode (2) */ | |
198 | CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */ | |
199 | CMD1(0xbf, 0x10), /* Drive system change control */ | |
200 | CMD1(0xb1, 0x56), /* Booster operation setup */ | |
201 | CMD1(0xb2, 0x33), /* Booster mode setup */ | |
202 | CMD1(0xb3, 0x11), /* Booster frequency setup */ | |
203 | CMD1(0xb4, 0x02), /* Op amp/system clock */ | |
204 | CMD1(0xb5, 0x35), /* VCS voltage */ | |
205 | CMD1(0xb6, 0x40), /* VCOM voltage */ | |
206 | CMD1(0xb7, 0x03), /* External display signal */ | |
207 | CMD1(0xbd, 0x00), /* ASW slew rate */ | |
208 | CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */ | |
209 | CMD1(0xc0, 0x11), /* Sleep out FR count (A) */ | |
210 | CMD1(0xc1, 0x11), /* Sleep out FR count (B) */ | |
211 | CMD1(0xc2, 0x11), /* Sleep out FR count (C) */ | |
212 | CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */ | |
213 | CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */ | |
214 | CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */ | |
215 | CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */ | |
216 | CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */ | |
217 | CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */ | |
218 | CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */ | |
219 | CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */ | |
220 | CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */ | |
221 | }; | |
222 | ||
223 | static void ssp_reconfig(struct ssp_dev *dev, int nparam) | |
224 | { | |
225 | static int last_nparam = -1; | |
226 | ||
227 | /* check if it is necessary to re-config SSP */ | |
228 | if (nparam == last_nparam) | |
229 | return; | |
230 | ||
231 | ssp_disable(dev); | |
232 | ssp_config(dev, (nparam == 2) ? 0x0010058a : 0x00100581, 0x18, 0, 0); | |
233 | ||
234 | last_nparam = nparam; | |
235 | } | |
236 | ||
237 | static void ssp_send_cmd(uint32_t *cmd, int num) | |
238 | { | |
239 | static int ssp_initialized; | |
240 | static struct ssp_dev ssp2; | |
241 | ||
242 | int i; | |
243 | ||
244 | if (!ssp_initialized) { | |
245 | ssp_init(&ssp2, 2, SSP_NO_IRQ); | |
246 | ssp_initialized = 1; | |
247 | } | |
248 | ||
249 | clk_enable(ssp2.ssp->clk); | |
250 | for (i = 0; i < num; i++, cmd++) { | |
251 | ssp_reconfig(&ssp2, (*cmd >> 30) & 0x3); | |
252 | ssp_write_word(&ssp2, *cmd & 0x3fffffff); | |
253 | ||
254 | /* FIXME: ssp_flush() is mandatory here to work */ | |
255 | ssp_flush(&ssp2); | |
256 | } | |
257 | clk_disable(ssp2.ssp->clk); | |
258 | } | |
259 | ||
260 | static void littleton_lcd_power(int on, struct fb_var_screeninfo *var) | |
261 | { | |
262 | if (on) { | |
263 | ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_on)); | |
264 | ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_reset)); | |
265 | if (var->xres > 240) { | |
266 | /* VGA */ | |
267 | ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_pass_through)); | |
268 | ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config)); | |
269 | ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_transfer)); | |
270 | } else { | |
271 | /* QVGA */ | |
272 | ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_pass_through)); | |
273 | ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config)); | |
274 | ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_transfer)); | |
275 | } | |
276 | } else | |
277 | ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_off)); | |
278 | } | |
279 | ||
280 | static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = { | |
281 | [0] = { | |
282 | /* VGA */ | |
283 | .pixclock = 38250, | |
284 | .xres = 480, | |
285 | .yres = 640, | |
286 | .bpp = 16, | |
287 | .hsync_len = 8, | |
288 | .left_margin = 8, | |
289 | .right_margin = 24, | |
290 | .vsync_len = 2, | |
291 | .upper_margin = 2, | |
292 | .lower_margin = 4, | |
293 | .sync = 0, | |
294 | }, | |
295 | [1] = { | |
296 | /* QVGA */ | |
297 | .pixclock = 153000, | |
298 | .xres = 240, | |
299 | .yres = 320, | |
300 | .bpp = 16, | |
301 | .hsync_len = 8, | |
302 | .left_margin = 8, | |
303 | .right_margin = 88, | |
304 | .vsync_len = 2, | |
305 | .upper_margin = 2, | |
306 | .lower_margin = 2, | |
307 | .sync = 0, | |
308 | }, | |
309 | }; | |
310 | ||
311 | static struct pxafb_mach_info littleton_lcd_info = { | |
312 | .modes = tpo_tdo24mtea1_modes, | |
313 | .num_modes = 2, | |
0454bd09 | 314 | .lcd_conn = LCD_COLOR_TFT_16BPP, |
e1d9b953 | 315 | .pxafb_lcd_power = littleton_lcd_power, |
316 | }; | |
317 | ||
318 | static void littleton_init_lcd(void) | |
319 | { | |
320 | set_pxa_fb_info(&littleton_lcd_info); | |
321 | } | |
322 | #else | |
323 | static inline void littleton_init_lcd(void) {}; | |
36caeb4e | 324 | #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */ |
e1d9b953 | 325 | |
36caeb4e | 326 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) |
5fa41510 | 327 | static unsigned int littleton_matrix_key_map[] = { |
328 | /* KEY(row, col, key_code) */ | |
329 | KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), | |
330 | KEY(0, 1, KEY_4), KEY(1, 1, KEY_5), KEY(2, 1, KEY_6), KEY(0, 2, KEY_7), | |
331 | KEY(1, 2, KEY_8), KEY(2, 2, KEY_9), | |
332 | ||
333 | KEY(0, 3, KEY_KPASTERISK), /* * */ | |
334 | KEY(2, 3, KEY_KPDOT), /* # */ | |
335 | ||
336 | KEY(5, 4, KEY_ENTER), | |
337 | ||
338 | KEY(5, 0, KEY_UP), | |
339 | KEY(5, 1, KEY_DOWN), | |
340 | KEY(5, 2, KEY_LEFT), | |
341 | KEY(5, 3, KEY_RIGHT), | |
342 | KEY(3, 2, KEY_HOME), | |
343 | KEY(4, 1, KEY_END), | |
344 | KEY(3, 3, KEY_BACK), | |
345 | ||
346 | KEY(4, 0, KEY_SEND), | |
347 | KEY(4, 2, KEY_VOLUMEUP), | |
348 | KEY(4, 3, KEY_VOLUMEDOWN), | |
349 | ||
350 | KEY(3, 0, KEY_F22), /* soft1 */ | |
351 | KEY(3, 1, KEY_F23), /* soft2 */ | |
352 | }; | |
353 | ||
354 | static struct pxa27x_keypad_platform_data littleton_keypad_info = { | |
355 | .matrix_key_rows = 6, | |
356 | .matrix_key_cols = 5, | |
357 | .matrix_key_map = littleton_matrix_key_map, | |
358 | .matrix_key_map_size = ARRAY_SIZE(littleton_matrix_key_map), | |
359 | ||
360 | .enable_rotary0 = 1, | |
361 | .rotary0_up_key = KEY_UP, | |
362 | .rotary0_down_key = KEY_DOWN, | |
363 | ||
364 | .debounce_interval = 30, | |
365 | }; | |
366 | static void __init littleton_init_keypad(void) | |
367 | { | |
368 | pxa_set_keypad_info(&littleton_keypad_info); | |
369 | } | |
370 | #else | |
371 | static inline void littleton_init_keypad(void) {} | |
372 | #endif | |
373 | ||
9c1db1a1 EM |
374 | #if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) |
375 | static struct mtd_partition littleton_nand_partitions[] = { | |
376 | [0] = { | |
377 | .name = "Bootloader", | |
378 | .offset = 0, | |
379 | .size = 0x060000, | |
380 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
381 | }, | |
382 | [1] = { | |
383 | .name = "Kernel", | |
384 | .offset = 0x060000, | |
385 | .size = 0x200000, | |
386 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
387 | }, | |
388 | [2] = { | |
389 | .name = "Filesystem", | |
390 | .offset = 0x0260000, | |
391 | .size = 0x3000000, /* 48M - rootfs */ | |
392 | }, | |
393 | [3] = { | |
394 | .name = "MassStorage", | |
395 | .offset = 0x3260000, | |
396 | .size = 0x3d40000, | |
397 | }, | |
398 | [4] = { | |
399 | .name = "BBT", | |
400 | .offset = 0x6FA0000, | |
401 | .size = 0x80000, | |
402 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
403 | }, | |
404 | /* NOTE: we reserve some blocks at the end of the NAND flash for | |
405 | * bad block management, and the max number of relocation blocks | |
406 | * differs on different platforms. Please take care with it when | |
407 | * defining the partition table. | |
408 | */ | |
409 | }; | |
410 | ||
411 | static struct pxa3xx_nand_platform_data littleton_nand_info = { | |
412 | .enable_arbiter = 1, | |
413 | .parts = littleton_nand_partitions, | |
414 | .nr_parts = ARRAY_SIZE(littleton_nand_partitions), | |
415 | }; | |
416 | ||
417 | static void __init littleton_init_nand(void) | |
418 | { | |
419 | pxa3xx_set_nand_info(&littleton_nand_info); | |
420 | } | |
421 | #else | |
422 | static inline void littleton_init_nand(void) {} | |
423 | #endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */ | |
424 | ||
e1d9b953 | 425 | static void __init littleton_init(void) |
426 | { | |
427 | /* initialize MFP configurations */ | |
428 | pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg)); | |
429 | ||
430 | /* | |
431 | * Note: we depend bootloader set the correct | |
432 | * value to MSC register for SMC91x. | |
433 | */ | |
434 | platform_device_register(&smc91x_device); | |
435 | ||
436 | littleton_init_lcd(); | |
5fa41510 | 437 | littleton_init_keypad(); |
9c1db1a1 | 438 | littleton_init_nand(); |
e1d9b953 | 439 | } |
440 | ||
441 | MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)") | |
442 | .phys_io = 0x40000000, | |
443 | .boot_params = 0xa0000100, | |
444 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | |
445 | .map_io = pxa_map_io, | |
446 | .init_irq = pxa3xx_init_irq, | |
447 | .timer = &pxa_timer, | |
448 | .init_machine = littleton_init, | |
449 | MACHINE_END |