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e9937d4b LB |
1 | /* |
2 | * linux/arch/arm/mach-pxa/lpd270.c | |
3 | * | |
4 | * Support for the LogicPD PXA270 Card Engine. | |
5 | * Derived from the mainstone code, which carries these notices: | |
6 | * | |
7 | * Author: Nicolas Pitre | |
8 | * Created: Nov 05, 2002 | |
9 | * Copyright: MontaVista Software Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/sysdev.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/fb.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/partitions.h> | |
4a730719 | 26 | #include <linux/pwm_backlight.h> |
e9937d4b LB |
27 | |
28 | #include <asm/types.h> | |
29 | #include <asm/setup.h> | |
30 | #include <asm/memory.h> | |
31 | #include <asm/mach-types.h> | |
be509729 | 32 | #include <asm/arch/hardware.h> |
e9937d4b LB |
33 | #include <asm/irq.h> |
34 | #include <asm/sizes.h> | |
35 | ||
36 | #include <asm/mach/arch.h> | |
37 | #include <asm/mach/map.h> | |
38 | #include <asm/mach/irq.h> | |
39 | #include <asm/mach/flash.h> | |
40 | ||
41 | #include <asm/arch/pxa-regs.h> | |
8785a8fb | 42 | #include <asm/arch/pxa2xx-regs.h> |
a683b14d | 43 | #include <asm/arch/pxa2xx-gpio.h> |
e9937d4b LB |
44 | #include <asm/arch/lpd270.h> |
45 | #include <asm/arch/audio.h> | |
46 | #include <asm/arch/pxafb.h> | |
47 | #include <asm/arch/mmc.h> | |
48 | #include <asm/arch/irda.h> | |
49 | #include <asm/arch/ohci.h> | |
50 | ||
51 | #include "generic.h" | |
46c41e62 | 52 | #include "devices.h" |
e9937d4b LB |
53 | |
54 | ||
55 | static unsigned int lpd270_irq_enabled; | |
56 | ||
57 | static void lpd270_mask_irq(unsigned int irq) | |
58 | { | |
59 | int lpd270_irq = irq - LPD270_IRQ(0); | |
60 | ||
61 | __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS); | |
62 | ||
63 | lpd270_irq_enabled &= ~(1 << lpd270_irq); | |
64 | __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); | |
65 | } | |
66 | ||
67 | static void lpd270_unmask_irq(unsigned int irq) | |
68 | { | |
69 | int lpd270_irq = irq - LPD270_IRQ(0); | |
70 | ||
71 | lpd270_irq_enabled |= 1 << lpd270_irq; | |
72 | __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); | |
73 | } | |
74 | ||
38c677cb DB |
75 | static struct irq_chip lpd270_irq_chip = { |
76 | .name = "CPLD", | |
e9937d4b LB |
77 | .ack = lpd270_mask_irq, |
78 | .mask = lpd270_mask_irq, | |
79 | .unmask = lpd270_unmask_irq, | |
80 | }; | |
81 | ||
10dd5ce2 | 82 | static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc) |
e9937d4b LB |
83 | { |
84 | unsigned long pending; | |
85 | ||
86 | pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled; | |
87 | do { | |
88 | GEDR(0) = GPIO_bit(0); /* clear useless edge notification */ | |
89 | if (likely(pending)) { | |
90 | irq = LPD270_IRQ(0) + __ffs(pending); | |
91 | desc = irq_desc + irq; | |
0cd61b68 | 92 | desc_handle_irq(irq, desc); |
e9937d4b LB |
93 | |
94 | pending = __raw_readw(LPD270_INT_STATUS) & | |
95 | lpd270_irq_enabled; | |
96 | } | |
97 | } while (pending); | |
98 | } | |
99 | ||
100 | static void __init lpd270_init_irq(void) | |
101 | { | |
102 | int irq; | |
103 | ||
cd49104d | 104 | pxa27x_init_irq(); |
e9937d4b LB |
105 | |
106 | __raw_writew(0, LPD270_INT_MASK); | |
107 | __raw_writew(0, LPD270_INT_STATUS); | |
108 | ||
109 | /* setup extra LogicPD PXA270 irqs */ | |
110 | for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { | |
111 | set_irq_chip(irq, &lpd270_irq_chip); | |
10dd5ce2 | 112 | set_irq_handler(irq, handle_level_irq); |
e9937d4b LB |
113 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
114 | } | |
115 | set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); | |
6cab4860 | 116 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
e9937d4b LB |
117 | } |
118 | ||
119 | ||
120 | #ifdef CONFIG_PM | |
121 | static int lpd270_irq_resume(struct sys_device *dev) | |
122 | { | |
123 | __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); | |
124 | return 0; | |
125 | } | |
126 | ||
127 | static struct sysdev_class lpd270_irq_sysclass = { | |
af5ca3f4 | 128 | .name = "cpld_irq", |
e9937d4b LB |
129 | .resume = lpd270_irq_resume, |
130 | }; | |
131 | ||
132 | static struct sys_device lpd270_irq_device = { | |
133 | .cls = &lpd270_irq_sysclass, | |
134 | }; | |
135 | ||
136 | static int __init lpd270_irq_device_init(void) | |
137 | { | |
720046de RK |
138 | int ret = -ENODEV; |
139 | if (machine_is_logicpd_pxa270()) { | |
140 | ret = sysdev_class_register(&lpd270_irq_sysclass); | |
141 | if (ret == 0) | |
142 | ret = sysdev_register(&lpd270_irq_device); | |
143 | } | |
e9937d4b LB |
144 | return ret; |
145 | } | |
146 | ||
147 | device_initcall(lpd270_irq_device_init); | |
148 | #endif | |
149 | ||
150 | ||
151 | static struct resource smc91x_resources[] = { | |
152 | [0] = { | |
153 | .start = LPD270_ETH_PHYS, | |
154 | .end = (LPD270_ETH_PHYS + 0xfffff), | |
155 | .flags = IORESOURCE_MEM, | |
156 | }, | |
157 | [1] = { | |
158 | .start = LPD270_ETHERNET_IRQ, | |
159 | .end = LPD270_ETHERNET_IRQ, | |
160 | .flags = IORESOURCE_IRQ, | |
161 | }, | |
162 | }; | |
163 | ||
164 | static struct platform_device smc91x_device = { | |
165 | .name = "smc91x", | |
166 | .id = 0, | |
167 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
168 | .resource = smc91x_resources, | |
169 | }; | |
170 | ||
e9937d4b LB |
171 | static struct resource lpd270_flash_resources[] = { |
172 | [0] = { | |
173 | .start = PXA_CS0_PHYS, | |
174 | .end = PXA_CS0_PHYS + SZ_64M - 1, | |
175 | .flags = IORESOURCE_MEM, | |
176 | }, | |
177 | [1] = { | |
178 | .start = PXA_CS1_PHYS, | |
179 | .end = PXA_CS1_PHYS + SZ_64M - 1, | |
180 | .flags = IORESOURCE_MEM, | |
181 | }, | |
182 | }; | |
183 | ||
184 | static struct mtd_partition lpd270_flash0_partitions[] = { | |
185 | { | |
186 | .name = "Bootloader", | |
187 | .size = 0x00040000, | |
188 | .offset = 0, | |
189 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
190 | }, { | |
191 | .name = "Kernel", | |
192 | .size = 0x00400000, | |
193 | .offset = 0x00040000, | |
194 | }, { | |
195 | .name = "Filesystem", | |
196 | .size = MTDPART_SIZ_FULL, | |
197 | .offset = 0x00440000 | |
198 | }, | |
199 | }; | |
200 | ||
201 | static struct flash_platform_data lpd270_flash_data[2] = { | |
202 | { | |
203 | .name = "processor-flash", | |
204 | .map_name = "cfi_probe", | |
205 | .parts = lpd270_flash0_partitions, | |
206 | .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions), | |
207 | }, { | |
208 | .name = "mainboard-flash", | |
209 | .map_name = "cfi_probe", | |
210 | .parts = NULL, | |
211 | .nr_parts = 0, | |
212 | } | |
213 | }; | |
214 | ||
215 | static struct platform_device lpd270_flash_device[2] = { | |
216 | { | |
217 | .name = "pxa2xx-flash", | |
218 | .id = 0, | |
219 | .dev = { | |
220 | .platform_data = &lpd270_flash_data[0], | |
221 | }, | |
222 | .resource = &lpd270_flash_resources[0], | |
223 | .num_resources = 1, | |
224 | }, { | |
225 | .name = "pxa2xx-flash", | |
226 | .id = 1, | |
227 | .dev = { | |
228 | .platform_data = &lpd270_flash_data[1], | |
229 | }, | |
230 | .resource = &lpd270_flash_resources[1], | |
231 | .num_resources = 1, | |
232 | }, | |
233 | }; | |
234 | ||
4a730719 RK |
235 | static struct platform_pwm_backlight_data lpd270_backlight_data = { |
236 | .pwm_id = 0, | |
237 | .max_brightness = 1, | |
238 | .dft_brightness = 1, | |
239 | .pwm_period_ns = 78770, | |
240 | }; | |
241 | ||
242 | static struct platform_device lpd270_backlight_device = { | |
243 | .name = "pwm-backlight", | |
244 | .dev = { | |
245 | .parent = &pxa27x_device_pwm0.dev, | |
246 | .platform_data = &lpd270_backlight_data, | |
247 | }, | |
248 | }; | |
e9937d4b LB |
249 | |
250 | /* 5.7" TFT QVGA (LoLo display number 1) */ | |
d14b272b | 251 | static struct pxafb_mode_info sharp_lq057q3dc02_mode = { |
65660297 LB |
252 | .pixclock = 150000, |
253 | .xres = 320, | |
254 | .yres = 240, | |
e9937d4b | 255 | .bpp = 16, |
65660297 LB |
256 | .hsync_len = 0x14, |
257 | .left_margin = 0x28, | |
258 | .right_margin = 0x0a, | |
259 | .vsync_len = 0x02, | |
e9937d4b LB |
260 | .upper_margin = 0x08, |
261 | .lower_margin = 0x14, | |
65660297 | 262 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
d14b272b RP |
263 | }; |
264 | ||
265 | static struct pxafb_mach_info sharp_lq057q3dc02 = { | |
266 | .modes = &sharp_lq057q3dc02_mode, | |
267 | .num_modes = 1, | |
e9937d4b | 268 | .lccr0 = 0x07800080, |
65660297 | 269 | .lccr3 = 0x00400000, |
65660297 LB |
270 | }; |
271 | ||
272 | /* 12.1" TFT SVGA (LoLo display number 2) */ | |
d14b272b | 273 | static struct pxafb_mode_info sharp_lq121s1dg31_mode = { |
65660297 LB |
274 | .pixclock = 50000, |
275 | .xres = 800, | |
276 | .yres = 600, | |
277 | .bpp = 16, | |
278 | .hsync_len = 0x05, | |
279 | .left_margin = 0x52, | |
280 | .right_margin = 0x05, | |
281 | .vsync_len = 0x04, | |
282 | .upper_margin = 0x14, | |
283 | .lower_margin = 0x0a, | |
284 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
285 | }; |
286 | ||
287 | static struct pxafb_mach_info sharp_lq121s1dg31 = { | |
288 | .modes = &sharp_lq121s1dg31_mode, | |
289 | .num_modes = 1, | |
65660297 LB |
290 | .lccr0 = 0x07800080, |
291 | .lccr3 = 0x00400000, | |
65660297 LB |
292 | }; |
293 | ||
294 | /* 3.6" TFT QVGA (LoLo display number 3) */ | |
d14b272b | 295 | static struct pxafb_mode_info sharp_lq036q1da01_mode = { |
65660297 LB |
296 | .pixclock = 150000, |
297 | .xres = 320, | |
298 | .yres = 240, | |
299 | .bpp = 16, | |
300 | .hsync_len = 0x0e, | |
301 | .left_margin = 0x04, | |
302 | .right_margin = 0x0a, | |
303 | .vsync_len = 0x03, | |
304 | .upper_margin = 0x03, | |
305 | .lower_margin = 0x03, | |
306 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
307 | }; |
308 | ||
309 | static struct pxafb_mach_info sharp_lq036q1da01 = { | |
310 | .modes = &sharp_lq036q1da01_mode, | |
311 | .num_modes = 1, | |
65660297 LB |
312 | .lccr0 = 0x07800080, |
313 | .lccr3 = 0x00400000, | |
e9937d4b LB |
314 | }; |
315 | ||
316 | /* 6.4" TFT VGA (LoLo display number 5) */ | |
d14b272b | 317 | static struct pxafb_mode_info sharp_lq64d343_mode = { |
65660297 | 318 | .pixclock = 25000, |
e9937d4b LB |
319 | .xres = 640, |
320 | .yres = 480, | |
321 | .bpp = 16, | |
65660297 | 322 | .hsync_len = 0x31, |
e9937d4b LB |
323 | .left_margin = 0x89, |
324 | .right_margin = 0x19, | |
65660297 | 325 | .vsync_len = 0x12, |
e9937d4b | 326 | .upper_margin = 0x22, |
65660297 | 327 | .lower_margin = 0x00, |
e9937d4b | 328 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
d14b272b RP |
329 | }; |
330 | ||
331 | static struct pxafb_mach_info sharp_lq64d343 = { | |
332 | .modes = &sharp_lq64d343_mode, | |
333 | .num_modes = 1, | |
e9937d4b | 334 | .lccr0 = 0x07800080, |
65660297 | 335 | .lccr3 = 0x00400000, |
65660297 LB |
336 | }; |
337 | ||
338 | /* 10.4" TFT VGA (LoLo display number 7) */ | |
d14b272b | 339 | static struct pxafb_mode_info sharp_lq10d368_mode = { |
65660297 LB |
340 | .pixclock = 25000, |
341 | .xres = 640, | |
342 | .yres = 480, | |
343 | .bpp = 16, | |
344 | .hsync_len = 0x31, | |
345 | .left_margin = 0x89, | |
346 | .right_margin = 0x19, | |
347 | .vsync_len = 0x12, | |
348 | .upper_margin = 0x22, | |
349 | .lower_margin = 0x00, | |
350 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
d14b272b RP |
351 | }; |
352 | ||
353 | static struct pxafb_mach_info sharp_lq10d368 = { | |
354 | .modes = &sharp_lq10d368_mode, | |
355 | .num_modes = 1, | |
65660297 LB |
356 | .lccr0 = 0x07800080, |
357 | .lccr3 = 0x00400000, | |
e9937d4b LB |
358 | }; |
359 | ||
360 | /* 3.5" TFT QVGA (LoLo display number 8) */ | |
d14b272b | 361 | static struct pxafb_mode_info sharp_lq035q7db02_20_mode = { |
65660297 | 362 | .pixclock = 150000, |
e9937d4b LB |
363 | .xres = 240, |
364 | .yres = 320, | |
365 | .bpp = 16, | |
65660297 LB |
366 | .hsync_len = 0x0e, |
367 | .left_margin = 0x0a, | |
368 | .right_margin = 0x0a, | |
369 | .vsync_len = 0x03, | |
e9937d4b LB |
370 | .upper_margin = 0x05, |
371 | .lower_margin = 0x14, | |
65660297 | 372 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
d14b272b RP |
373 | }; |
374 | ||
375 | static struct pxafb_mach_info sharp_lq035q7db02_20 = { | |
376 | .modes = &sharp_lq035q7db02_20_mode, | |
377 | .num_modes = 1, | |
e9937d4b | 378 | .lccr0 = 0x07800080, |
65660297 | 379 | .lccr3 = 0x00400000, |
e9937d4b LB |
380 | }; |
381 | ||
65660297 LB |
382 | static struct pxafb_mach_info *lpd270_lcd_to_use; |
383 | ||
384 | static int __init lpd270_set_lcd(char *str) | |
385 | { | |
386 | if (!strnicmp(str, "lq057q3dc02", 11)) { | |
387 | lpd270_lcd_to_use = &sharp_lq057q3dc02; | |
388 | } else if (!strnicmp(str, "lq121s1dg31", 11)) { | |
389 | lpd270_lcd_to_use = &sharp_lq121s1dg31; | |
390 | } else if (!strnicmp(str, "lq036q1da01", 11)) { | |
391 | lpd270_lcd_to_use = &sharp_lq036q1da01; | |
392 | } else if (!strnicmp(str, "lq64d343", 8)) { | |
393 | lpd270_lcd_to_use = &sharp_lq64d343; | |
394 | } else if (!strnicmp(str, "lq10d368", 8)) { | |
395 | lpd270_lcd_to_use = &sharp_lq10d368; | |
396 | } else if (!strnicmp(str, "lq035q7db02-20", 14)) { | |
397 | lpd270_lcd_to_use = &sharp_lq035q7db02_20; | |
398 | } else { | |
399 | printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str); | |
400 | } | |
401 | ||
402 | return 1; | |
403 | } | |
404 | ||
405 | __setup("lcd=", lpd270_set_lcd); | |
406 | ||
e9937d4b LB |
407 | static struct platform_device *platform_devices[] __initdata = { |
408 | &smc91x_device, | |
4a730719 | 409 | &lpd270_backlight_device, |
e9937d4b LB |
410 | &lpd270_flash_device[0], |
411 | &lpd270_flash_device[1], | |
412 | }; | |
413 | ||
414 | static int lpd270_ohci_init(struct device *dev) | |
415 | { | |
416 | /* setup Port1 GPIO pin. */ | |
417 | pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */ | |
418 | pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */ | |
419 | ||
420 | /* Set the Power Control Polarity Low and Power Sense | |
421 | Polarity Low to active low. */ | |
422 | UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & | |
423 | ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE); | |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
428 | static struct pxaohci_platform_data lpd270_ohci_platform_data = { | |
429 | .port_mode = PMM_PERPORT_MODE, | |
430 | .init = lpd270_ohci_init, | |
431 | }; | |
432 | ||
433 | static void __init lpd270_init(void) | |
434 | { | |
435 | lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; | |
436 | lpd270_flash_data[1].width = 4; | |
437 | ||
438 | /* | |
439 | * System bus arbiter setting: | |
440 | * - Core_Park | |
441 | * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4 | |
442 | */ | |
443 | ARB_CNTRL = ARB_CORE_PARK | 0x234; | |
444 | ||
445 | /* | |
446 | * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45. | |
447 | */ | |
448 | pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); | |
4a730719 | 449 | pxa_gpio_mode(GPIO16_PWM0_MD); |
e9937d4b LB |
450 | |
451 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | |
452 | ||
9f19d638 MB |
453 | pxa_set_ac97_info(NULL); |
454 | ||
65660297 LB |
455 | if (lpd270_lcd_to_use != NULL) |
456 | set_pxa_fb_info(lpd270_lcd_to_use); | |
e9937d4b LB |
457 | |
458 | pxa_set_ohci_info(&lpd270_ohci_platform_data); | |
459 | } | |
460 | ||
461 | ||
462 | static struct map_desc lpd270_io_desc[] __initdata = { | |
463 | { | |
464 | .virtual = LPD270_CPLD_VIRT, | |
465 | .pfn = __phys_to_pfn(LPD270_CPLD_PHYS), | |
466 | .length = LPD270_CPLD_SIZE, | |
467 | .type = MT_DEVICE, | |
468 | }, | |
469 | }; | |
470 | ||
471 | static void __init lpd270_map_io(void) | |
472 | { | |
473 | pxa_map_io(); | |
474 | iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc)); | |
475 | ||
476 | /* initialize sleep mode regs (wake-up sources, etc) */ | |
477 | PGSR0 = 0x00008800; | |
478 | PGSR1 = 0x00000002; | |
479 | PGSR2 = 0x0001FC00; | |
480 | PGSR3 = 0x00001F81; | |
481 | PWER = 0xC0000002; | |
482 | PRER = 0x00000002; | |
483 | PFER = 0x00000002; | |
484 | ||
485 | /* for use I SRAM as framebuffer. */ | |
486 | PSLR |= 0x00000F04; | |
487 | PCFR = 0x00000066; | |
488 | } | |
489 | ||
490 | MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine") | |
491 | /* Maintainer: Peter Barada */ | |
492 | .phys_io = 0x40000000, | |
493 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | |
494 | .boot_params = 0xa0000100, | |
495 | .map_io = lpd270_map_io, | |
496 | .init_irq = lpd270_init_irq, | |
497 | .timer = &pxa_timer, | |
498 | .init_machine = lpd270_init, | |
499 | MACHINE_END |