Commit | Line | Data |
---|---|---|
7facc2f9 | 1 | /* |
2 | * linux/arch/arm/mach-pxa/mfp-pxa2xx.c | |
3 | * | |
4 | * PXA2xx pin mux configuration support | |
5 | * | |
6 | * The GPIOs on PXA2xx can be configured as one of many alternate | |
7 | * functions, this is by concept samilar to the MFP configuration | |
8 | * on PXA3xx, what's more important, the low power pin state and | |
9 | * wakeup detection are also supported by the same framework. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/init.h> | |
2eaa03b5 | 19 | #include <linux/syscore_ops.h> |
7facc2f9 | 20 | |
da065a0b | 21 | #include <mach/gpio.h> |
a09e64fb RK |
22 | #include <mach/pxa2xx-regs.h> |
23 | #include <mach/mfp-pxa2xx.h> | |
7facc2f9 | 24 | |
25 | #include "generic.h" | |
26 | ||
5a3d9651 EM |
27 | #define PGSR(x) __REG2(0x40F00020, (x) << 2) |
28 | #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3) | |
29 | #define GAFR_L(x) __GAFR(0, x) | |
30 | #define GAFR_U(x) __GAFR(1, x) | |
7facc2f9 | 31 | |
32 | #define PWER_WE35 (1 << 24) | |
33 | ||
c0a596d6 | 34 | struct gpio_desc { |
7facc2f9 | 35 | unsigned valid : 1; |
36 | unsigned can_wakeup : 1; | |
37 | unsigned keypad_gpio : 1; | |
067455aa | 38 | unsigned dir_inverted : 1; |
7facc2f9 | 39 | unsigned int mask; /* bit mask in PWER or PKWR */ |
99687114 | 40 | unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */ |
7facc2f9 | 41 | unsigned long config; |
c0a596d6 | 42 | }; |
43 | ||
44 | static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1]; | |
7facc2f9 | 45 | |
5a3d9651 | 46 | static unsigned long gpdr_lpm[4]; |
566b450c | 47 | |
c0a596d6 | 48 | static int __mfp_config_gpio(unsigned gpio, unsigned long c) |
7facc2f9 | 49 | { |
50 | unsigned long gafr, mask = GPIO_bit(gpio); | |
5a3d9651 EM |
51 | int bank = gpio_to_bank(gpio); |
52 | int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */ | |
53 | int shft = (gpio & 0xf) << 1; | |
54 | int fn = MFP_AF(c); | |
067455aa | 55 | int is_out = (c & MFP_DIR_OUT) ? 1 : 0; |
7facc2f9 | 56 | |
7facc2f9 | 57 | if (fn > 3) |
58 | return -EINVAL; | |
59 | ||
5a3d9651 EM |
60 | /* alternate function and direction at run-time */ |
61 | gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank); | |
62 | gafr = (gafr & ~(0x3 << shft)) | (fn << shft); | |
7facc2f9 | 63 | |
5a3d9651 EM |
64 | if (uorl == 0) |
65 | GAFR_L(bank) = gafr; | |
66 | else | |
67 | GAFR_U(bank) = gafr; | |
68 | ||
067455aa | 69 | if (is_out ^ gpio_desc[gpio].dir_inverted) |
7facc2f9 | 70 | GPDR(gpio) |= mask; |
71 | else | |
72 | GPDR(gpio) &= ~mask; | |
73 | ||
5a3d9651 EM |
74 | /* alternate function and direction at low power mode */ |
75 | switch (c & MFP_LPM_STATE_MASK) { | |
76 | case MFP_LPM_DRIVE_HIGH: | |
77 | PGSR(bank) |= mask; | |
067455aa | 78 | is_out = 1; |
5a3d9651 EM |
79 | break; |
80 | case MFP_LPM_DRIVE_LOW: | |
81 | PGSR(bank) &= ~mask; | |
067455aa | 82 | is_out = 1; |
5a3d9651 | 83 | break; |
1fe8c2bc | 84 | case MFP_LPM_INPUT: |
5a3d9651 EM |
85 | case MFP_LPM_DEFAULT: |
86 | break; | |
87 | default: | |
88 | /* warning and fall through, treat as MFP_LPM_DEFAULT */ | |
89 | pr_warning("%s: GPIO%d: unsupported low power mode\n", | |
90 | __func__, gpio); | |
91 | break; | |
92 | } | |
93 | ||
067455aa | 94 | if (is_out ^ gpio_desc[gpio].dir_inverted) |
5a3d9651 EM |
95 | gpdr_lpm[bank] |= mask; |
96 | else | |
97 | gpdr_lpm[bank] &= ~mask; | |
7facc2f9 | 98 | |
c0a596d6 | 99 | /* give early warning if MFP_LPM_CAN_WAKEUP is set on the |
100 | * configurations of those pins not able to wakeup | |
101 | */ | |
102 | if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) { | |
7facc2f9 | 103 | pr_warning("%s: GPIO%d unable to wakeup\n", |
104 | __func__, gpio); | |
105 | return -EINVAL; | |
106 | } | |
107 | ||
067455aa | 108 | if ((c & MFP_LPM_CAN_WAKEUP) && is_out) { |
c0a596d6 | 109 | pr_warning("%s: output GPIO%d unable to wakeup\n", |
110 | __func__, gpio); | |
111 | return -EINVAL; | |
7facc2f9 | 112 | } |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
0fedb0ca EM |
117 | static inline int __mfp_validate(int mfp) |
118 | { | |
119 | int gpio = mfp_to_gpio(mfp); | |
120 | ||
121 | if ((mfp > MFP_PIN_GPIO127) || !gpio_desc[gpio].valid) { | |
122 | pr_warning("%s: GPIO%d is invalid pin\n", __func__, gpio); | |
123 | return -1; | |
124 | } | |
125 | ||
126 | return gpio; | |
127 | } | |
128 | ||
7facc2f9 | 129 | void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num) |
130 | { | |
131 | unsigned long flags; | |
132 | unsigned long *c; | |
133 | int i, gpio; | |
134 | ||
135 | for (i = 0, c = mfp_cfgs; i < num; i++, c++) { | |
136 | ||
0fedb0ca EM |
137 | gpio = __mfp_validate(MFP_PIN(*c)); |
138 | if (gpio < 0) | |
7facc2f9 | 139 | continue; |
7facc2f9 | 140 | |
141 | local_irq_save(flags); | |
142 | ||
143 | gpio_desc[gpio].config = *c; | |
144 | __mfp_config_gpio(gpio, *c); | |
145 | ||
146 | local_irq_restore(flags); | |
147 | } | |
148 | } | |
149 | ||
566b450c EM |
150 | void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm) |
151 | { | |
5a3d9651 | 152 | unsigned long flags, c; |
566b450c EM |
153 | int gpio; |
154 | ||
155 | gpio = __mfp_validate(mfp); | |
156 | if (gpio < 0) | |
157 | return; | |
158 | ||
159 | local_irq_save(flags); | |
5a3d9651 EM |
160 | |
161 | c = gpio_desc[gpio].config; | |
162 | c = (c & ~MFP_LPM_STATE_MASK) | lpm; | |
163 | __mfp_config_gpio(gpio, c); | |
164 | ||
566b450c EM |
165 | local_irq_restore(flags); |
166 | } | |
167 | ||
c0a596d6 | 168 | int gpio_set_wake(unsigned int gpio, unsigned int on) |
169 | { | |
170 | struct gpio_desc *d; | |
99687114 | 171 | unsigned long c, mux_taken; |
c0a596d6 | 172 | |
173 | if (gpio > mfp_to_gpio(MFP_PIN_GPIO127)) | |
174 | return -EINVAL; | |
175 | ||
176 | d = &gpio_desc[gpio]; | |
177 | c = d->config; | |
178 | ||
179 | if (!d->valid) | |
180 | return -EINVAL; | |
181 | ||
c09f431c EM |
182 | /* Allow keypad GPIOs to wakeup system when |
183 | * configured as generic GPIOs. | |
184 | */ | |
185 | if (d->keypad_gpio && (MFP_AF(d->config) == 0) && | |
186 | (d->config & MFP_LPM_CAN_WAKEUP)) { | |
187 | if (on) | |
188 | PKWR |= d->mask; | |
189 | else | |
190 | PKWR &= ~d->mask; | |
191 | return 0; | |
192 | } | |
c0a596d6 | 193 | |
99687114 RJ |
194 | mux_taken = (PWER & d->mux_mask) & (~d->mask); |
195 | if (on && mux_taken) | |
196 | return -EBUSY; | |
197 | ||
c0a596d6 | 198 | if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) { |
199 | if (on) { | |
99687114 | 200 | PWER = (PWER & ~d->mux_mask) | d->mask; |
c0a596d6 | 201 | |
202 | if (c & MFP_LPM_EDGE_RISE) | |
203 | PRER |= d->mask; | |
204 | else | |
205 | PRER &= ~d->mask; | |
206 | ||
207 | if (c & MFP_LPM_EDGE_FALL) | |
208 | PFER |= d->mask; | |
209 | else | |
210 | PFER &= ~d->mask; | |
211 | } else { | |
212 | PWER &= ~d->mask; | |
213 | PRER &= ~d->mask; | |
214 | PFER &= ~d->mask; | |
215 | } | |
216 | } | |
217 | return 0; | |
218 | } | |
219 | ||
7facc2f9 | 220 | #ifdef CONFIG_PXA25x |
5a3d9651 | 221 | static void __init pxa25x_mfp_init(void) |
7facc2f9 | 222 | { |
223 | int i; | |
224 | ||
ddd244dd | 225 | for (i = 0; i <= pxa_last_gpio; i++) |
5a3d9651 | 226 | gpio_desc[i].valid = 1; |
7facc2f9 | 227 | |
5a3d9651 EM |
228 | for (i = 0; i <= 15; i++) { |
229 | gpio_desc[i].can_wakeup = 1; | |
230 | gpio_desc[i].mask = GPIO_bit(i); | |
7facc2f9 | 231 | } |
067455aa EM |
232 | |
233 | /* PXA26x has additional 4 GPIOs (86/87/88/89) which has the | |
234 | * direction bit inverted in GPDR2. See PXA26x DM 4.1.1. | |
235 | */ | |
236 | for (i = 86; i <= pxa_last_gpio; i++) | |
237 | gpio_desc[i].dir_inverted = 1; | |
7facc2f9 | 238 | } |
5a3d9651 EM |
239 | #else |
240 | static inline void pxa25x_mfp_init(void) {} | |
7facc2f9 | 241 | #endif /* CONFIG_PXA25x */ |
242 | ||
243 | #ifdef CONFIG_PXA27x | |
c0a596d6 | 244 | static int pxa27x_pkwr_gpio[] = { |
7facc2f9 | 245 | 13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94, |
246 | 95, 96, 97, 98, 99, 100, 101, 102 | |
247 | }; | |
248 | ||
c0a596d6 | 249 | int keypad_set_wake(unsigned int on) |
250 | { | |
251 | unsigned int i, gpio, mask = 0; | |
c09f431c | 252 | struct gpio_desc *d; |
c0a596d6 | 253 | |
254 | for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) { | |
255 | ||
256 | gpio = pxa27x_pkwr_gpio[i]; | |
c09f431c | 257 | d = &gpio_desc[gpio]; |
c0a596d6 | 258 | |
c09f431c EM |
259 | /* skip if configured as generic GPIO */ |
260 | if (MFP_AF(d->config) == 0) | |
261 | continue; | |
262 | ||
263 | if (d->config & MFP_LPM_CAN_WAKEUP) | |
c0a596d6 | 264 | mask |= gpio_desc[gpio].mask; |
265 | } | |
266 | ||
c09f431c EM |
267 | if (on) |
268 | PKWR |= mask; | |
269 | else | |
270 | PKWR &= ~mask; | |
c0a596d6 | 271 | return 0; |
272 | } | |
273 | ||
99687114 RJ |
274 | #define PWER_WEMUX2_GPIO38 (1 << 16) |
275 | #define PWER_WEMUX2_GPIO53 (2 << 16) | |
276 | #define PWER_WEMUX2_GPIO40 (3 << 16) | |
277 | #define PWER_WEMUX2_GPIO36 (4 << 16) | |
278 | #define PWER_WEMUX2_MASK (7 << 16) | |
279 | #define PWER_WEMUX3_GPIO31 (1 << 19) | |
280 | #define PWER_WEMUX3_GPIO113 (2 << 19) | |
281 | #define PWER_WEMUX3_MASK (3 << 19) | |
282 | ||
283 | #define INIT_GPIO_DESC_MUXED(mux, gpio) \ | |
284 | do { \ | |
285 | gpio_desc[(gpio)].can_wakeup = 1; \ | |
286 | gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \ | |
287 | gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \ | |
288 | } while (0) | |
289 | ||
5a3d9651 | 290 | static void __init pxa27x_mfp_init(void) |
7facc2f9 | 291 | { |
292 | int i, gpio; | |
293 | ||
ddd244dd | 294 | for (i = 0; i <= pxa_last_gpio; i++) { |
5a3d9651 EM |
295 | /* skip GPIO2, 5, 6, 7, 8, they are not |
296 | * valid pins allow configuration | |
297 | */ | |
298 | if (i == 2 || i == 5 || i == 6 || i == 7 || i == 8) | |
299 | continue; | |
7facc2f9 | 300 | |
5a3d9651 EM |
301 | gpio_desc[i].valid = 1; |
302 | } | |
7facc2f9 | 303 | |
5a3d9651 EM |
304 | /* Keypad GPIOs */ |
305 | for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) { | |
306 | gpio = pxa27x_pkwr_gpio[i]; | |
307 | gpio_desc[gpio].can_wakeup = 1; | |
308 | gpio_desc[gpio].keypad_gpio = 1; | |
309 | gpio_desc[gpio].mask = 1 << i; | |
310 | } | |
7facc2f9 | 311 | |
5a3d9651 EM |
312 | /* Overwrite GPIO13 as a PWER wakeup source */ |
313 | for (i = 0; i <= 15; i++) { | |
314 | /* skip GPIO2, 5, 6, 7, 8 */ | |
315 | if (GPIO_bit(i) & 0x1e4) | |
316 | continue; | |
7facc2f9 | 317 | |
5a3d9651 EM |
318 | gpio_desc[i].can_wakeup = 1; |
319 | gpio_desc[i].mask = GPIO_bit(i); | |
320 | } | |
321 | ||
322 | gpio_desc[35].can_wakeup = 1; | |
323 | gpio_desc[35].mask = PWER_WE35; | |
324 | ||
99687114 RJ |
325 | INIT_GPIO_DESC_MUXED(WEMUX3, 31); |
326 | INIT_GPIO_DESC_MUXED(WEMUX3, 113); | |
327 | INIT_GPIO_DESC_MUXED(WEMUX2, 38); | |
328 | INIT_GPIO_DESC_MUXED(WEMUX2, 53); | |
329 | INIT_GPIO_DESC_MUXED(WEMUX2, 40); | |
330 | INIT_GPIO_DESC_MUXED(WEMUX2, 36); | |
5a3d9651 EM |
331 | } |
332 | #else | |
333 | static inline void pxa27x_mfp_init(void) {} | |
334 | #endif /* CONFIG_PXA27x */ | |
335 | ||
336 | #ifdef CONFIG_PM | |
337 | static unsigned long saved_gafr[2][4]; | |
338 | static unsigned long saved_gpdr[4]; | |
818bc814 | 339 | static unsigned long saved_pgsr[4]; |
5a3d9651 | 340 | |
2eaa03b5 | 341 | static int pxa2xx_mfp_suspend(void) |
5a3d9651 EM |
342 | { |
343 | int i; | |
344 | ||
1106143d EM |
345 | /* set corresponding PGSR bit of those marked MFP_LPM_KEEP_OUTPUT */ |
346 | for (i = 0; i < pxa_last_gpio; i++) { | |
347 | if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) && | |
348 | (GPDR(i) & GPIO_bit(i))) { | |
349 | if (GPLR(i) & GPIO_bit(i)) | |
350 | PGSR(i) |= GPIO_bit(i); | |
351 | else | |
352 | PGSR(i) &= ~GPIO_bit(i); | |
353 | } | |
354 | } | |
355 | ||
ddd244dd | 356 | for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { |
7facc2f9 | 357 | |
5a3d9651 EM |
358 | saved_gafr[0][i] = GAFR_L(i); |
359 | saved_gafr[1][i] = GAFR_U(i); | |
360 | saved_gpdr[i] = GPDR(i * 32); | |
818bc814 | 361 | saved_pgsr[i] = PGSR(i); |
5a3d9651 EM |
362 | |
363 | GPDR(i * 32) = gpdr_lpm[i]; | |
7facc2f9 | 364 | } |
5a3d9651 EM |
365 | return 0; |
366 | } | |
7facc2f9 | 367 | |
2eaa03b5 | 368 | static void pxa2xx_mfp_resume(void) |
5a3d9651 EM |
369 | { |
370 | int i; | |
371 | ||
ddd244dd | 372 | for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { |
5a3d9651 EM |
373 | GAFR_L(i) = saved_gafr[0][i]; |
374 | GAFR_U(i) = saved_gafr[1][i]; | |
375 | GPDR(i * 32) = saved_gpdr[i]; | |
818bc814 | 376 | PGSR(i) = saved_pgsr[i]; |
5a3d9651 EM |
377 | } |
378 | PSSR = PSSR_RDH | PSSR_PH; | |
7facc2f9 | 379 | } |
5a3d9651 EM |
380 | #else |
381 | #define pxa2xx_mfp_suspend NULL | |
382 | #define pxa2xx_mfp_resume NULL | |
383 | #endif | |
384 | ||
2eaa03b5 | 385 | struct syscore_ops pxa2xx_mfp_syscore_ops = { |
5a3d9651 EM |
386 | .suspend = pxa2xx_mfp_suspend, |
387 | .resume = pxa2xx_mfp_resume, | |
388 | }; | |
389 | ||
390 | static int __init pxa2xx_mfp_init(void) | |
391 | { | |
392 | int i; | |
393 | ||
e7f3c600 EM |
394 | if (!cpu_is_pxa2xx()) |
395 | return 0; | |
396 | ||
5a3d9651 EM |
397 | if (cpu_is_pxa25x()) |
398 | pxa25x_mfp_init(); | |
399 | ||
400 | if (cpu_is_pxa27x()) | |
401 | pxa27x_mfp_init(); | |
402 | ||
866bd435 TC |
403 | /* clear RDH bit to enable GPIO receivers after reset/sleep exit */ |
404 | PSSR = PSSR_RDH; | |
405 | ||
5a3d9651 | 406 | /* initialize gafr_run[], pgsr_lpm[] from existing values */ |
ddd244dd | 407 | for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) |
5a3d9651 EM |
408 | gpdr_lpm[i] = GPDR(i * 32); |
409 | ||
2eaa03b5 | 410 | return 0; |
5a3d9651 EM |
411 | } |
412 | postcore_initcall(pxa2xx_mfp_init); |