Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa25x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA21x/25x/26x variants. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * Since this file should be linked before any other machine specific file, | |
15 | * the __initcall() here will be executed first. This serves as default | |
16 | * initialization stuff for PXA machines which can be overridden later if | |
17 | * need be. | |
18 | */ | |
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
34f3231f | 22 | #include <linux/platform_device.h> |
95d9ffbe | 23 | #include <linux/suspend.h> |
c0165504 | 24 | #include <linux/sysdev.h> |
1da177e4 LT |
25 | |
26 | #include <asm/hardware.h> | |
cd49104d | 27 | #include <asm/arch/irqs.h> |
1da177e4 | 28 | #include <asm/arch/pxa-regs.h> |
c0a596d6 | 29 | #include <asm/arch/mfp-pxa25x.h> |
e176bb05 | 30 | #include <asm/arch/pm.h> |
f53f066c | 31 | #include <asm/arch/dma.h> |
1da177e4 LT |
32 | |
33 | #include "generic.h" | |
46c41e62 | 34 | #include "devices.h" |
a6dba20c | 35 | #include "clock.h" |
1da177e4 LT |
36 | |
37 | /* | |
38 | * Various clock factors driven by the CCCR register. | |
39 | */ | |
40 | ||
41 | /* Crystal Frequency to Memory Frequency Multiplier (L) */ | |
42 | static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; | |
43 | ||
44 | /* Memory Frequency to Run Mode Frequency Multiplier (M) */ | |
45 | static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; | |
46 | ||
47 | /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ | |
48 | /* Note: we store the value N * 2 here. */ | |
49 | static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; | |
50 | ||
51 | /* Crystal clock */ | |
52 | #define BASE_CLK 3686400 | |
53 | ||
54 | /* | |
55 | * Get the clock frequency as reflected by CCCR and the turbo flag. | |
56 | * We assume these values have been applied via a fcs. | |
57 | * If info is not 0 we also display the current settings. | |
58 | */ | |
15a40333 | 59 | unsigned int pxa25x_get_clk_frequency_khz(int info) |
1da177e4 LT |
60 | { |
61 | unsigned long cccr, turbo; | |
62 | unsigned int l, L, m, M, n2, N; | |
63 | ||
64 | cccr = CCCR; | |
65 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); | |
66 | ||
67 | l = L_clk_mult[(cccr >> 0) & 0x1f]; | |
68 | m = M_clk_mult[(cccr >> 5) & 0x03]; | |
69 | n2 = N2_clk_mult[(cccr >> 7) & 0x07]; | |
70 | ||
71 | L = l * BASE_CLK; | |
72 | M = m * L; | |
73 | N = n2 * M / 2; | |
74 | ||
75 | if(info) | |
76 | { | |
77 | L += 5000; | |
78 | printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n", | |
79 | L / 1000000, (L % 1000000) / 10000, l ); | |
80 | M += 5000; | |
81 | printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", | |
82 | M / 1000000, (M % 1000000) / 10000, m ); | |
83 | N += 5000; | |
84 | printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", | |
85 | N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5, | |
86 | (turbo & 1) ? "" : "in" ); | |
87 | } | |
88 | ||
89 | return (turbo & 1) ? (N/1000) : (M/1000); | |
90 | } | |
91 | ||
1da177e4 LT |
92 | /* |
93 | * Return the current memory clock frequency in units of 10kHz | |
94 | */ | |
15a40333 | 95 | unsigned int pxa25x_get_memclk_frequency_10khz(void) |
1da177e4 LT |
96 | { |
97 | return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; | |
98 | } | |
99 | ||
a6dba20c RK |
100 | static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) |
101 | { | |
102 | return pxa25x_get_memclk_frequency_10khz() * 10000; | |
103 | } | |
104 | ||
105 | static const struct clkops clk_pxa25x_lcd_ops = { | |
106 | .enable = clk_cken_enable, | |
107 | .disable = clk_cken_disable, | |
108 | .getrate = clk_pxa25x_lcd_getrate, | |
109 | }; | |
110 | ||
111 | /* | |
112 | * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) | |
113 | * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz | |
114 | * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) | |
115 | */ | |
e01dbdb4 DB |
116 | static struct clk pxa25x_hwuart_clk = |
117 | INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) | |
118 | ; | |
119 | ||
a6dba20c RK |
120 | static struct clk pxa25x_clks[] = { |
121 | INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), | |
122 | INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), | |
123 | INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), | |
435b6e94 | 124 | INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), |
a6dba20c RK |
125 | INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), |
126 | INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), | |
127 | INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), | |
d8e0db11 | 128 | |
129 | INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), | |
130 | INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), | |
131 | INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), | |
132 | ||
27b98a67 MB |
133 | INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), |
134 | ||
a6dba20c RK |
135 | /* |
136 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), | |
137 | INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), | |
a6dba20c | 138 | INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), |
a6dba20c | 139 | */ |
435b6e94 | 140 | INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), |
a6dba20c RK |
141 | }; |
142 | ||
a8fa3f0c | 143 | #ifdef CONFIG_PM |
8775420d | 144 | |
711be5cc EM |
145 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
146 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
147 | ||
711be5cc EM |
148 | /* |
149 | * List of global PXA peripheral registers to preserve. | |
150 | * More ones like CP and general purpose register values are preserved | |
151 | * with the stack pointer in sleep.S. | |
152 | */ | |
649de51b | 153 | enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, |
711be5cc EM |
154 | |
155 | SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, | |
156 | SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, | |
157 | SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, | |
158 | ||
159 | SLEEP_SAVE_PSTR, | |
160 | ||
711be5cc EM |
161 | SLEEP_SAVE_CKEN, |
162 | ||
649de51b | 163 | SLEEP_SAVE_COUNT |
711be5cc EM |
164 | }; |
165 | ||
166 | ||
167 | static void pxa25x_cpu_pm_save(unsigned long *sleep_save) | |
168 | { | |
711be5cc EM |
169 | SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); |
170 | ||
171 | SAVE(GAFR0_L); SAVE(GAFR0_U); | |
172 | SAVE(GAFR1_L); SAVE(GAFR1_U); | |
173 | SAVE(GAFR2_L); SAVE(GAFR2_U); | |
174 | ||
711be5cc EM |
175 | SAVE(CKEN); |
176 | SAVE(PSTR); | |
56b11288 RP |
177 | |
178 | /* Clear GPIO transition detect bits */ | |
179 | GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; | |
711be5cc EM |
180 | } |
181 | ||
182 | static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) | |
183 | { | |
56b11288 RP |
184 | /* ensure not to come back here if it wasn't intended */ |
185 | PSPR = 0; | |
186 | ||
711be5cc | 187 | /* restore registers */ |
711be5cc EM |
188 | RESTORE(GAFR0_L); RESTORE(GAFR0_U); |
189 | RESTORE(GAFR1_L); RESTORE(GAFR1_U); | |
190 | RESTORE(GAFR2_L); RESTORE(GAFR2_U); | |
711be5cc EM |
191 | RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); |
192 | ||
56b11288 RP |
193 | PSSR = PSSR_RDH | PSSR_PH; |
194 | ||
711be5cc | 195 | RESTORE(CKEN); |
711be5cc EM |
196 | RESTORE(PSTR); |
197 | } | |
198 | ||
199 | static void pxa25x_cpu_pm_enter(suspend_state_t state) | |
8775420d | 200 | { |
dc38e2ad RK |
201 | /* Clear reset status */ |
202 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
203 | ||
8775420d TP |
204 | switch (state) { |
205 | case PM_SUSPEND_MEM: | |
206 | /* set resume return address */ | |
207 | PSPR = virt_to_phys(pxa_cpu_resume); | |
b750a093 | 208 | pxa25x_cpu_suspend(PWRMODE_SLEEP); |
8775420d TP |
209 | break; |
210 | } | |
211 | } | |
a8fa3f0c | 212 | |
711be5cc | 213 | static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { |
649de51b | 214 | .save_count = SLEEP_SAVE_COUNT, |
26398a70 | 215 | .valid = suspend_valid_only_mem, |
711be5cc EM |
216 | .save = pxa25x_cpu_pm_save, |
217 | .restore = pxa25x_cpu_pm_restore, | |
218 | .enter = pxa25x_cpu_pm_enter, | |
e176bb05 | 219 | }; |
711be5cc EM |
220 | |
221 | static void __init pxa25x_init_pm(void) | |
222 | { | |
223 | pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; | |
224 | } | |
f79299ca | 225 | #else |
226 | static inline void pxa25x_init_pm(void) {} | |
a8fa3f0c | 227 | #endif |
e176bb05 | 228 | |
c95530c7 | 229 | /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm |
230 | */ | |
231 | ||
232 | static int pxa25x_set_wake(unsigned int irq, unsigned int on) | |
233 | { | |
234 | int gpio = IRQ_TO_GPIO(irq); | |
c0a596d6 | 235 | uint32_t mask = 0; |
236 | ||
237 | if (gpio >= 0 && gpio < 85) | |
238 | return gpio_set_wake(gpio, on); | |
c95530c7 | 239 | |
240 | if (irq == IRQ_RTCAlrm) { | |
241 | mask = PWER_RTC; | |
242 | goto set_pwer; | |
243 | } | |
244 | ||
245 | return -EINVAL; | |
246 | ||
247 | set_pwer: | |
248 | if (on) | |
249 | PWER |= mask; | |
250 | else | |
251 | PWER &=~mask; | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
cd49104d EM |
256 | void __init pxa25x_init_irq(void) |
257 | { | |
b9e25ace | 258 | pxa_init_irq(32, pxa25x_set_wake); |
259 | pxa_init_gpio(85, pxa25x_set_wake); | |
cd49104d EM |
260 | } |
261 | ||
34f3231f | 262 | static struct platform_device *pxa25x_devices[] __initdata = { |
e09d02e1 | 263 | &pxa_device_udc, |
e09d02e1 EM |
264 | &pxa_device_ffuart, |
265 | &pxa_device_btuart, | |
266 | &pxa_device_stuart, | |
e09d02e1 | 267 | &pxa_device_i2s, |
e09d02e1 | 268 | &pxa_device_rtc, |
d8e0db11 | 269 | &pxa25x_device_ssp, |
270 | &pxa25x_device_nssp, | |
271 | &pxa25x_device_assp, | |
34f3231f RK |
272 | }; |
273 | ||
c0165504 | 274 | static struct sys_device pxa25x_sysdev[] = { |
275 | { | |
276 | .cls = &pxa_irq_sysclass, | |
16dfdbf0 | 277 | }, { |
278 | .cls = &pxa_gpio_sysclass, | |
c0165504 | 279 | }, |
280 | }; | |
281 | ||
e176bb05 RK |
282 | static int __init pxa25x_init(void) |
283 | { | |
c0165504 | 284 | int i, ret = 0; |
f53f066c | 285 | |
e01dbdb4 DB |
286 | /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ |
287 | if (cpu_is_pxa25x()) | |
288 | clks_register(&pxa25x_hwuart_clk, 1); | |
289 | ||
e176bb05 | 290 | if (cpu_is_pxa21x() || cpu_is_pxa25x()) { |
a6dba20c RK |
291 | clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); |
292 | ||
f53f066c EM |
293 | if ((ret = pxa_init_dma(16))) |
294 | return ret; | |
f79299ca | 295 | |
711be5cc | 296 | pxa25x_init_pm(); |
f79299ca | 297 | |
c0165504 | 298 | for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) { |
299 | ret = sysdev_register(&pxa25x_sysdev[i]); | |
300 | if (ret) | |
301 | pr_err("failed to register sysdev[%d]\n", i); | |
302 | } | |
303 | ||
34f3231f RK |
304 | ret = platform_add_devices(pxa25x_devices, |
305 | ARRAY_SIZE(pxa25x_devices)); | |
c0165504 | 306 | if (ret) |
307 | return ret; | |
e176bb05 | 308 | } |
c0165504 | 309 | |
34f3231f RK |
310 | /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ |
311 | if (cpu_is_pxa25x()) | |
e09d02e1 | 312 | ret = platform_device_register(&pxa_device_hwuart); |
34f3231f RK |
313 | |
314 | return ret; | |
e176bb05 RK |
315 | } |
316 | ||
1c104e0e | 317 | postcore_initcall(pxa25x_init); |