Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa27x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Nov 05, 2002 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA27x aka Bulverde. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
2f8163ba | 14 | #include <linux/gpio.h> |
157d2644 | 15 | #include <linux/gpio-pxa.h> |
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/kernel.h> | |
18 | #include <linux/init.h> | |
95d9ffbe | 19 | #include <linux/suspend.h> |
d052d1be | 20 | #include <linux/platform_device.h> |
2eaa03b5 | 21 | #include <linux/syscore_ops.h> |
ad68bb9f | 22 | #include <linux/io.h> |
a3f4c927 | 23 | #include <linux/irq.h> |
b459396e | 24 | #include <linux/i2c/pxa-i2c.h> |
1da177e4 | 25 | |
851982c1 | 26 | #include <asm/mach/map.h> |
a09e64fb | 27 | #include <mach/hardware.h> |
1da177e4 | 28 | #include <asm/irq.h> |
2c74a0ce | 29 | #include <asm/suspend.h> |
a09e64fb | 30 | #include <mach/irqs.h> |
51c62982 | 31 | #include <mach/pxa27x.h> |
afd2fc02 | 32 | #include <mach/reset.h> |
293b2da1 | 33 | #include <linux/platform_data/usb-ohci-pxa27x.h> |
a09e64fb RK |
34 | #include <mach/pm.h> |
35 | #include <mach/dma.h> | |
ad68bb9f MV |
36 | #include <mach/smemc.h> |
37 | ||
1da177e4 | 38 | #include "generic.h" |
46c41e62 | 39 | #include "devices.h" |
48a17db2 RJ |
40 | #include <linux/clk-provider.h> |
41 | #include <linux/clkdev.h> | |
1da177e4 | 42 | |
0cb0b0d3 EM |
43 | void pxa27x_clear_otgph(void) |
44 | { | |
45 | if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH)) | |
46 | PSSR |= PSSR_OTGPH; | |
47 | } | |
48 | EXPORT_SYMBOL(pxa27x_clear_otgph); | |
49 | ||
fb1bf8cd | 50 | static unsigned long ac97_reset_config[] = { |
3b4bc7bc | 51 | GPIO113_AC97_nRESET_GPIO_HIGH, |
5e16e3cb | 52 | GPIO113_AC97_nRESET, |
3b4bc7bc | 53 | GPIO95_AC97_nRESET_GPIO_HIGH, |
5e16e3cb | 54 | GPIO95_AC97_nRESET, |
fb1bf8cd EM |
55 | }; |
56 | ||
053fe0f1 | 57 | void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio) |
fb1bf8cd | 58 | { |
053fe0f1 MD |
59 | /* |
60 | * This helper function is used to work around a bug in the pxa27x's | |
61 | * ac97 controller during a warm reset. The configuration of the | |
62 | * reset_gpio is changed as follows: | |
63 | * to_gpio == true: configured to generic output gpio and driven high | |
64 | * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET | |
65 | */ | |
66 | ||
fb1bf8cd | 67 | if (reset_gpio == 113) |
053fe0f1 MD |
68 | pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] : |
69 | &ac97_reset_config[1], 1); | |
fb1bf8cd EM |
70 | |
71 | if (reset_gpio == 95) | |
053fe0f1 MD |
72 | pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] : |
73 | &ac97_reset_config[3], 1); | |
fb1bf8cd | 74 | } |
053fe0f1 | 75 | EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset); |
fb1bf8cd | 76 | |
a8fa3f0c NP |
77 | #ifdef CONFIG_PM |
78 | ||
711be5cc EM |
79 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
80 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
81 | ||
d082d36e MR |
82 | /* |
83 | * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM | |
84 | */ | |
85 | static unsigned int pwrmode = PWRMODE_SLEEP; | |
86 | ||
87 | int __init pxa27x_set_pwrmode(unsigned int mode) | |
88 | { | |
89 | switch (mode) { | |
90 | case PWRMODE_SLEEP: | |
91 | case PWRMODE_DEEPSLEEP: | |
92 | pwrmode = mode; | |
93 | return 0; | |
94 | } | |
95 | ||
96 | return -EINVAL; | |
97 | } | |
98 | ||
711be5cc EM |
99 | /* |
100 | * List of global PXA peripheral registers to preserve. | |
101 | * More ones like CP and general purpose register values are preserved | |
102 | * with the stack pointer in sleep.S. | |
103 | */ | |
5a3d9651 | 104 | enum { |
711be5cc | 105 | SLEEP_SAVE_PSTR, |
711be5cc | 106 | SLEEP_SAVE_MDREFR, |
5a3d9651 | 107 | SLEEP_SAVE_PCFR, |
649de51b | 108 | SLEEP_SAVE_COUNT |
711be5cc EM |
109 | }; |
110 | ||
111 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) | |
112 | { | |
ad68bb9f | 113 | sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); |
5a3d9651 | 114 | SAVE(PCFR); |
711be5cc | 115 | |
711be5cc | 116 | SAVE(PSTR); |
711be5cc EM |
117 | } |
118 | ||
119 | void pxa27x_cpu_pm_restore(unsigned long *sleep_save) | |
120 | { | |
ad68bb9f | 121 | __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); |
5a3d9651 | 122 | RESTORE(PCFR); |
711be5cc EM |
123 | |
124 | PSSR = PSSR_RDH | PSSR_PH; | |
125 | ||
711be5cc EM |
126 | RESTORE(PSTR); |
127 | } | |
128 | ||
129 | void pxa27x_cpu_pm_enter(suspend_state_t state) | |
8775420d TP |
130 | { |
131 | extern void pxa_cpu_standby(void); | |
a9503d21 RK |
132 | #ifndef CONFIG_IWMMXT |
133 | u64 acc0; | |
134 | ||
135 | asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0)); | |
136 | #endif | |
8775420d | 137 | |
8775420d TP |
138 | /* ensure voltage-change sequencer not initiated, which hangs */ |
139 | PCFR &= ~PCFR_FVC; | |
140 | ||
141 | /* Clear edge-detect status register. */ | |
142 | PEDR = 0xDF12FE1B; | |
143 | ||
dc38e2ad RK |
144 | /* Clear reset status */ |
145 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
146 | ||
8775420d | 147 | switch (state) { |
26705ca4 TP |
148 | case PM_SUSPEND_STANDBY: |
149 | pxa_cpu_standby(); | |
150 | break; | |
8775420d | 151 | case PM_SUSPEND_MEM: |
2c74a0ce | 152 | cpu_suspend(pwrmode, pxa27x_finish_suspend); |
a9503d21 RK |
153 | #ifndef CONFIG_IWMMXT |
154 | asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0)); | |
155 | #endif | |
8775420d TP |
156 | break; |
157 | } | |
158 | } | |
1da177e4 | 159 | |
711be5cc | 160 | static int pxa27x_cpu_pm_valid(suspend_state_t state) |
88dfe98c RK |
161 | { |
162 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
163 | } | |
164 | ||
4104980a RK |
165 | static int pxa27x_cpu_pm_prepare(void) |
166 | { | |
167 | /* set resume return address */ | |
4f5ad99b | 168 | PSPR = virt_to_phys(cpu_resume); |
4104980a RK |
169 | return 0; |
170 | } | |
171 | ||
172 | static void pxa27x_cpu_pm_finish(void) | |
173 | { | |
174 | /* ensure not to come back here if it wasn't intended */ | |
175 | PSPR = 0; | |
176 | } | |
177 | ||
711be5cc | 178 | static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { |
649de51b | 179 | .save_count = SLEEP_SAVE_COUNT, |
711be5cc EM |
180 | .save = pxa27x_cpu_pm_save, |
181 | .restore = pxa27x_cpu_pm_restore, | |
182 | .valid = pxa27x_cpu_pm_valid, | |
183 | .enter = pxa27x_cpu_pm_enter, | |
4104980a RK |
184 | .prepare = pxa27x_cpu_pm_prepare, |
185 | .finish = pxa27x_cpu_pm_finish, | |
e176bb05 | 186 | }; |
711be5cc EM |
187 | |
188 | static void __init pxa27x_init_pm(void) | |
189 | { | |
190 | pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; | |
191 | } | |
f79299ca | 192 | #else |
193 | static inline void pxa27x_init_pm(void) {} | |
a8fa3f0c NP |
194 | #endif |
195 | ||
c95530c7 | 196 | /* PXA27x: Various gpios can issue wakeup events. This logic only |
197 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | |
198 | */ | |
a3f4c927 | 199 | static int pxa27x_set_wake(struct irq_data *d, unsigned int on) |
c95530c7 | 200 | { |
4929f5a8 | 201 | int gpio = pxa_irq_to_gpio(d->irq); |
c95530c7 | 202 | uint32_t mask; |
203 | ||
c0a596d6 | 204 | if (gpio >= 0 && gpio < 128) |
205 | return gpio_set_wake(gpio, on); | |
c95530c7 | 206 | |
a3f4c927 | 207 | if (d->irq == IRQ_KEYPAD) |
c0a596d6 | 208 | return keypad_set_wake(on); |
c95530c7 | 209 | |
a3f4c927 | 210 | switch (d->irq) { |
c95530c7 | 211 | case IRQ_RTCAlrm: |
212 | mask = PWER_RTC; | |
213 | break; | |
214 | case IRQ_USB: | |
215 | mask = 1u << 26; | |
216 | break; | |
217 | default: | |
218 | return -EINVAL; | |
219 | } | |
220 | ||
c95530c7 | 221 | if (on) |
222 | PWER |= mask; | |
223 | else | |
224 | PWER &=~mask; | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | void __init pxa27x_init_irq(void) | |
230 | { | |
b9e25ace | 231 | pxa_init_irq(34, pxa27x_set_wake); |
c95530c7 | 232 | } |
233 | ||
ef6dbda6 RJ |
234 | void __init pxa27x_dt_init_irq(void) |
235 | { | |
236 | if (IS_ENABLED(CONFIG_OF)) | |
237 | pxa_dt_irq_init(pxa27x_set_wake); | |
238 | } | |
239 | ||
851982c1 MV |
240 | static struct map_desc pxa27x_io_desc[] __initdata = { |
241 | { /* Mem Ctl */ | |
97b09da4 | 242 | .virtual = (unsigned long)SMEMC_VIRT, |
ad68bb9f | 243 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), |
0e32986c | 244 | .length = SMEMC_SIZE, |
851982c1 | 245 | .type = MT_DEVICE |
b10f1c83 LP |
246 | }, { /* UNCACHED_PHYS_0 */ |
247 | .virtual = UNCACHED_PHYS_0, | |
248 | .pfn = __phys_to_pfn(0x00000000), | |
249 | .length = UNCACHED_PHYS_0_SIZE, | |
250 | .type = MT_DEVICE | |
851982c1 MV |
251 | }, |
252 | }; | |
253 | ||
254 | void __init pxa27x_map_io(void) | |
255 | { | |
256 | pxa_map_io(); | |
257 | iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc)); | |
258 | pxa27x_get_clk_frequency_khz(1); | |
259 | } | |
260 | ||
1da177e4 LT |
261 | /* |
262 | * device registration specific to PXA27x. | |
263 | */ | |
9ba63c4f | 264 | void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
b7a36701 | 265 | { |
bc3a5959 PZ |
266 | local_irq_disable(); |
267 | PCFR |= PCFR_PI2CEN; | |
268 | local_irq_enable(); | |
14758220 | 269 | pxa_register_device(&pxa27x_device_i2c_power, info); |
b7a36701 MR |
270 | } |
271 | ||
b95ace54 | 272 | static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = { |
b8f649f1 HZ |
273 | .irq_base = PXA_GPIO_TO_IRQ(0), |
274 | .gpio_set_wake = gpio_set_wake, | |
b95ace54 RJ |
275 | }; |
276 | ||
1da177e4 | 277 | static struct platform_device *devices[] __initdata = { |
7a857620 | 278 | &pxa27x_device_udc, |
09a5358d | 279 | &pxa_device_pmu, |
e09d02e1 | 280 | &pxa_device_i2s, |
f0fba2ad LG |
281 | &pxa_device_asoc_ssp1, |
282 | &pxa_device_asoc_ssp2, | |
283 | &pxa_device_asoc_ssp3, | |
284 | &pxa_device_asoc_platform, | |
e09d02e1 | 285 | &pxa_device_rtc, |
d8e0db11 | 286 | &pxa27x_device_ssp1, |
287 | &pxa27x_device_ssp2, | |
288 | &pxa27x_device_ssp3, | |
75540c1a | 289 | &pxa27x_device_pwm0, |
290 | &pxa27x_device_pwm1, | |
1da177e4 LT |
291 | }; |
292 | ||
293 | static int __init pxa27x_init(void) | |
294 | { | |
2eaa03b5 | 295 | int ret = 0; |
c0165504 | 296 | |
e176bb05 | 297 | if (cpu_is_pxa27x()) { |
04fef228 EM |
298 | |
299 | reset_status = RCSR; | |
300 | ||
fef1f99a | 301 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
f53f066c | 302 | return ret; |
f79299ca | 303 | |
711be5cc | 304 | pxa27x_init_pm(); |
f79299ca | 305 | |
2eaa03b5 RW |
306 | register_syscore_ops(&pxa_irq_syscore_ops); |
307 | register_syscore_ops(&pxa2xx_mfp_syscore_ops); | |
c0165504 | 308 | |
24e32a55 RJ |
309 | if (!of_have_populated_dt()) { |
310 | pxa_register_device(&pxa27x_device_gpio, | |
311 | &pxa27x_gpio_info); | |
4be0856f | 312 | pxa2xx_set_dmac_info(32); |
24e32a55 RJ |
313 | ret = platform_add_devices(devices, |
314 | ARRAY_SIZE(devices)); | |
315 | } | |
e176bb05 | 316 | } |
c0165504 | 317 | |
e176bb05 | 318 | return ret; |
1da177e4 LT |
319 | } |
320 | ||
1c104e0e | 321 | postcore_initcall(pxa27x_init); |