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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-pxa/pxa27x.c | |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Nov 05, 2002 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * Code specific to PXA27x aka Bulverde. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
95d9ffbe | 17 | #include <linux/suspend.h> |
d052d1be | 18 | #include <linux/platform_device.h> |
c0165504 | 19 | #include <linux/sysdev.h> |
1da177e4 | 20 | |
a09e64fb | 21 | #include <mach/hardware.h> |
1da177e4 | 22 | #include <asm/irq.h> |
a09e64fb | 23 | #include <mach/irqs.h> |
a58fbcd8 | 24 | #include <mach/gpio.h> |
51c62982 | 25 | #include <mach/pxa27x.h> |
afd2fc02 | 26 | #include <mach/reset.h> |
a09e64fb RK |
27 | #include <mach/ohci.h> |
28 | #include <mach/pm.h> | |
29 | #include <mach/dma.h> | |
f0a83701 | 30 | #include <plat/i2c.h> |
1da177e4 LT |
31 | |
32 | #include "generic.h" | |
46c41e62 | 33 | #include "devices.h" |
a6dba20c | 34 | #include "clock.h" |
1da177e4 | 35 | |
0cb0b0d3 EM |
36 | void pxa27x_clear_otgph(void) |
37 | { | |
38 | if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH)) | |
39 | PSSR |= PSSR_OTGPH; | |
40 | } | |
41 | EXPORT_SYMBOL(pxa27x_clear_otgph); | |
42 | ||
fb1bf8cd EM |
43 | static unsigned long ac97_reset_config[] = { |
44 | GPIO95_AC97_nRESET, | |
45 | GPIO95_GPIO, | |
46 | GPIO113_AC97_nRESET, | |
47 | GPIO113_GPIO, | |
48 | }; | |
49 | ||
50 | void pxa27x_assert_ac97reset(int reset_gpio, int on) | |
51 | { | |
52 | if (reset_gpio == 113) | |
53 | pxa2xx_mfp_config(on ? &ac97_reset_config[0] : | |
54 | &ac97_reset_config[1], 1); | |
55 | ||
56 | if (reset_gpio == 95) | |
57 | pxa2xx_mfp_config(on ? &ac97_reset_config[2] : | |
58 | &ac97_reset_config[3], 1); | |
59 | } | |
60 | EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset); | |
61 | ||
1da177e4 LT |
62 | /* Crystal clock: 13MHz */ |
63 | #define BASE_CLK 13000000 | |
64 | ||
65 | /* | |
66 | * Get the clock frequency as reflected by CCSR and the turbo flag. | |
67 | * We assume these values have been applied via a fcs. | |
68 | * If info is not 0 we also display the current settings. | |
69 | */ | |
15a40333 | 70 | unsigned int pxa27x_get_clk_frequency_khz(int info) |
1da177e4 LT |
71 | { |
72 | unsigned long ccsr, clkcfg; | |
73 | unsigned int l, L, m, M, n2, N, S; | |
74 | int cccr_a, t, ht, b; | |
75 | ||
76 | ccsr = CCSR; | |
77 | cccr_a = CCCR & (1 << 25); | |
78 | ||
79 | /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ | |
80 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); | |
afe5df20 | 81 | t = clkcfg & (1 << 0); |
1da177e4 LT |
82 | ht = clkcfg & (1 << 2); |
83 | b = clkcfg & (1 << 3); | |
84 | ||
85 | l = ccsr & 0x1f; | |
86 | n2 = (ccsr>>7) & 0xf; | |
87 | m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; | |
88 | ||
89 | L = l * BASE_CLK; | |
90 | N = (L * n2) / 2; | |
91 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); | |
92 | S = (b) ? L : (L/2); | |
93 | ||
94 | if (info) { | |
95 | printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", | |
96 | L / 1000000, (L % 1000000) / 10000, l ); | |
97 | printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", | |
98 | N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5, | |
99 | (t) ? "" : "in" ); | |
100 | printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n", | |
101 | M / 1000000, (M % 1000000) / 10000, m ); | |
102 | printk( KERN_INFO "System bus clock: %d.%02dMHz \n", | |
103 | S / 1000000, (S % 1000000) / 10000 ); | |
104 | } | |
105 | ||
106 | return (t) ? (N/1000) : (L/1000); | |
107 | } | |
108 | ||
109 | /* | |
110 | * Return the current mem clock frequency in units of 10kHz as | |
111 | * reflected by CCCR[A], B, and L | |
112 | */ | |
15a40333 | 113 | unsigned int pxa27x_get_memclk_frequency_10khz(void) |
1da177e4 LT |
114 | { |
115 | unsigned long ccsr, clkcfg; | |
116 | unsigned int l, L, m, M; | |
117 | int cccr_a, b; | |
118 | ||
119 | ccsr = CCSR; | |
120 | cccr_a = CCCR & (1 << 25); | |
121 | ||
122 | /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ | |
123 | asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); | |
124 | b = clkcfg & (1 << 3); | |
125 | ||
126 | l = ccsr & 0x1f; | |
127 | m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; | |
128 | ||
129 | L = l * BASE_CLK; | |
130 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); | |
131 | ||
132 | return (M / 10000); | |
133 | } | |
134 | ||
135 | /* | |
136 | * Return the current LCD clock frequency in units of 10kHz as | |
137 | */ | |
a88a447d | 138 | static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) |
1da177e4 LT |
139 | { |
140 | unsigned long ccsr; | |
141 | unsigned int l, L, k, K; | |
142 | ||
143 | ccsr = CCSR; | |
144 | ||
145 | l = ccsr & 0x1f; | |
146 | k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; | |
147 | ||
148 | L = l * BASE_CLK; | |
149 | K = L / k; | |
150 | ||
151 | return (K / 10000); | |
152 | } | |
153 | ||
a6dba20c RK |
154 | static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) |
155 | { | |
156 | return pxa27x_get_lcdclk_frequency_10khz() * 10000; | |
157 | } | |
158 | ||
159 | static const struct clkops clk_pxa27x_lcd_ops = { | |
160 | .enable = clk_cken_enable, | |
161 | .disable = clk_cken_disable, | |
162 | .getrate = clk_pxa27x_lcd_getrate, | |
163 | }; | |
164 | ||
8c3abc7d RK |
165 | static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); |
166 | static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); | |
167 | static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); | |
168 | static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1); | |
169 | static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1); | |
170 | static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0); | |
171 | static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0); | |
172 | static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5); | |
173 | static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0); | |
174 | static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0); | |
175 | static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); | |
176 | static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); | |
177 | static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); | |
178 | static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); | |
179 | static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); | |
180 | static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); | |
181 | static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); | |
182 | static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); | |
183 | static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0); | |
184 | static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); | |
185 | static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0); | |
186 | static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0); | |
187 | static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); | |
188 | static DEFINE_CKEN(pxa27x_im, IM, 0, 0); | |
189 | static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0); | |
190 | ||
191 | static struct clk_lookup pxa27x_clkregs[] = { | |
192 | INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), | |
193 | INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL), | |
194 | INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL), | |
195 | INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL), | |
196 | INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL), | |
197 | INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL), | |
198 | INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL), | |
199 | INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL), | |
200 | INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL), | |
201 | INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"), | |
202 | INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"), | |
203 | INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL), | |
204 | INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL), | |
205 | INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL), | |
206 | INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL), | |
207 | INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL), | |
208 | INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL), | |
209 | INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL), | |
210 | INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL), | |
211 | INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"), | |
212 | INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"), | |
213 | INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"), | |
214 | INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"), | |
215 | INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), | |
216 | INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), | |
217 | INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), | |
a6dba20c RK |
218 | }; |
219 | ||
a8fa3f0c NP |
220 | #ifdef CONFIG_PM |
221 | ||
711be5cc EM |
222 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
223 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
224 | ||
d082d36e MR |
225 | /* |
226 | * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM | |
227 | */ | |
228 | static unsigned int pwrmode = PWRMODE_SLEEP; | |
229 | ||
230 | int __init pxa27x_set_pwrmode(unsigned int mode) | |
231 | { | |
232 | switch (mode) { | |
233 | case PWRMODE_SLEEP: | |
234 | case PWRMODE_DEEPSLEEP: | |
235 | pwrmode = mode; | |
236 | return 0; | |
237 | } | |
238 | ||
239 | return -EINVAL; | |
240 | } | |
241 | ||
711be5cc EM |
242 | /* |
243 | * List of global PXA peripheral registers to preserve. | |
244 | * More ones like CP and general purpose register values are preserved | |
245 | * with the stack pointer in sleep.S. | |
246 | */ | |
5a3d9651 | 247 | enum { |
711be5cc | 248 | SLEEP_SAVE_PSTR, |
711be5cc | 249 | SLEEP_SAVE_CKEN, |
711be5cc | 250 | SLEEP_SAVE_MDREFR, |
5a3d9651 | 251 | SLEEP_SAVE_PCFR, |
649de51b | 252 | SLEEP_SAVE_COUNT |
711be5cc EM |
253 | }; |
254 | ||
255 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) | |
256 | { | |
711be5cc | 257 | SAVE(MDREFR); |
5a3d9651 | 258 | SAVE(PCFR); |
711be5cc | 259 | |
711be5cc EM |
260 | SAVE(CKEN); |
261 | SAVE(PSTR); | |
711be5cc EM |
262 | } |
263 | ||
264 | void pxa27x_cpu_pm_restore(unsigned long *sleep_save) | |
265 | { | |
711be5cc | 266 | RESTORE(MDREFR); |
5a3d9651 | 267 | RESTORE(PCFR); |
711be5cc EM |
268 | |
269 | PSSR = PSSR_RDH | PSSR_PH; | |
270 | ||
271 | RESTORE(CKEN); | |
711be5cc EM |
272 | RESTORE(PSTR); |
273 | } | |
274 | ||
275 | void pxa27x_cpu_pm_enter(suspend_state_t state) | |
8775420d TP |
276 | { |
277 | extern void pxa_cpu_standby(void); | |
8775420d | 278 | |
8775420d TP |
279 | /* ensure voltage-change sequencer not initiated, which hangs */ |
280 | PCFR &= ~PCFR_FVC; | |
281 | ||
282 | /* Clear edge-detect status register. */ | |
283 | PEDR = 0xDF12FE1B; | |
284 | ||
dc38e2ad RK |
285 | /* Clear reset status */ |
286 | RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; | |
287 | ||
8775420d | 288 | switch (state) { |
26705ca4 TP |
289 | case PM_SUSPEND_STANDBY: |
290 | pxa_cpu_standby(); | |
291 | break; | |
8775420d | 292 | case PM_SUSPEND_MEM: |
d082d36e | 293 | pxa27x_cpu_suspend(pwrmode); |
8775420d TP |
294 | break; |
295 | } | |
296 | } | |
1da177e4 | 297 | |
711be5cc | 298 | static int pxa27x_cpu_pm_valid(suspend_state_t state) |
88dfe98c RK |
299 | { |
300 | return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; | |
301 | } | |
302 | ||
4104980a RK |
303 | static int pxa27x_cpu_pm_prepare(void) |
304 | { | |
305 | /* set resume return address */ | |
306 | PSPR = virt_to_phys(pxa_cpu_resume); | |
307 | return 0; | |
308 | } | |
309 | ||
310 | static void pxa27x_cpu_pm_finish(void) | |
311 | { | |
312 | /* ensure not to come back here if it wasn't intended */ | |
313 | PSPR = 0; | |
314 | } | |
315 | ||
711be5cc | 316 | static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { |
649de51b | 317 | .save_count = SLEEP_SAVE_COUNT, |
711be5cc EM |
318 | .save = pxa27x_cpu_pm_save, |
319 | .restore = pxa27x_cpu_pm_restore, | |
320 | .valid = pxa27x_cpu_pm_valid, | |
321 | .enter = pxa27x_cpu_pm_enter, | |
4104980a RK |
322 | .prepare = pxa27x_cpu_pm_prepare, |
323 | .finish = pxa27x_cpu_pm_finish, | |
e176bb05 | 324 | }; |
711be5cc EM |
325 | |
326 | static void __init pxa27x_init_pm(void) | |
327 | { | |
328 | pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; | |
329 | } | |
f79299ca | 330 | #else |
331 | static inline void pxa27x_init_pm(void) {} | |
a8fa3f0c NP |
332 | #endif |
333 | ||
c95530c7 | 334 | /* PXA27x: Various gpios can issue wakeup events. This logic only |
335 | * handles the simple cases, not the WEMUX2 and WEMUX3 options | |
336 | */ | |
c95530c7 | 337 | static int pxa27x_set_wake(unsigned int irq, unsigned int on) |
338 | { | |
339 | int gpio = IRQ_TO_GPIO(irq); | |
340 | uint32_t mask; | |
341 | ||
c0a596d6 | 342 | if (gpio >= 0 && gpio < 128) |
343 | return gpio_set_wake(gpio, on); | |
c95530c7 | 344 | |
c0a596d6 | 345 | if (irq == IRQ_KEYPAD) |
346 | return keypad_set_wake(on); | |
c95530c7 | 347 | |
348 | switch (irq) { | |
349 | case IRQ_RTCAlrm: | |
350 | mask = PWER_RTC; | |
351 | break; | |
352 | case IRQ_USB: | |
353 | mask = 1u << 26; | |
354 | break; | |
355 | default: | |
356 | return -EINVAL; | |
357 | } | |
358 | ||
c95530c7 | 359 | if (on) |
360 | PWER |= mask; | |
361 | else | |
362 | PWER &=~mask; | |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
367 | void __init pxa27x_init_irq(void) | |
368 | { | |
b9e25ace | 369 | pxa_init_irq(34, pxa27x_set_wake); |
a58fbcd8 | 370 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake); |
c95530c7 | 371 | } |
372 | ||
1da177e4 LT |
373 | /* |
374 | * device registration specific to PXA27x. | |
375 | */ | |
9ba63c4f | 376 | void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
b7a36701 | 377 | { |
bc3a5959 PZ |
378 | local_irq_disable(); |
379 | PCFR |= PCFR_PI2CEN; | |
380 | local_irq_enable(); | |
14758220 | 381 | pxa_register_device(&pxa27x_device_i2c_power, info); |
b7a36701 MR |
382 | } |
383 | ||
1da177e4 | 384 | static struct platform_device *devices[] __initdata = { |
7a857620 | 385 | &pxa27x_device_udc, |
e09d02e1 | 386 | &pxa_device_i2s, |
f0fba2ad LG |
387 | &pxa_device_asoc_ssp1, |
388 | &pxa_device_asoc_ssp2, | |
389 | &pxa_device_asoc_ssp3, | |
390 | &pxa_device_asoc_platform, | |
72493146 | 391 | &sa1100_device_rtc, |
e09d02e1 | 392 | &pxa_device_rtc, |
d8e0db11 | 393 | &pxa27x_device_ssp1, |
394 | &pxa27x_device_ssp2, | |
395 | &pxa27x_device_ssp3, | |
75540c1a | 396 | &pxa27x_device_pwm0, |
397 | &pxa27x_device_pwm1, | |
1da177e4 LT |
398 | }; |
399 | ||
c0165504 | 400 | static struct sys_device pxa27x_sysdev[] = { |
401 | { | |
c0165504 | 402 | .cls = &pxa_irq_sysclass, |
5a3d9651 EM |
403 | }, { |
404 | .cls = &pxa2xx_mfp_sysclass, | |
16dfdbf0 | 405 | }, { |
406 | .cls = &pxa_gpio_sysclass, | |
c0165504 | 407 | }, |
408 | }; | |
409 | ||
1da177e4 LT |
410 | static int __init pxa27x_init(void) |
411 | { | |
c0165504 | 412 | int i, ret = 0; |
413 | ||
e176bb05 | 414 | if (cpu_is_pxa27x()) { |
04fef228 EM |
415 | |
416 | reset_status = RCSR; | |
417 | ||
0a0300dc | 418 | clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); |
a6dba20c | 419 | |
fef1f99a | 420 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
f53f066c | 421 | return ret; |
f79299ca | 422 | |
711be5cc | 423 | pxa27x_init_pm(); |
f79299ca | 424 | |
c0165504 | 425 | for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) { |
426 | ret = sysdev_register(&pxa27x_sysdev[i]); | |
427 | if (ret) | |
428 | pr_err("failed to register sysdev[%d]\n", i); | |
429 | } | |
430 | ||
e176bb05 RK |
431 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
432 | } | |
c0165504 | 433 | |
e176bb05 | 434 | return ret; |
1da177e4 LT |
435 | } |
436 | ||
1c104e0e | 437 | postcore_initcall(pxa27x_init); |