[deliverable/linux.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/gpio-pxa.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/syscore_ops.h>
#include <linux/i2c/pxa-i2c.h>

#include <asm/mach/map.h>
#include <asm/suspend.h>
#include <mach/hardware.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include "pm.h"
#include <mach/dma.h>
#include <mach/smemc.h>
#include <mach/irqs.h>

#include "generic.h"
#include "devices.h"

#define PECR_IE(n)	((1 << ((n) * 2)) << 28)
#define PECR_IS(n)	((1 << ((n) * 2)) << 29)

extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));

/*
 * NAND NFC: DFI bus arbitration subset
 */
#define NDCR			(*(volatile u32 __iomem*)(NAND_VIRT + 0))
#define NDCR_ND_ARB_EN		(1 << 12)
#define NDCR_ND_ARB_CNTL	(1 << 19)

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;
#ifndef CONFIG_IWMMXT
	u64 acc0;

	asm volatile(".arch_extension xscale\n\t"
		     "mra %Q0, %R0, acc0" : "=r" (acc0));
#endif

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(cpu_resume);

	cpu_suspend(0, pxa3xx_finish_suspend);

	*p = saved_data;

	AD3ER = 0;

#ifndef CONFIG_IWMMXT
	asm volatile(".arch_extension xscale\n\t"
		     "mar acc0, %Q0, %R0" : "=r" (acc0));
#endif
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (d->irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

static void pxa_ack_ext_wakeup(struct irq_data *d)
{
	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
}

static void pxa_mask_ext_wakeup(struct irq_data *d)
{
	pxa_mask_irq(d);
	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
}

static void pxa_unmask_ext_wakeup(struct irq_data *d)
{
	pxa_unmask_irq(d);
	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
}

static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
{
	if (flow_type & IRQ_TYPE_EDGE_RISING)
		PWER |= 1 << (d->irq - IRQ_WAKEUP0);

	if (flow_type & IRQ_TYPE_EDGE_FALLING)
		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);

	return 0;
}

static struct irq_chip pxa_ext_wakeup_chip = {
	.name		= "WAKEUP",
	.irq_ack	= pxa_ack_ext_wakeup,
	.irq_mask	= pxa_mask_ext_wakeup,
	.irq_unmask	= pxa_unmask_ext_wakeup,
	.irq_set_type	= pxa_set_ext_wakeup_type,
};

static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
					   unsigned int))
{
	int irq;

	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
		irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
					 handle_edge_irq);
		irq_clear_status_flags(irq, IRQ_NOREQUEST);
	}

	pxa_ext_wakeup_chip.irq_set_wake = fn;
}

static void __init __pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
}

void __init pxa3xx_init_irq(void)
{
	__pxa3xx_init_irq();
	pxa_init_irq(56, pxa3xx_set_wake);
}

#ifdef CONFIG_OF
void __init pxa3xx_dt_init_irq(void)
{
	__pxa3xx_init_irq();
	pxa_dt_irq_init(pxa3xx_set_wake);
}
#endif	/* CONFIG_OF */

static struct map_desc pxa3xx_io_desc[] __initdata = {
	{	/* Mem Ctl */
		.virtual	= (unsigned long)SMEMC_VIRT,
		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
		.length		= SMEMC_SIZE,
		.type		= MT_DEVICE
	}, {
		.virtual	= (unsigned long)NAND_VIRT,
		.pfn		= __phys_to_pfn(NAND_PHYS),
		.length		= NAND_SIZE,
		.type		= MT_DEVICE
	},
};

void __init pxa3xx_map_io(void)
{
	pxa_map_io();
	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	pxa3xx_get_clk_frequency_khz(1);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
	.irq_base	= PXA_GPIO_TO_IRQ(0),
};

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&pxa_device_asoc_ssp1,
	&pxa_device_asoc_ssp2,
	&pxa_device_asoc_ssp3,
	&pxa_device_asoc_ssp4,
	&pxa_device_asoc_platform,
	&pxa_device_rtc,
	&pxa3xx_device_ssp1,
	&pxa3xx_device_ssp2,
	&pxa3xx_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static int __init pxa3xx_init(void)
{
	int ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		/*
		 * Disable DFI bus arbitration, to prevent a system bus lock if
		 * somebody disables the NAND clock (unused clock) while this
		 * bit remains set.
		 */
		NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa3xx_init_pm();

		register_syscore_ops(&pxa_irq_syscore_ops);
		register_syscore_ops(&pxa3xx_mfp_syscore_ops);

		if (of_have_populated_dt())
			return 0;

		pxa2xx_set_dmac_info(32, 100);
		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
		if (ret)
			return ret;
		if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
			platform_device_add_data(&pxa3xx_device_gpio,
						 &pxa3xx_gpio_pdata,
						 sizeof(pxa3xx_gpio_pdata));
			ret = platform_device_register(&pxa3xx_device_gpio);
		}
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
2c8086a5	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
b8f649f1	18	#include <linux/gpio-pxa.h>
2c8086a5	19	#include <linux/pm.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/irq.h>
7b5dea12	22	#include <linux/io.h>
82ce44d1	23	#include <linux/of.h>
2eaa03b5	24	#include <linux/syscore_ops.h>
b459396e	25	#include <linux/i2c/pxa-i2c.h>
2c8086a5	26
851982c1	27	#include <asm/mach/map.h>
2c74a0ce	28	#include <asm/suspend.h>
a09e64fb RK	29	#include <mach/hardware.h>
a09e64fb RK	30	#include <mach/pxa3xx-regs.h>
afd2fc02	31	#include <mach/reset.h>
293b2da1	32	#include <linux/platform_data/usb-ohci-pxa27x.h>
4c25c5d2	33	#include "pm.h"
a09e64fb	34	#include <mach/dma.h>
ad68bb9f	35	#include <mach/smemc.h>
4e611091	36	#include <mach/irqs.h>
2c8086a5	37
	38	#include "generic.h"
	39	#include "devices.h"
2c8086a5	40
bf293aec MR	41	#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
	42	#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
	43
089d0362	44	extern void __init pxa_dt_irq_init(int (fn)(struct irq_data , unsigned int));
7b5dea12	45
adf3442c RJ	46	/*
	47	* NAND NFC: DFI bus arbitration subset
	48	*/
	49	#define NDCR ((volatile u32 __iomem)(NAND_VIRT + 0))
	50	#define NDCR_ND_ARB_EN (1 << 12)
	51	#define NDCR_ND_ARB_CNTL (1 << 19)
	52
63910745 AB	53	#ifdef CONFIG_PM
	54
	55	#define ISRAM_START 0x5c000000
	56	#define ISRAM_SIZE SZ_256K
	57
7b5dea12 RK	58	static void __iomem *sram;
	59	static unsigned long wakeup_src;
	60
7b5dea12 RK	61	/*
	62	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	63	* memory controller has to be reinitialised, so we place some code
	64	* in the SRAM to perform this function.
	65	*
	66	* We disable FIQs across the standby - otherwise, we might receive a
	67	* FIQ while the SDRAM is unavailable.
	68	*/
	69	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	70	{
7b5dea12 RK	71	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	72
	73	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	74	pm_enter_standby_end - pm_enter_standby_start);
	75
	76	AD2D0SR = ~0;
	77	AD2D1SR = ~0;
	78	AD2D0ER = wakeup_src;
	79	AD2D1ER = 0;
	80	ASCR = ASCR;
	81	ARSR = ARSR;
	82
	83	local_fiq_disable();
	84	fn(pwrmode);
	85	local_fiq_enable();
	86
	87	AD2D0ER = 0;
	88	AD2D1ER = 0;
7b5dea12 RK	89	}
7b5dea12 RK	90
c4d1fb62	91	/*
	92	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	93	* PXA3xx development kits assumes that the resuming process continues
	94	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	95	* register is used privately by BootROM and OBM, and _must_ be set to
	96	* 0x5c014000 for the moment.
	97	*/
	98	static void pxa3xx_cpu_pm_suspend(void)
	99	{
	100	volatile unsigned long p = (volatile void )0xc0000000;
	101	unsigned long saved_data = *p;
a9503d21 RK	102	#ifndef CONFIG_IWMMXT
a9503d21 RK	103	u64 acc0;
c4d1fb62	104
343c1cdb AB	105	asm volatile(".arch_extension xscale\n\t"
343c1cdb AB	106	"mra %Q0, %R0, acc0" : "=r" (acc0));
a9503d21 RK	107	#endif
a9503d21 RK	108
c4d1fb62	109	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	110	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	111	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	112
	113	/* clear and setup wakeup source */
	114	AD3SR = ~0;
	115	AD3ER = wakeup_src;
	116	ASCR = ASCR;
	117	ARSR = ARSR;
	118
	119	PCFR \|= (1u << 13); /* L1_DIS */
	120	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	121
	122	PSPR = 0x5c014000;
	123
	124	/* overwrite with the resume address */
4f5ad99b	125	*p = virt_to_phys(cpu_resume);
c4d1fb62	126
2c74a0ce	127	cpu_suspend(0, pxa3xx_finish_suspend);
c4d1fb62	128
	129	*p = saved_data;
	130
	131	AD3ER = 0;
a9503d21 RK	132
a9503d21 RK	133	#ifndef CONFIG_IWMMXT
343c1cdb AB	134	asm volatile(".arch_extension xscale\n\t"
343c1cdb AB	135	"mar acc0, %Q0, %R0" : "=r" (acc0));
a9503d21	136	#endif
c4d1fb62	137	}
c4d1fb62	138
7b5dea12 RK	139	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	140	{
	141	/*
	142	* Don't sleep if no wakeup sources are defined
	143	*/
b86a5da8 MB	144	if (wakeup_src == 0) {
b86a5da8 MB	145	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	146	return;
b86a5da8	147	}
7b5dea12 RK	148
	149	switch (state) {
	150	case PM_SUSPEND_STANDBY:
	151	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	152	break;
	153
	154	case PM_SUSPEND_MEM:
c4d1fb62	155	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	156	break;
	157	}
	158	}
	159
	160	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	161	{
	162	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	163	}
	164
	165	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
7b5dea12 RK	166	.valid = pxa3xx_cpu_pm_valid,
7b5dea12 RK	167	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	168	};
2c8086a5	169
7b5dea12 RK	170	static void __init pxa3xx_init_pm(void)
	171	{
	172	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	173	if (!sram) {
	174	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	175	return;
	176	}
	177
	178	/*
	179	* Since we copy wakeup code into the SRAM, we need to ensure
	180	* that it is preserved over the low power modes. Note: bit 8
	181	* is undocumented in the developer manual, but must be set.
	182	*/
	183	AD1R \|= ADXR_L2 \| ADXR_R0;
	184	AD2R \|= ADXR_L2 \| ADXR_R0;
	185	AD3R \|= ADXR_L2 \| ADXR_R0;
	186
	187	/*
	188	* Clear the resume enable registers.
	189	*/
	190	AD1D0ER = 0;
	191	AD2D0ER = 0;
	192	AD2D1ER = 0;
	193	AD3ER = 0;
	194
	195	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	196	}
	197
a3f4c927	198	static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
7b5dea12 RK	199	{
	200	unsigned long flags, mask = 0;
	201
a3f4c927	202	switch (d->irq) {
7b5dea12 RK	203	case IRQ_SSP3:
	204	mask = ADXER_MFP_WSSP3;
	205	break;
	206	case IRQ_MSL:
	207	mask = ADXER_WMSL0;
	208	break;
	209	case IRQ_USBH2:
	210	case IRQ_USBH1:
	211	mask = ADXER_WUSBH;
	212	break;
	213	case IRQ_KEYPAD:
	214	mask = ADXER_WKP;
	215	break;
	216	case IRQ_AC97:
	217	mask = ADXER_MFP_WAC97;
	218	break;
	219	case IRQ_USIM:
	220	mask = ADXER_WUSIM0;
	221	break;
	222	case IRQ_SSP2:
	223	mask = ADXER_MFP_WSSP2;
	224	break;
	225	case IRQ_I2C:
	226	mask = ADXER_MFP_WI2C;
	227	break;
	228	case IRQ_STUART:
	229	mask = ADXER_MFP_WUART3;
	230	break;
	231	case IRQ_BTUART:
	232	mask = ADXER_MFP_WUART2;
	233	break;
	234	case IRQ_FFUART:
	235	mask = ADXER_MFP_WUART1;
	236	break;
	237	case IRQ_MMC:
	238	mask = ADXER_MFP_WMMC1;
	239	break;
	240	case IRQ_SSP:
	241	mask = ADXER_MFP_WSSP1;
	242	break;
	243	case IRQ_RTCAlrm:
	244	mask = ADXER_WRTC;
	245	break;
	246	case IRQ_SSP4:
	247	mask = ADXER_MFP_WSSP4;
	248	break;
	249	case IRQ_TSI:
	250	mask = ADXER_WTSI;
	251	break;
	252	case IRQ_USIM2:
	253	mask = ADXER_WUSIM1;
	254	break;
	255	case IRQ_MMC2:
	256	mask = ADXER_MFP_WMMC2;
	257	break;
	258	case IRQ_NAND:
	259	mask = ADXER_MFP_WFLASH;
	260	break;
	261	case IRQ_USB2:
	262	mask = ADXER_WUSB2;
	263	break;
	264	case IRQ_WAKEUP0:
	265	mask = ADXER_WEXTWAKE0;
	266	break;
267	case IRQ_WAKEUP1:
268	mask = ADXER_WEXTWAKE1;
269	break;
270	case IRQ_MMC3:
271	mask = ADXER_MFP_GEN12;
272	break;
e1217707 MB	273	default:
e1217707 MB	274	return -EINVAL;
7b5dea12 RK	275	}
	276
	277	local_irq_save(flags);
	278	if (on)
	279	wakeup_src \|= mask;
	280	else
	281	wakeup_src &= ~mask;
	282	local_irq_restore(flags);
	283
	284	return 0;
	285	}
7b5dea12 RK	286	#else
7b5dea12 RK	287	static inline void pxa3xx_init_pm(void) {}
b9e25ace	288	#define pxa3xx_set_wake NULL
7b5dea12 RK	289	#endif
7b5dea12 RK	290
a3f4c927	291	static void pxa_ack_ext_wakeup(struct irq_data *d)
bf293aec	292	{
a3f4c927	293	PECR \|= PECR_IS(d->irq - IRQ_WAKEUP0);
bf293aec MR	294	}
bf293aec MR	295
a3f4c927	296	static void pxa_mask_ext_wakeup(struct irq_data *d)
bf293aec	297	{
5d284e35	298	pxa_mask_irq(d);
a3f4c927	299	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
bf293aec MR	300	}
bf293aec MR	301
a3f4c927	302	static void pxa_unmask_ext_wakeup(struct irq_data *d)
bf293aec	303	{
5d284e35	304	pxa_unmask_irq(d);
a3f4c927	305	PECR \|= PECR_IE(d->irq - IRQ_WAKEUP0);
bf293aec MR	306	}
bf293aec MR	307
a3f4c927	308	static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
12882096 IG	309	{
12882096 IG	310	if (flow_type & IRQ_TYPE_EDGE_RISING)
a3f4c927	311	PWER \|= 1 << (d->irq - IRQ_WAKEUP0);
12882096 IG	312
12882096 IG	313	if (flow_type & IRQ_TYPE_EDGE_FALLING)
a3f4c927	314	PWER \|= 1 << (d->irq - IRQ_WAKEUP0 + 2);
12882096 IG	315
	316	return 0;
	317	}
	318
bf293aec MR	319	static struct irq_chip pxa_ext_wakeup_chip = {
bf293aec MR	320	.name = "WAKEUP",
a3f4c927 LB	321	.irq_ack = pxa_ack_ext_wakeup,
	322	.irq_mask = pxa_mask_ext_wakeup,
	323	.irq_unmask = pxa_unmask_ext_wakeup,
	324	.irq_set_type = pxa_set_ext_wakeup_type,
bf293aec MR	325	};
bf293aec MR	326
157d2644 HZ	327	static void __init pxa_init_ext_wakeup_irq(int (fn)(struct irq_data ,
157d2644 HZ	328	unsigned int))
bf293aec MR	329	{
	330	int irq;
	331
	332	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
f38c02f3 TG	333	irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
f38c02f3 TG	334	handle_edge_irq);
e8d36d5d	335	irq_clear_status_flags(irq, IRQ_NOREQUEST);
bf293aec MR	336	}
bf293aec MR	337
a3f4c927	338	pxa_ext_wakeup_chip.irq_set_wake = fn;
bf293aec MR	339	}
bf293aec MR	340
089d0362	341	static void __init __pxa3xx_init_irq(void)
2c8086a5	342	{
	343	/* enable CP6 access */
	344	u32 value;
	345	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	346	value \|= (1 << 6);
	347	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	348
bf293aec	349	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
2c8086a5	350	}
2c8086a5	351
089d0362 DM	352	void __init pxa3xx_init_irq(void)
	353	{
	354	__pxa3xx_init_irq();
	355	pxa_init_irq(56, pxa3xx_set_wake);
	356	}
	357
e6c509c8	358	#ifdef CONFIG_OF
089d0362 DM	359	void __init pxa3xx_dt_init_irq(void)
	360	{
	361	__pxa3xx_init_irq();
	362	pxa_dt_irq_init(pxa3xx_set_wake);
	363	}
e6c509c8	364	#endif /* CONFIG_OF */
089d0362	365
851982c1 MV	366	static struct map_desc pxa3xx_io_desc[] __initdata = {
851982c1 MV	367	{ /* Mem Ctl */
97b09da4	368	.virtual = (unsigned long)SMEMC_VIRT,
ad68bb9f	369	.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
0e32986c	370	.length = SMEMC_SIZE,
851982c1	371	.type = MT_DEVICE
adf3442c RJ	372	}, {
	373	.virtual = (unsigned long)NAND_VIRT,
	374	.pfn = __phys_to_pfn(NAND_PHYS),
	375	.length = NAND_SIZE,
	376	.type = MT_DEVICE
	377	},
851982c1 MV	378	};
	379
	380	void __init pxa3xx_map_io(void)
	381	{
	382	pxa_map_io();
	383	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
	384	pxa3xx_get_clk_frequency_khz(1);
	385	}
	386
2c8086a5	387	/*
	388	* device registration specific to PXA3xx.
	389	*/
	390
9ba63c4f MR	391	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	392	{
14758220	393	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	394	}
9ba63c4f MR	395
b8f649f1 HZ	396	static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
	397	.irq_base = PXA_GPIO_TO_IRQ(0),
	398	};
	399
2c8086a5	400	static struct platform_device *devices[] __initdata = {
94c35a6b	401	&pxa27x_device_udc,
09a5358d	402	&pxa_device_pmu,
2c8086a5	403	&pxa_device_i2s,
f0fba2ad LG	404	&pxa_device_asoc_ssp1,
	405	&pxa_device_asoc_ssp2,
	406	&pxa_device_asoc_ssp3,
	407	&pxa_device_asoc_ssp4,
	408	&pxa_device_asoc_platform,
2c8086a5	409	&pxa_device_rtc,
0da0e227 DM	410	&pxa3xx_device_ssp1,
	411	&pxa3xx_device_ssp2,
	412	&pxa3xx_device_ssp3,
d8e0db11	413	&pxa3xx_device_ssp4,
75540c1a	414	&pxa27x_device_pwm0,
75540c1a	415	&pxa27x_device_pwm1,
2c8086a5	416	};
	417
	418	static int __init pxa3xx_init(void)
	419	{
2eaa03b5	420	int ret = 0;
2c8086a5	421
2c8086a5	422	if (cpu_is_pxa3xx()) {
04fef228 EM	423
	424	reset_status = ARSR;
	425
86260f98 DK	426	/*
	427	* clear RDH bit every time after reset
	428	*
	429	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	430	* preserve them here in case they will be referenced later
	431	*/
	432	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	433
adf3442c RJ	434	/*
	435	* Disable DFI bus arbitration, to prevent a system bus lock if
	436	* somebody disables the NAND clock (unused clock) while this
	437	* bit remains set.
	438	*/
	439	NDCR = (NDCR & ~NDCR_ND_ARB_EN) \| NDCR_ND_ARB_CNTL;
	440
fef1f99a	441	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
2c8086a5	442	return ret;
2c8086a5	443
7b5dea12 RK	444	pxa3xx_init_pm();
7b5dea12 RK	445
2eaa03b5 RW	446	register_syscore_ops(&pxa_irq_syscore_ops);
2eaa03b5 RW	447	register_syscore_ops(&pxa3xx_mfp_syscore_ops);
c0165504	448
2cab0292 HZ	449	if (of_have_populated_dt())
	450	return 0;
	451
72b195cb	452	pxa2xx_set_dmac_info(32, 100);
2cab0292 HZ	453	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	454	if (ret)
	455	return ret;
b8f649f1 HZ	456	if (cpu_is_pxa300() \|\| cpu_is_pxa310() \|\| cpu_is_pxa320()) {
	457	platform_device_add_data(&pxa3xx_device_gpio,
	458	&pxa3xx_gpio_pdata,
	459	sizeof(pxa3xx_gpio_pdata));
2cab0292	460	ret = platform_device_register(&pxa3xx_device_gpio);
b8f649f1	461	}
2c8086a5	462	}
c0165504	463
c0165504	464	return ret;
2c8086a5	465	}
2c8086a5	466
1c104e0e	467	postcore_initcall(pxa3xx_init);