Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/arm/mach-pxa/time.c | |
3 | * | |
7bbb18c9 BG |
4 | * PXA clocksource, clockevents, and OST interrupt handlers. |
5 | * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>. | |
6 | * | |
7 | * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001 | |
8 | * by MontaVista Software, Inc. (Nico, your code rocks!) | |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
1da177e4 LT |
15 | #include <linux/kernel.h> |
16 | #include <linux/init.h> | |
1da177e4 | 17 | #include <linux/interrupt.h> |
7bbb18c9 | 18 | #include <linux/clockchips.h> |
6c3a1583 | 19 | #include <linux/sched.h> |
7bbb18c9 | 20 | |
6c3a1583 | 21 | #include <asm/div64.h> |
1da177e4 LT |
22 | #include <asm/mach/irq.h> |
23 | #include <asm/mach/time.h> | |
7ce83018 | 24 | #include <asm/sched_clock.h> |
5bf3df3f | 25 | #include <mach/regs-ost.h> |
1da177e4 | 26 | |
6c3a1583 NP |
27 | /* |
28 | * This is PXA's sched_clock implementation. This has a resolution | |
29 | * of at least 308 ns and a maximum value of 208 days. | |
30 | * | |
31 | * The return value is guaranteed to be monotonic in that range as | |
32 | * long as there is always less than 582 seconds between successive | |
33 | * calls to sched_clock() which should always be the case in practice. | |
34 | */ | |
7ce83018 | 35 | static DEFINE_CLOCK_DATA(cd); |
6c3a1583 | 36 | |
7ce83018 | 37 | unsigned long long notrace sched_clock(void) |
6c3a1583 | 38 | { |
7ce83018 RK |
39 | u32 cyc = OSCR; |
40 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); | |
6c3a1583 NP |
41 | } |
42 | ||
7ce83018 | 43 | static void notrace pxa_update_sched_clock(void) |
6c3a1583 | 44 | { |
7ce83018 RK |
45 | u32 cyc = OSCR; |
46 | update_sched_clock(&cd, cyc, (u32)~0); | |
6c3a1583 NP |
47 | } |
48 | ||
49 | ||
a88264c2 RK |
50 | #define MIN_OSCR_DELTA 16 |
51 | ||
1da177e4 | 52 | static irqreturn_t |
7bbb18c9 | 53 | pxa_ost0_interrupt(int irq, void *dev_id) |
1da177e4 | 54 | { |
7bbb18c9 BG |
55 | struct clock_event_device *c = dev_id; |
56 | ||
a88264c2 RK |
57 | /* Disarm the compare/match, signal the event. */ |
58 | OIER &= ~OIER_E0; | |
59 | OSSR = OSSR_M0; | |
60 | c->event_handler(c); | |
1da177e4 LT |
61 | |
62 | return IRQ_HANDLED; | |
63 | } | |
64 | ||
7bbb18c9 BG |
65 | static int |
66 | pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev) | |
67 | { | |
a602f0f2 | 68 | unsigned long next, oscr; |
7bbb18c9 | 69 | |
7bbb18c9 | 70 | OIER |= OIER_E0; |
91bc51d8 RK |
71 | next = OSCR + delta; |
72 | OSMR0 = next; | |
73 | oscr = OSCR; | |
91bc51d8 RK |
74 | |
75 | return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; | |
7bbb18c9 BG |
76 | } |
77 | ||
78 | static void | |
79 | pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |
80 | { | |
7bbb18c9 | 81 | switch (mode) { |
7bbb18c9 | 82 | case CLOCK_EVT_MODE_ONESHOT: |
7bbb18c9 | 83 | OIER &= ~OIER_E0; |
91bc51d8 | 84 | OSSR = OSSR_M0; |
7bbb18c9 BG |
85 | break; |
86 | ||
87 | case CLOCK_EVT_MODE_UNUSED: | |
88 | case CLOCK_EVT_MODE_SHUTDOWN: | |
89 | /* initializing, released, or preparing for suspend */ | |
7bbb18c9 | 90 | OIER &= ~OIER_E0; |
91bc51d8 | 91 | OSSR = OSSR_M0; |
7bbb18c9 | 92 | break; |
df43309b RK |
93 | |
94 | case CLOCK_EVT_MODE_RESUME: | |
a88264c2 | 95 | case CLOCK_EVT_MODE_PERIODIC: |
df43309b | 96 | break; |
7bbb18c9 BG |
97 | } |
98 | } | |
99 | ||
100 | static struct clock_event_device ckevt_pxa_osmr0 = { | |
101 | .name = "osmr0", | |
a88264c2 | 102 | .features = CLOCK_EVT_FEAT_ONESHOT, |
7bbb18c9 | 103 | .rating = 200, |
7bbb18c9 BG |
104 | .set_next_event = pxa_osmr0_set_next_event, |
105 | .set_mode = pxa_osmr0_set_mode, | |
1da177e4 LT |
106 | }; |
107 | ||
7bbb18c9 BG |
108 | static struct irqaction pxa_ost0_irq = { |
109 | .name = "ost0", | |
110 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | |
111 | .handler = pxa_ost0_interrupt, | |
112 | .dev_id = &ckevt_pxa_osmr0, | |
113 | }; | |
114 | ||
1da177e4 LT |
115 | static void __init pxa_timer_init(void) |
116 | { | |
6769717d | 117 | unsigned long clock_tick_rate = get_clock_tick_rate(); |
08197f6e | 118 | |
7bbb18c9 BG |
119 | OIER = 0; |
120 | OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; | |
1da177e4 | 121 | |
7ce83018 | 122 | init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); |
6c3a1583 | 123 | |
ccc46e29 | 124 | clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4); |
7bbb18c9 BG |
125 | ckevt_pxa_osmr0.max_delta_ns = |
126 | clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); | |
127 | ckevt_pxa_osmr0.min_delta_ns = | |
dd01b2fc | 128 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; |
320ab2b0 | 129 | ckevt_pxa_osmr0.cpumask = cpumask_of(0); |
1da177e4 | 130 | |
7bbb18c9 | 131 | setup_irq(IRQ_OST0, &pxa_ost0_irq); |
5c53ff08 | 132 | |
234b6ced RK |
133 | clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32, |
134 | clocksource_mmio_readl_up); | |
7bbb18c9 | 135 | clockevents_register_device(&ckevt_pxa_osmr0); |
5c53ff08 NP |
136 | } |
137 | ||
1da177e4 | 138 | #ifdef CONFIG_PM |
4ae7806f | 139 | static unsigned long osmr[4], oier, oscr; |
1da177e4 LT |
140 | |
141 | static void pxa_timer_suspend(void) | |
142 | { | |
143 | osmr[0] = OSMR0; | |
144 | osmr[1] = OSMR1; | |
145 | osmr[2] = OSMR2; | |
146 | osmr[3] = OSMR3; | |
147 | oier = OIER; | |
4ae7806f | 148 | oscr = OSCR; |
1da177e4 LT |
149 | } |
150 | ||
151 | static void pxa_timer_resume(void) | |
152 | { | |
4ae7806f RK |
153 | /* |
154 | * Ensure that we have at least MIN_OSCR_DELTA between match | |
155 | * register 0 and the OSCR, to guarantee that we will receive | |
156 | * the one-shot timer interrupt. We adjust OSMR0 in preference | |
157 | * to OSCR to guarantee that OSCR is monotonically incrementing. | |
158 | */ | |
159 | if (osmr[0] - oscr < MIN_OSCR_DELTA) | |
160 | osmr[0] += MIN_OSCR_DELTA; | |
161 | ||
1da177e4 LT |
162 | OSMR0 = osmr[0]; |
163 | OSMR1 = osmr[1]; | |
164 | OSMR2 = osmr[2]; | |
165 | OSMR3 = osmr[3]; | |
166 | OIER = oier; | |
4ae7806f | 167 | OSCR = oscr; |
1da177e4 LT |
168 | } |
169 | #else | |
170 | #define pxa_timer_suspend NULL | |
171 | #define pxa_timer_resume NULL | |
172 | #endif | |
173 | ||
174 | struct sys_timer pxa_timer = { | |
175 | .init = pxa_timer_init, | |
176 | .suspend = pxa_timer_suspend, | |
177 | .resume = pxa_timer_resume, | |
1da177e4 | 178 | }; |