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ARM: pxa: move declarations from generic.h to <soc>.h
[deliverable/linux.git] / arch / arm / mach-pxa / zeus.c
CommitLineData
e491a11c
MZ		 1/*
2 * Support for the Arcom ZEUS.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * Loosely based on Arcom's 2.6.16.28.
7 * Maintained by Marc Zyngier <maz@misterjones.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/cpufreq.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/pm.h>
18#include <linux/gpio.h>
19#include <linux/serial_8250.h>
20#include <linux/dm9000.h>
21#include <linux/mmc/host.h>
22#include <linux/spi/spi.h>
8348c259 23#include <linux/spi/pxa2xx_spi.h>
e491a11c
MZ		 24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26#include <linux/mtd/physmap.h>
27#include <linux/i2c.h>
b459396e 28#include <linux/i2c/pxa-i2c.h>
e491a11c 29#include <linux/i2c/pca953x.h>
a1916eb0 30#include <linux/apm-emulation.h>
438a22fe 31#include <linux/can/platform/mcp251x.h>
e491a11c
MZ		 32
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36
ca0e687c 37#include <mach/pxa27x.h>
e491a11c
MZ		 38#include <mach/regs-uart.h>
39#include <mach/ohci.h>
40#include <mach/mmc.h>
41#include <mach/pxa27x-udc.h>
42#include <mach/udc.h>
43#include <mach/pxafb.h>
e491a11c
MZ		 44#include <mach/pm.h>
45#include <mach/audio.h>
c2de1c38 46#include <mach/arcom-pcmcia.h>
e491a11c 47#include <mach/zeus.h>
ad68bb9f 48#include <mach/smemc.h>
e491a11c
MZ		 49
50#include "generic.h"
51
52/*
53 * Interrupt handling
54 */
55
56static unsigned long zeus_irq_enabled_mask;
57static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
58static const int zeus_isa_irq_map[] = {
59 0, /* ISA irq #0, invalid */
60 0, /* ISA irq #1, invalid */
61 0, /* ISA irq #2, invalid */
62 1 << 0, /* ISA irq #3 */
63 1 << 1, /* ISA irq #4 */
64 1 << 2, /* ISA irq #5 */
65 1 << 3, /* ISA irq #6 */
66 1 << 4, /* ISA irq #7 */
67 0, /* ISA irq #8, invalid */
68 0, /* ISA irq #9, invalid */
69 1 << 5, /* ISA irq #10 */
70 1 << 6, /* ISA irq #11 */
71 1 << 7, /* ISA irq #12 */
72};
73
74static inline int zeus_irq_to_bitmask(unsigned int irq)
75{
76 return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
77}
78
79static inline int zeus_bit_to_irq(int bit)
80{
81 return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
82}
83
a3f4c927 84static void zeus_ack_irq(struct irq_data *d)
e491a11c 85{
a3f4c927 86 __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
e491a11c
MZ		 87}
88
a3f4c927 89static void zeus_mask_irq(struct irq_data *d)
e491a11c 90{
a3f4c927 91 zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
e491a11c
MZ		 92}
93
a3f4c927 94static void zeus_unmask_irq(struct irq_data *d)
e491a11c 95{
a3f4c927 96 zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
e491a11c
MZ		 97}
98
99static inline unsigned long zeus_irq_pending(void)
100{
101 return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
102}
103
104static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
105{
106 unsigned long pending;
107
108 pending = zeus_irq_pending();
109 do {
110 /* we're in a chained irq handler,
111 * so ack the interrupt by hand */
a3f4c927 112 desc->irq_data.chip->irq_ack(&desc->irq_data);
e491a11c
MZ		 113
114 if (likely(pending)) {
115 irq = zeus_bit_to_irq(__ffs(pending));
116 generic_handle_irq(irq);
117 }
118 pending = zeus_irq_pending();
119 } while (pending);
120}
121
122static struct irq_chip zeus_irq_chip = {
a3f4c927
LB		 123 .name = "ISA",
124 .irq_ack = zeus_ack_irq,
125 .irq_mask = zeus_mask_irq,
126 .irq_unmask = zeus_unmask_irq,
e491a11c
MZ		 127};
128
129static void __init zeus_init_irq(void)
130{
131 int level;
132 int isa_irq;
133
134 pxa27x_init_irq();
135
136 /* Peripheral IRQs. It would be nice to move those inside driver
137 configuration, but it is not supported at the moment. */
6845664a
TG		 138 irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
139 irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
140 irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
141 irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
142 IRQ_TYPE_EDGE_FALLING);
143 irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
e491a11c
MZ		 144
145 /* Setup ISA IRQs */
146 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
147 isa_irq = zeus_bit_to_irq(level);
f38c02f3
TG		 148 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
149 handle_edge_irq);
e491a11c
MZ		 150 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
151 }
152
6845664a
TG		 153 irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
154 irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
e491a11c
MZ		 155}
156
157
158/*
159 * Platform devices
160 */
161
162/* Flash */
163static struct resource zeus_mtd_resources[] = {
164 [0] = { /* NOR Flash (up to 64MB) */
165 .start = ZEUS_FLASH_PHYS,
166 .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
167 .flags = IORESOURCE_MEM,
168 },
169 [1] = { /* SRAM */
170 .start = ZEUS_SRAM_PHYS,
171 .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
172 .flags = IORESOURCE_MEM,
173 },
174};
175
176static struct physmap_flash_data zeus_flash_data[] = {
177 [0] = {
178 .width = 2,
179 .parts = NULL,
180 .nr_parts = 0,
181 },
182};
183
184static struct platform_device zeus_mtd_devices[] = {
185 [0] = {
186 .name = "physmap-flash",
187 .id = 0,
188 .dev = {
189 .platform_data = &zeus_flash_data[0],
190 },
191 .resource = &zeus_mtd_resources[0],
192 .num_resources = 1,
193 },
194};
195
196/* Serial */
197static struct resource zeus_serial_resources[] = {
198 {
199 .start = 0x10000000,
200 .end = 0x1000000f,
201 .flags = IORESOURCE_MEM,
202 },
203 {
204 .start = 0x10800000,
205 .end = 0x1080000f,
206 .flags = IORESOURCE_MEM,
207 },
208 {
209 .start = 0x11000000,
210 .end = 0x1100000f,
211 .flags = IORESOURCE_MEM,
212 },
213 {
214 .start = 0x40100000,
215 .end = 0x4010001f,
216 .flags = IORESOURCE_MEM,
217 },
218 {
219 .start = 0x40200000,
220 .end = 0x4020001f,
221 .flags = IORESOURCE_MEM,
222 },
223 {
224 .start = 0x40700000,
225 .end = 0x4070001f,
226 .flags = IORESOURCE_MEM,
227 },
228};
229
230static struct plat_serial8250_port serial_platform_data[] = {
231 /* External UARTs */
232 /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
233 { /* COM1 */
234 .mapbase = 0x10000000,
235 .irq = gpio_to_irq(ZEUS_UARTA_GPIO),
236 .irqflags = IRQF_TRIGGER_RISING,
237 .uartclk = 14745600,
238 .regshift = 1,
239 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
240 .iotype = UPIO_MEM,
241 },
242 { /* COM2 */
243 .mapbase = 0x10800000,
244 .irq = gpio_to_irq(ZEUS_UARTB_GPIO),
245 .irqflags = IRQF_TRIGGER_RISING,
246 .uartclk = 14745600,
247 .regshift = 1,
248 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
249 .iotype = UPIO_MEM,
250 },
251 { /* COM3 */
252 .mapbase = 0x11000000,
253 .irq = gpio_to_irq(ZEUS_UARTC_GPIO),
254 .irqflags = IRQF_TRIGGER_RISING,
255 .uartclk = 14745600,
256 .regshift = 1,
257 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
258 .iotype = UPIO_MEM,
259 },
260 { /* COM4 */
261 .mapbase = 0x11800000,
262 .irq = gpio_to_irq(ZEUS_UARTD_GPIO),
263 .irqflags = IRQF_TRIGGER_RISING,
264 .uartclk = 14745600,
265 .regshift = 1,
266 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
267 .iotype = UPIO_MEM,
268 },
269 /* Internal UARTs */
270 { /* FFUART */
271 .membase = (void *)&FFUART,
272 .mapbase = __PREG(FFUART),
273 .irq = IRQ_FFUART,
274 .uartclk = 921600 * 16,
275 .regshift = 2,
276 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
277 .iotype = UPIO_MEM,
278 },
279 { /* BTUART */
280 .membase = (void *)&BTUART,
281 .mapbase = __PREG(BTUART),
282 .irq = IRQ_BTUART,
283 .uartclk = 921600 * 16,
284 .regshift = 2,
285 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
286 .iotype = UPIO_MEM,
287 },
288 { /* STUART */
289 .membase = (void *)&STUART,
290 .mapbase = __PREG(STUART),
291 .irq = IRQ_STUART,
292 .uartclk = 921600 * 16,
293 .regshift = 2,
294 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
295 .iotype = UPIO_MEM,
296 },
297 { },
298};
299
300static struct platform_device zeus_serial_device = {
301 .name = "serial8250",
302 .id = PLAT8250_DEV_PLATFORM,
303 .dev = {
304 .platform_data = serial_platform_data,
305 },
306 .num_resources = ARRAY_SIZE(zeus_serial_resources),
307 .resource = zeus_serial_resources,
308};
309
310/* Ethernet */
311static struct resource zeus_dm9k0_resource[] = {
312 [0] = {
313 .start = ZEUS_ETH0_PHYS,
314 .end = ZEUS_ETH0_PHYS + 1,
315 .flags = IORESOURCE_MEM
316 },
317 [1] = {
318 .start = ZEUS_ETH0_PHYS + 2,
319 .end = ZEUS_ETH0_PHYS + 3,
320 .flags = IORESOURCE_MEM
321 },
322 [2] = {
323 .start = gpio_to_irq(ZEUS_ETH0_GPIO),
324 .end = gpio_to_irq(ZEUS_ETH0_GPIO),
325 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
326 },
327};
328
329static struct resource zeus_dm9k1_resource[] = {
330 [0] = {
331 .start = ZEUS_ETH1_PHYS,
332 .end = ZEUS_ETH1_PHYS + 1,
333 .flags = IORESOURCE_MEM
334 },
335 [1] = {
336 .start = ZEUS_ETH1_PHYS + 2,
337 .end = ZEUS_ETH1_PHYS + 3,
338 .flags = IORESOURCE_MEM,
339 },
340 [2] = {
341 .start = gpio_to_irq(ZEUS_ETH1_GPIO),
342 .end = gpio_to_irq(ZEUS_ETH1_GPIO),
343 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
344 },
345};
346
347static struct dm9000_plat_data zeus_dm9k_platdata = {
348 .flags = DM9000_PLATF_16BITONLY,
349};
350
351static struct platform_device zeus_dm9k0_device = {
352 .name = "dm9000",
353 .id = 0,
354 .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
355 .resource = zeus_dm9k0_resource,
356 .dev = {
357 .platform_data = &zeus_dm9k_platdata,
358 }
359};
360
361static struct platform_device zeus_dm9k1_device = {
362 .name = "dm9000",
363 .id = 1,
364 .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
365 .resource = zeus_dm9k1_resource,
366 .dev = {
367 .platform_data = &zeus_dm9k_platdata,
368 }
369};
370
371/* External SRAM */
372static struct resource zeus_sram_resource = {
373 .start = ZEUS_SRAM_PHYS,
374 .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
375 .flags = IORESOURCE_MEM,
376};
377
378static struct platform_device zeus_sram_device = {
379 .name = "pxa2xx-8bit-sram",
380 .id = 0,
381 .num_resources = 1,
382 .resource = &zeus_sram_resource,
383};
384
385/* SPI interface on SSP3 */
386static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
387 .num_chipselect = 1,
388 .enable_dma = 1,
389};
390
438a22fe
MZ		 391/* CAN bus on SPI */
392static int zeus_mcp2515_setup(struct spi_device *sdev)
393{
394 int err;
395
396 err = gpio_request(ZEUS_CAN_SHDN_GPIO, "CAN shutdown");
397 if (err)
398 return err;
399
400 err = gpio_direction_output(ZEUS_CAN_SHDN_GPIO, 1);
401 if (err) {
402 gpio_free(ZEUS_CAN_SHDN_GPIO);
403 return err;
404 }
405
406 return 0;
407}
408
409static int zeus_mcp2515_transceiver_enable(int enable)
410{
411 gpio_set_value(ZEUS_CAN_SHDN_GPIO, !enable);
412 return 0;
413}
414
415static struct mcp251x_platform_data zeus_mcp2515_pdata = {
416 .oscillator_frequency = 16*1000*1000,
438a22fe 417 .board_specific_setup = zeus_mcp2515_setup,
438a22fe
MZ		 418 .power_enable = zeus_mcp2515_transceiver_enable,
419};
420
421static struct spi_board_info zeus_spi_board_info[] = {
422 [0] = {
e446630c 423 .modalias = "mcp2515",
438a22fe
MZ		 424 .platform_data = &zeus_mcp2515_pdata,
425 .irq = gpio_to_irq(ZEUS_CAN_GPIO),
426 .max_speed_hz = 1*1000*1000,
427 .bus_num = 3,
428 .mode = SPI_MODE_0,
429 .chip_select = 0,
e491a11c
MZ		 430 },
431};
432
433/* Leds */
434static struct gpio_led zeus_leds[] = {
435 [0] = {
436 .name = "zeus:yellow:1",
437 .default_trigger = "heartbeat",
438 .gpio = ZEUS_EXT0_GPIO(3),
439 .active_low = 1,
440 },
441 [1] = {
442 .name = "zeus:yellow:2",
443 .default_trigger = "default-on",
444 .gpio = ZEUS_EXT0_GPIO(4),
445 .active_low = 1,
446 },
447 [2] = {
448 .name = "zeus:yellow:3",
449 .default_trigger = "default-on",
450 .gpio = ZEUS_EXT0_GPIO(5),
451 .active_low = 1,
452 },
453};
454
455static struct gpio_led_platform_data zeus_leds_info = {
456 .leds = zeus_leds,
457 .num_leds = ARRAY_SIZE(zeus_leds),
458};
459
460static struct platform_device zeus_leds_device = {
461 .name = "leds-gpio",
462 .id = -1,
463 .dev = {
464 .platform_data = &zeus_leds_info,
465 },
466};
467
c2de1c38
MZ		 468static void zeus_cf_reset(int state)
469{
470 u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
471
472 if (state)
473 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
474 else
475 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
476
477 __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
478}
479
480static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
481 .cd_gpio = ZEUS_CF_CD_GPIO,
482 .rdy_gpio = ZEUS_CF_RDY_GPIO,
483 .pwr_gpio = ZEUS_CF_PWEN_GPIO,
484 .reset = zeus_cf_reset,
485};
486
487static struct platform_device zeus_pcmcia_device = {
488 .name = "zeus-pcmcia",
489 .id = -1,
490 .dev = {
491 .platform_data = &zeus_pcmcia_info,
492 },
493};
494
fcfdc67f
MZ		 495static struct resource zeus_max6369_resource = {
496 .start = ZEUS_CPLD_EXTWDOG_PHYS,
497 .end = ZEUS_CPLD_EXTWDOG_PHYS,
498 .flags = IORESOURCE_MEM,
499};
500
501struct platform_device zeus_max6369_device = {
502 .name = "max6369_wdt",
503 .id = -1,
504 .resource = &zeus_max6369_resource,
505 .num_resources = 1,
506};
507
e491a11c
MZ		 508static struct platform_device *zeus_devices[] __initdata = {
509 &zeus_serial_device,
510 &zeus_mtd_devices[0],
511 &zeus_dm9k0_device,
512 &zeus_dm9k1_device,
513 &zeus_sram_device,
e491a11c 514 &zeus_leds_device,
c2de1c38 515 &zeus_pcmcia_device,
fcfdc67f 516 &zeus_max6369_device,
e491a11c
MZ		 517};
518
519/* AC'97 */
520static pxa2xx_audio_ops_t zeus_ac97_info = {
521 .reset_gpio = 95,
522};
523
524
525/*
526 * USB host
527 */
528
529static int zeus_ohci_init(struct device *dev)
530{
531 int err;
532
533 /* Switch on port 2. */
534 if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
535 dev_err(dev, "Can't request USB2_PWREN\n");
536 return err;
537 }
538
539 if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
540 gpio_free(ZEUS_USB2_PWREN_GPIO);
541 dev_err(dev, "Can't enable USB2_PWREN\n");
542 return err;
543 }
544
545 /* Port 2 is shared between host and client interface. */
546 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
547
548 return 0;
549}
550
551static void zeus_ohci_exit(struct device *dev)
552{
553 /* Power-off port 2 */
554 gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
555 gpio_free(ZEUS_USB2_PWREN_GPIO);
556}
557
558static struct pxaohci_platform_data zeus_ohci_platform_data = {
559 .port_mode = PMM_NPS_MODE,
7ff27dfa
MZ		 560 /* Clear Power Control Polarity Low and set Power Sense
561 * Polarity Low. Supply power to USB ports. */
562 .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
e491a11c
MZ		 563 .init = zeus_ohci_init,
564 .exit = zeus_ohci_exit,
565};
566
567/*
568 * Flat Panel
569 */
570
571static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
572{
573 gpio_set_value(ZEUS_LCD_EN_GPIO, on);
574}
575
576static void zeus_backlight_power(int on)
577{
578 gpio_set_value(ZEUS_BKLEN_GPIO, on);
579}
580
581static int zeus_setup_fb_gpios(void)
582{
583 int err;
584
585 if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
586 goto out_err;
587
588 if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
589 goto out_err_lcd;
590
591 if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
592 goto out_err_lcd;
593
594 if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
595 goto out_err_bkl;
596
597 return 0;
598
599out_err_bkl:
600 gpio_free(ZEUS_BKLEN_GPIO);
601out_err_lcd:
602 gpio_free(ZEUS_LCD_EN_GPIO);
603out_err:
604 return err;
605}
606
607static struct pxafb_mode_info zeus_fb_mode_info[] = {
608 {
609 .pixclock = 39722,
610
611 .xres = 640,
612 .yres = 480,
613
614 .bpp = 16,
615
616 .hsync_len = 63,
617 .left_margin = 16,
618 .right_margin = 81,
619
620 .vsync_len = 2,
621 .upper_margin = 12,
622 .lower_margin = 31,
623
624 .sync = 0,
625 },
626};
627
628static struct pxafb_mach_info zeus_fb_info = {
629 .modes = zeus_fb_mode_info,
630 .num_modes = 1,
631 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
632 .pxafb_lcd_power = zeus_lcd_power,
633 .pxafb_backlight_power = zeus_backlight_power,
634};
635
636/*
637 * MMC/SD Device
638 *
639 * The card detect interrupt isn't debounced so we delay it by 250ms
640 * to give the card a chance to fully insert/eject.
641 */
642
643static struct pxamci_platform_data zeus_mci_platform_data = {
644 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
f97cab28 645 .detect_delay_ms = 250,
e491a11c
MZ		 646 .gpio_card_detect = ZEUS_MMC_CD_GPIO,
647 .gpio_card_ro = ZEUS_MMC_WP_GPIO,
648 .gpio_card_ro_invert = 1,
649 .gpio_power = -1
650};
651
652/*
653 * USB Device Controller
654 */
655static void zeus_udc_command(int cmd)
656{
657 switch (cmd) {
658 case PXA2XX_UDC_CMD_DISCONNECT:
659 pr_info("zeus: disconnecting USB client\n");
660 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
661 break;
662
663 case PXA2XX_UDC_CMD_CONNECT:
664 pr_info("zeus: connecting USB client\n");
665 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
666 break;
667 }
668}
669
670static struct pxa2xx_udc_mach_info zeus_udc_info = {
671 .udc_command = zeus_udc_command,
672};
673
98acdbe4 674#ifdef CONFIG_PM
e491a11c
MZ		 675static void zeus_power_off(void)
676{
677 local_irq_disable();
4f5ad99b 678 pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
e491a11c 679}
98acdbe4
SS		 680#else
681#define zeus_power_off NULL
682#endif
e491a11c 683
a1916eb0
MZ		 684#ifdef CONFIG_APM_EMULATION
685static void zeus_get_power_status(struct apm_power_info *info)
686{
687 /* Power supply is always present */
688 info->ac_line_status = APM_AC_ONLINE;
689 info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
690 info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT;
691}
692
693static inline void zeus_setup_apm(void)
694{
695 apm_get_power_status = zeus_get_power_status;
696}
697#else
698static inline void zeus_setup_apm(void)
699{
700}
701#endif
702
100627b4
MZ		 703static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
704 unsigned ngpio, void *context)
e491a11c
MZ		 705{
706 int i;
707 u8 pcb_info = 0;
708
709 for (i = 0; i < 8; i++) {
710 int pcb_bit = gpio + i + 8;
711
712 if (gpio_request(pcb_bit, "pcb info")) {
713 dev_err(&client->dev, "Can't request pcb info %d\n", i);
714 continue;
715 }
716
717 if (gpio_direction_input(pcb_bit)) {
718 dev_err(&client->dev, "Can't read pcb info %d\n", i);
719 gpio_free(pcb_bit);
720 continue;
721 }
722
723 pcb_info |= !!gpio_get_value(pcb_bit) << i;
724
725 gpio_free(pcb_bit);
726 }
727
728 dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
729 pcb_info >> 4, pcb_info & 0xf);
730
731 return 0;
732}
733
734static struct pca953x_platform_data zeus_pca953x_pdata[] = {
735 [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
736 [1] = {
737 .gpio_base = ZEUS_EXT1_GPIO_BASE,
738 .setup = zeus_get_pcb_info,
739 },
740 [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
741};
742
743static struct i2c_board_info __initdata zeus_i2c_devices[] = {
744 {
745 I2C_BOARD_INFO("pca9535", 0x21),
746 .platform_data = &zeus_pca953x_pdata[0],
747 },
748 {
749 I2C_BOARD_INFO("pca9535", 0x22),
750 .platform_data = &zeus_pca953x_pdata[1],
751 },
752 {
753 I2C_BOARD_INFO("pca9535", 0x20),
754 .platform_data = &zeus_pca953x_pdata[2],
755 .irq = gpio_to_irq(ZEUS_EXTGPIO_GPIO),
756 },
757 { I2C_BOARD_INFO("lm75a", 0x48) },
758 { I2C_BOARD_INFO("24c01", 0x50) },
759 { I2C_BOARD_INFO("isl1208", 0x6f) },
760};
761
762static mfp_cfg_t zeus_pin_config[] __initdata = {
c11b6a42
EM		 763 /* AC97 */
764 GPIO28_AC97_BITCLK,
765 GPIO29_AC97_SDATA_IN_0,
766 GPIO30_AC97_SDATA_OUT,
767 GPIO31_AC97_SYNC,
768
e491a11c
MZ		 769 GPIO15_nCS_1,
770 GPIO78_nCS_2,
771 GPIO80_nCS_4,
772 GPIO33_nCS_5,
773
774 GPIO22_GPIO,
775 GPIO32_MMC_CLK,
776 GPIO92_MMC_DAT_0,
777 GPIO109_MMC_DAT_1,
778 GPIO110_MMC_DAT_2,
779 GPIO111_MMC_DAT_3,
780 GPIO112_MMC_CMD,
781
782 GPIO88_USBH1_PWR,
783 GPIO89_USBH1_PEN,
784 GPIO119_USBH2_PWR,
785 GPIO120_USBH2_PEN,
786
787 GPIO86_LCD_LDD_16,
788 GPIO87_LCD_LDD_17,
789
790 GPIO102_GPIO,
791 GPIO104_CIF_DD_2,
792 GPIO105_CIF_DD_1,
793
438a22fe
MZ		 794 GPIO81_SSP3_TXD,
795 GPIO82_SSP3_RXD,
796 GPIO83_SSP3_SFRM,
797 GPIO84_SSP3_SCLK,
798
e491a11c
MZ		 799 GPIO48_nPOE,
800 GPIO49_nPWE,
801 GPIO50_nPIOR,
802 GPIO51_nPIOW,
803 GPIO85_nPCE_1,
804 GPIO54_nPCE_2,
805 GPIO79_PSKTSEL,
806 GPIO55_nPREG,
807 GPIO56_nPWAIT,
808 GPIO57_nIOIS16,
809 GPIO36_GPIO, /* CF CD */
810 GPIO97_GPIO, /* CF PWREN */
811 GPIO99_GPIO, /* CF RDY */
812};
813
5f86ceba
MZ		 814/*
815 * DM9k MSCx settings: SRAM, 16 bits
816 * 17 cycles delay first access
817 * 5 cycles delay next access
818 * 13 cycles recovery time
819 * faster device
820 */
821#define DM9K_MSC_VALUE 0xe4c9
822
e491a11c
MZ		 823static void __init zeus_init(void)
824{
5f86ceba 825 u16 dm9000_msc = DM9K_MSC_VALUE;
ad68bb9f 826 u32 msc0, msc1;
e491a11c
MZ		 827
828 system_rev = __raw_readw(ZEUS_CPLD_VERSION);
829 pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
830
831 /* Fix timings for dm9000s (CS1/CS2)*/
bc3e55c6
MV		 832 msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
833 msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
ad68bb9f
MV		 834 __raw_writel(msc0, MSC0);
835 __raw_writel(msc1, MSC1);
e491a11c
MZ		 836
837 pm_power_off = zeus_power_off;
a1916eb0 838 zeus_setup_apm();
e491a11c
MZ		 839
840 pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
841
842 platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
843
844 pxa_set_ohci_info(&zeus_ohci_platform_data);
845
846 if (zeus_setup_fb_gpios())
847 pr_err("Failed to setup fb gpios\n");
848 else
4321e1a1 849 pxa_set_fb_info(NULL, &zeus_fb_info);
e491a11c
MZ		 850
851 pxa_set_mci_info(&zeus_mci_platform_data);
852 pxa_set_udc_info(&zeus_udc_info);
853 pxa_set_ac97_info(&zeus_ac97_info);
854 pxa_set_i2c_info(NULL);
855 i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
438a22fe
MZ		 856 pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
857 spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
e491a11c
MZ		 858}
859
860static struct map_desc zeus_io_desc[] __initdata = {
861 {
862 .virtual = ZEUS_CPLD_VERSION,
863 .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
864 .length = 0x1000,
865 .type = MT_DEVICE,
866 },
867 {
868 .virtual = ZEUS_CPLD_ISA_IRQ,
869 .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
870 .length = 0x1000,
871 .type = MT_DEVICE,
872 },
873 {
874 .virtual = ZEUS_CPLD_CONTROL,
875 .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
876 .length = 0x1000,
877 .type = MT_DEVICE,
878 },
e491a11c
MZ		 879 {
880 .virtual = ZEUS_PC104IO,
881 .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
882 .length = 0x00800000,
883 .type = MT_DEVICE,
884 },
885};
886
887static void __init zeus_map_io(void)
888{
851982c1 889 pxa27x_map_io();
e491a11c
MZ		 890
891 iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
892
893 /* Clear PSPR to ensure a full restart on wake-up. */
894 PMCR = PSPR = 0;
895
896 /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
897 OSCC |= OSCC_OON;
898
899 /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
900 * float chip selects and PCMCIA */
901 PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
902}
903
90ac0dfd 904MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
e491a11c 905 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
e491a11c
MZ		 906 .boot_params = 0xa0000100,
907 .map_io = zeus_map_io,
6ac6b817 908 .nr_irqs = ZEUS_NR_IRQS,
e491a11c
MZ		 909 .init_irq = zeus_init_irq,
910 .timer = &pxa_timer,
911 .init_machine = zeus_init,
912MACHINE_END
913
Linux kernel - Deliverables
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