Commit | Line | Data |
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8ad68bbf CM |
1 | /* |
2 | * linux/arch/arm/mach-realview/core.c | |
3 | * | |
4 | * Copyright (C) 1999 - 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
8ad68bbf | 21 | #include <linux/init.h> |
1be7228d | 22 | #include <linux/platform_device.h> |
8ad68bbf | 23 | #include <linux/dma-mapping.h> |
edbaa603 | 24 | #include <linux/device.h> |
8ad68bbf | 25 | #include <linux/interrupt.h> |
a62c80e5 RK |
26 | #include <linux/amba/bus.h> |
27 | #include <linux/amba/clcd.h> | |
fced80c7 | 28 | #include <linux/io.h> |
c5142e84 | 29 | #include <linux/smsc911x.h> |
6be62ba2 | 30 | #include <linux/ata_platform.h> |
6ef297f8 | 31 | #include <linux/amba/mmci.h> |
5a0e3ad6 | 32 | #include <linux/gfp.h> |
b8b87aef | 33 | #include <linux/mtd/physmap.h> |
8ad68bbf | 34 | |
a09e64fb | 35 | #include <mach/hardware.h> |
8ad68bbf | 36 | #include <asm/irq.h> |
68c3d935 | 37 | #include <asm/mach-types.h> |
8ad68bbf | 38 | #include <asm/hardware/arm_timer.h> |
c5a0adb5 | 39 | #include <asm/hardware/icst.h> |
8ad68bbf CM |
40 | |
41 | #include <asm/mach/arch.h> | |
8ad68bbf | 42 | #include <asm/mach/irq.h> |
8ad68bbf | 43 | #include <asm/mach/map.h> |
8ad68bbf | 44 | |
8ad68bbf | 45 | |
ee8c9571 CM |
46 | #include <mach/platform.h> |
47 | #include <mach/irqs.h> | |
8a9618f5 | 48 | #include <asm/hardware/timer-sp.h> |
ee8c9571 | 49 | |
3cb5ee49 | 50 | #include <plat/clcd.h> |
1da0c89c RK |
51 | #include <plat/sched_clock.h> |
52 | ||
8ad68bbf | 53 | #include "core.h" |
8ad68bbf | 54 | |
8ad68bbf CM |
55 | #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) |
56 | ||
667f390b | 57 | static void realview_flash_set_vpp(struct platform_device *pdev, int on) |
8ad68bbf CM |
58 | { |
59 | u32 val; | |
60 | ||
61 | val = __raw_readl(REALVIEW_FLASHCTRL); | |
62 | if (on) | |
63 | val |= REALVIEW_FLASHPROG_FLVPPEN; | |
64 | else | |
65 | val &= ~REALVIEW_FLASHPROG_FLVPPEN; | |
66 | __raw_writel(val, REALVIEW_FLASHCTRL); | |
67 | } | |
68 | ||
b8b87aef | 69 | static struct physmap_flash_data realview_flash_data = { |
8ad68bbf | 70 | .width = 4, |
8ad68bbf CM |
71 | .set_vpp = realview_flash_set_vpp, |
72 | }; | |
73 | ||
8ad68bbf | 74 | struct platform_device realview_flash_device = { |
b8b87aef | 75 | .name = "physmap-flash", |
8ad68bbf CM |
76 | .id = 0, |
77 | .dev = { | |
78 | .platform_data = &realview_flash_data, | |
79 | }, | |
8ad68bbf CM |
80 | }; |
81 | ||
a44ddfd5 CM |
82 | int realview_flash_register(struct resource *res, u32 num) |
83 | { | |
84 | realview_flash_device.resource = res; | |
85 | realview_flash_device.num_resources = num; | |
86 | return platform_device_register(&realview_flash_device); | |
87 | } | |
88 | ||
c5142e84 SG |
89 | static struct smsc911x_platform_config smsc911x_config = { |
90 | .flags = SMSC911X_USE_32BIT, | |
91 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, | |
92 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | |
93 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
0a5b2f6b CM |
94 | }; |
95 | ||
0a381330 | 96 | static struct platform_device realview_eth_device = { |
c5142e84 | 97 | .name = "smsc911x", |
0a381330 CM |
98 | .id = 0, |
99 | .num_resources = 2, | |
100 | }; | |
101 | ||
102 | int realview_eth_register(const char *name, struct resource *res) | |
103 | { | |
104 | if (name) | |
105 | realview_eth_device.name = name; | |
106 | realview_eth_device.resource = res; | |
c5142e84 SG |
107 | if (strcmp(realview_eth_device.name, "smsc911x") == 0) |
108 | realview_eth_device.dev.platform_data = &smsc911x_config; | |
0a381330 CM |
109 | |
110 | return platform_device_register(&realview_eth_device); | |
7db21712 CM |
111 | } |
112 | ||
113 | struct platform_device realview_usb_device = { | |
114 | .name = "isp1760", | |
115 | .num_resources = 2, | |
116 | }; | |
117 | ||
118 | int realview_usb_register(struct resource *res) | |
119 | { | |
120 | realview_usb_device.resource = res; | |
121 | return platform_device_register(&realview_usb_device); | |
0a381330 CM |
122 | } |
123 | ||
6be62ba2 CM |
124 | static struct pata_platform_info pata_platform_data = { |
125 | .ioport_shift = 1, | |
126 | }; | |
127 | ||
128 | static struct resource pata_resources[] = { | |
129 | [0] = { | |
130 | .start = REALVIEW_CF_BASE, | |
131 | .end = REALVIEW_CF_BASE + 0xff, | |
132 | .flags = IORESOURCE_MEM, | |
133 | }, | |
134 | [1] = { | |
135 | .start = REALVIEW_CF_BASE + 0x100, | |
136 | .end = REALVIEW_CF_BASE + SZ_4K - 1, | |
137 | .flags = IORESOURCE_MEM, | |
138 | }, | |
139 | }; | |
140 | ||
141 | struct platform_device realview_cf_device = { | |
142 | .name = "pata_platform", | |
143 | .id = -1, | |
144 | .num_resources = ARRAY_SIZE(pata_resources), | |
145 | .resource = pata_resources, | |
146 | .dev = { | |
147 | .platform_data = &pata_platform_data, | |
148 | }, | |
149 | }; | |
150 | ||
6b65cd74 RK |
151 | static struct resource realview_i2c_resource = { |
152 | .start = REALVIEW_I2C_BASE, | |
153 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, | |
154 | .flags = IORESOURCE_MEM, | |
155 | }; | |
156 | ||
157 | struct platform_device realview_i2c_device = { | |
158 | .name = "versatile-i2c", | |
533ad5e6 | 159 | .id = 0, |
6b65cd74 RK |
160 | .num_resources = 1, |
161 | .resource = &realview_i2c_resource, | |
162 | }; | |
163 | ||
533ad5e6 CM |
164 | static struct i2c_board_info realview_i2c_board_info[] = { |
165 | { | |
64e8be6e | 166 | I2C_BOARD_INFO("ds1338", 0xd0 >> 1), |
533ad5e6 CM |
167 | }, |
168 | }; | |
169 | ||
170 | static int __init realview_i2c_init(void) | |
171 | { | |
172 | return i2c_register_board_info(0, realview_i2c_board_info, | |
173 | ARRAY_SIZE(realview_i2c_board_info)); | |
174 | } | |
175 | arch_initcall(realview_i2c_init); | |
176 | ||
8ad68bbf CM |
177 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) |
178 | ||
98b0979f RK |
179 | /* |
180 | * This is only used if GPIOLIB support is disabled | |
181 | */ | |
8ad68bbf CM |
182 | static unsigned int realview_mmc_status(struct device *dev) |
183 | { | |
184 | struct amba_device *adev = container_of(dev, struct amba_device, dev); | |
185 | u32 mask; | |
186 | ||
48f1d5a3 LW |
187 | if (machine_is_realview_pb1176()) { |
188 | static bool inserted = false; | |
189 | ||
190 | /* | |
191 | * The PB1176 does not have the status register, | |
192 | * assume it is inserted at startup, then invert | |
193 | * for each call so card insertion/removal will | |
194 | * be detected anyway. This will not be called if | |
195 | * GPIO on PL061 is active, which is the proper | |
196 | * way to do this on the PB1176. | |
197 | */ | |
198 | inserted = !inserted; | |
199 | return inserted ? 0 : 1; | |
200 | } | |
201 | ||
8ad68bbf CM |
202 | if (adev->res.start == REALVIEW_MMCI0_BASE) |
203 | mask = 1; | |
204 | else | |
205 | mask = 2; | |
206 | ||
74bc8093 | 207 | return readl(REALVIEW_SYSMCI) & mask; |
8ad68bbf CM |
208 | } |
209 | ||
6ef297f8 | 210 | struct mmci_platform_data realview_mmc0_plat_data = { |
8ad68bbf CM |
211 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
212 | .status = realview_mmc_status, | |
98b0979f RK |
213 | .gpio_wp = 17, |
214 | .gpio_cd = 16, | |
29719445 | 215 | .cd_invert = true, |
8ad68bbf CM |
216 | }; |
217 | ||
6ef297f8 | 218 | struct mmci_platform_data realview_mmc1_plat_data = { |
8ad68bbf CM |
219 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
220 | .status = realview_mmc_status, | |
98b0979f RK |
221 | .gpio_wp = 19, |
222 | .gpio_cd = 18, | |
29719445 | 223 | .cd_invert = true, |
8ad68bbf CM |
224 | }; |
225 | ||
631e55f9 | 226 | void __init realview_init_early(void) |
cf30fb4a | 227 | { |
631e55f9 RK |
228 | void __iomem *sys = __io_address(REALVIEW_SYS_BASE); |
229 | ||
631e55f9 | 230 | versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000); |
cf30fb4a | 231 | } |
cf30fb4a | 232 | |
8ad68bbf CM |
233 | /* |
234 | * CLCD support. | |
235 | */ | |
8ad68bbf CM |
236 | #define SYS_CLCD_NLCDIOON (1 << 2) |
237 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) | |
238 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) | |
239 | #define SYS_CLCD_ID_MASK (0x1f << 8) | |
240 | #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8) | |
241 | #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8) | |
242 | #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8) | |
243 | #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) | |
244 | #define SYS_CLCD_ID_VGA (0x1f << 8) | |
245 | ||
8ad68bbf CM |
246 | /* |
247 | * Disable all display connectors on the interface module. | |
248 | */ | |
249 | static void realview_clcd_disable(struct clcd_fb *fb) | |
250 | { | |
251 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; | |
252 | u32 val; | |
253 | ||
254 | val = readl(sys_clcd); | |
255 | val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; | |
256 | writel(val, sys_clcd); | |
257 | } | |
258 | ||
259 | /* | |
260 | * Enable the relevant connector on the interface module. | |
261 | */ | |
262 | static void realview_clcd_enable(struct clcd_fb *fb) | |
263 | { | |
264 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; | |
265 | u32 val; | |
266 | ||
8ad68bbf | 267 | /* |
9e7714d0 | 268 | * Enable the PSUs |
8ad68bbf | 269 | */ |
9e7714d0 | 270 | val = readl(sys_clcd); |
8ad68bbf CM |
271 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; |
272 | writel(val, sys_clcd); | |
273 | } | |
274 | ||
3cb5ee49 RK |
275 | /* |
276 | * Detect which LCD panel is connected, and return the appropriate | |
277 | * clcd_panel structure. Note: we do not have any information on | |
278 | * the required timings for the 8.4in panel, so we presently assume | |
279 | * VGA timings. | |
280 | */ | |
8ad68bbf CM |
281 | static int realview_clcd_setup(struct clcd_fb *fb) |
282 | { | |
3cb5ee49 RK |
283 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
284 | const char *panel_name, *vga_panel_name; | |
c34a1025 | 285 | unsigned long framesize; |
3cb5ee49 | 286 | u32 val; |
8ad68bbf | 287 | |
3cb5ee49 | 288 | if (machine_is_realview_eb()) { |
c34a1025 CT |
289 | /* VGA, 16bpp */ |
290 | framesize = 640 * 480 * 2; | |
3cb5ee49 RK |
291 | vga_panel_name = "VGA"; |
292 | } else { | |
c34a1025 CT |
293 | /* XVGA, 16bpp */ |
294 | framesize = 1024 * 768 * 2; | |
3cb5ee49 | 295 | vga_panel_name = "XVGA"; |
8ad68bbf CM |
296 | } |
297 | ||
3cb5ee49 RK |
298 | val = readl(sys_clcd) & SYS_CLCD_ID_MASK; |
299 | if (val == SYS_CLCD_ID_SANYO_3_8) | |
300 | panel_name = "Sanyo TM38QV67A02A"; | |
301 | else if (val == SYS_CLCD_ID_SANYO_2_5) | |
302 | panel_name = "Sanyo QVGA Portrait"; | |
303 | else if (val == SYS_CLCD_ID_EPSON_2_2) | |
304 | panel_name = "Epson L2F50113T00"; | |
305 | else if (val == SYS_CLCD_ID_VGA) | |
306 | panel_name = vga_panel_name; | |
307 | else { | |
308 | pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val); | |
309 | panel_name = vga_panel_name; | |
310 | } | |
8ad68bbf | 311 | |
3cb5ee49 RK |
312 | fb->panel = versatile_clcd_get_panel(panel_name); |
313 | if (!fb->panel) | |
314 | return -EINVAL; | |
8ad68bbf | 315 | |
3cb5ee49 | 316 | return versatile_clcd_setup_dma(fb, framesize); |
8ad68bbf CM |
317 | } |
318 | ||
319 | struct clcd_board clcd_plat_data = { | |
320 | .name = "RealView", | |
3cb5ee49 | 321 | .caps = CLCD_CAP_ALL, |
8ad68bbf CM |
322 | .check = clcdfb_check, |
323 | .decode = clcdfb_decode, | |
324 | .disable = realview_clcd_disable, | |
325 | .enable = realview_clcd_enable, | |
326 | .setup = realview_clcd_setup, | |
3cb5ee49 RK |
327 | .mmap = versatile_clcd_mmap_dma, |
328 | .remove = versatile_clcd_remove_dma, | |
8ad68bbf CM |
329 | }; |
330 | ||
8ad68bbf CM |
331 | /* |
332 | * Where is the timer (VA)? | |
333 | */ | |
80192735 CM |
334 | void __iomem *timer0_va_base; |
335 | void __iomem *timer1_va_base; | |
336 | void __iomem *timer2_va_base; | |
337 | void __iomem *timer3_va_base; | |
8ad68bbf | 338 | |
8ad68bbf | 339 | /* |
a8655e83 | 340 | * Set up the clock source and clock events devices |
8ad68bbf | 341 | */ |
8cc4c548 | 342 | void __init realview_timer_init(unsigned int timer_irq) |
8ad68bbf CM |
343 | { |
344 | u32 val; | |
345 | ||
346 | /* | |
347 | * set clock frequency: | |
348 | * REALVIEW_REFCLK is 32KHz | |
349 | * REALVIEW_TIMCLK is 1MHz | |
350 | */ | |
351 | val = readl(__io_address(REALVIEW_SCTL_BASE)); | |
352 | writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) | | |
353 | (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | | |
354 | (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) | | |
355 | (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val, | |
356 | __io_address(REALVIEW_SCTL_BASE)); | |
357 | ||
358 | /* | |
359 | * Initialise to a known state (all timers off) | |
360 | */ | |
80192735 CM |
361 | writel(0, timer0_va_base + TIMER_CTRL); |
362 | writel(0, timer1_va_base + TIMER_CTRL); | |
363 | writel(0, timer2_va_base + TIMER_CTRL); | |
364 | writel(0, timer3_va_base + TIMER_CTRL); | |
8ad68bbf | 365 | |
fb593cf3 | 366 | sp804_clocksource_init(timer3_va_base, "timer3"); |
57cc4f7d | 367 | sp804_clockevents_init(timer0_va_base, timer_irq, "timer0"); |
8ad68bbf | 368 | } |
5b39d154 CM |
369 | |
370 | /* | |
371 | * Setup the memory banks. | |
372 | */ | |
0744a3ee | 373 | void realview_fixup(struct tag *tags, char **from, struct meminfo *meminfo) |
5b39d154 CM |
374 | { |
375 | /* | |
376 | * Most RealView platforms have 512MB contiguous RAM at 0x70000000. | |
377 | * Half of this is mirrored at 0. | |
378 | */ | |
379 | #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET | |
380 | meminfo->bank[0].start = 0x70000000; | |
381 | meminfo->bank[0].size = SZ_512M; | |
382 | meminfo->nr_banks = 1; | |
383 | #else | |
384 | meminfo->bank[0].start = 0; | |
385 | meminfo->bank[0].size = SZ_256M; | |
386 | meminfo->nr_banks = 1; | |
387 | #endif | |
388 | } |