[deliverable/linux.git] / arch / arm / mach-realview / core.c

/*
 *  linux/arch/arm/mach-realview/core.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/io.h>
#include <linux/smsc911x.h>
#include <linux/ata_platform.h>
#include <linux/amba/mmci.h>
#include <linux/gfp.h>

#include <asm/clkdev.h>
#include <asm/system.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>

#include <asm/hardware/gic.h>

#include <mach/clkdev.h>
#include <mach/platform.h>
#include <mach/irqs.h>
#include <plat/timer-sp.h>

#include "core.h"

/* used by entry-macro.S and platsmp.c */
void __iomem *gic_cpu_base_addr;

#ifdef CONFIG_ZONE_DMA
/*
 * Adjust the zones if there are restrictions for DMA access.
 */
void __init realview_adjust_zones(int node, unsigned long *size,
				  unsigned long *hole)
{
	unsigned long dma_size = SZ_256M >> PAGE_SHIFT;

	if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
		return;

	size[ZONE_NORMAL] = size[0] - dma_size;
	size[ZONE_DMA] = dma_size;
	hole[ZONE_NORMAL] = hole[0];
	hole[ZONE_DMA] = 0;
}
#endif


#define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)

static int realview_flash_init(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);

	return 0;
}

static void realview_flash_exit(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static void realview_flash_set_vpp(int on)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	if (on)
		val |= REALVIEW_FLASHPROG_FLVPPEN;
	else
		val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static struct flash_platform_data realview_flash_data = {
	.map_name		= "cfi_probe",
	.width			= 4,
	.init			= realview_flash_init,
	.exit			= realview_flash_exit,
	.set_vpp		= realview_flash_set_vpp,
};

struct platform_device realview_flash_device = {
	.name			= "armflash",
	.id			= 0,
	.dev			= {
		.platform_data	= &realview_flash_data,
	},
};

int realview_flash_register(struct resource *res, u32 num)
{
	realview_flash_device.resource = res;
	realview_flash_device.num_resources = num;
	return platform_device_register(&realview_flash_device);
}

static struct smsc911x_platform_config smsc911x_config = {
	.flags		= SMSC911X_USE_32BIT,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct platform_device realview_eth_device = {
	.name		= "smsc911x",
	.id		= 0,
	.num_resources	= 2,
};

int realview_eth_register(const char *name, struct resource *res)
{
	if (name)
		realview_eth_device.name = name;
	realview_eth_device.resource = res;
	if (strcmp(realview_eth_device.name, "smsc911x") == 0)
		realview_eth_device.dev.platform_data = &smsc911x_config;

	return platform_device_register(&realview_eth_device);
}

struct platform_device realview_usb_device = {
	.name			= "isp1760",
	.num_resources		= 2,
};

int realview_usb_register(struct resource *res)
{
	realview_usb_device.resource = res;
	return platform_device_register(&realview_usb_device);
}

static struct pata_platform_info pata_platform_data = {
	.ioport_shift		= 1,
};

static struct resource pata_resources[] = {
	[0] = {
		.start		= REALVIEW_CF_BASE,
		.end		= REALVIEW_CF_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= REALVIEW_CF_BASE + 0x100,
		.end		= REALVIEW_CF_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

struct platform_device realview_cf_device = {
	.name			= "pata_platform",
	.id			= -1,
	.num_resources		= ARRAY_SIZE(pata_resources),
	.resource		= pata_resources,
	.dev			= {
		.platform_data	= &pata_platform_data,
	},
};

static struct resource realview_i2c_resource = {
	.start		= REALVIEW_I2C_BASE,
	.end		= REALVIEW_I2C_BASE + SZ_4K - 1,
	.flags		= IORESOURCE_MEM,
};

struct platform_device realview_i2c_device = {
	.name		= "versatile-i2c",
	.id		= 0,
	.num_resources	= 1,
	.resource	= &realview_i2c_resource,
};

static struct i2c_board_info realview_i2c_board_info[] = {
	{
		I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
	},
};

static int __init realview_i2c_init(void)
{
	return i2c_register_board_info(0, realview_i2c_board_info,
				       ARRAY_SIZE(realview_i2c_board_info));
}
arch_initcall(realview_i2c_init);

#define REALVIEW_SYSMCI	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)

/*
 * This is only used if GPIOLIB support is disabled
 */
static unsigned int realview_mmc_status(struct device *dev)
{
	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	u32 mask;

	if (adev->res.start == REALVIEW_MMCI0_BASE)
		mask = 1;
	else
		mask = 2;

	return !(readl(REALVIEW_SYSMCI) & mask);
}

struct mmci_platform_data realview_mmc0_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
	.gpio_wp	= 17,
	.gpio_cd	= 16,
};

struct mmci_platform_data realview_mmc1_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
	.gpio_wp	= 19,
	.gpio_cd	= 18,
};

/*
 * Clock handling
 */
static const struct icst_params realview_oscvco_params = {
	.ref		= 24000000,
	.vco_max	= ICST307_VCO_MAX,
	.vco_min	= ICST307_VCO_MIN,
	.vd_min		= 4 + 8,
	.vd_max		= 511 + 8,
	.rd_min		= 1 + 2,
	.rd_max		= 127 + 2,
	.s2div		= icst307_s2div,
	.idx2s		= icst307_idx2s,
};

static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
{
	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
	u32 val;

	val = readl(clk->vcoreg) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, sys_lock);
	writel(val, clk->vcoreg);
	writel(0, sys_lock);
}

static const struct clk_ops oscvco_clk_ops = {
	.round	= icst_clk_round,
	.set	= icst_clk_set,
	.setvco	= realview_oscvco_set,
};

static struct clk oscvco_clk = {
	.ops	= &oscvco_clk_ops,
	.params	= &realview_oscvco_params,
};

/*
 * These are fixed clocks.
 */
static struct clk ref24_clk = {
	.rate	= 24000000,
};

static struct clk_lookup lookups[] = {
	{	/* UART0 */
		.dev_id		= "dev:uart0",
		.clk		= &ref24_clk,
	}, {	/* UART1 */
		.dev_id		= "dev:uart1",
		.clk		= &ref24_clk,
	}, {	/* UART2 */
		.dev_id		= "dev:uart2",
		.clk		= &ref24_clk,
	}, {	/* UART3 */
		.dev_id		= "fpga:uart3",
		.clk		= &ref24_clk,
	}, {	/* KMI0 */
		.dev_id		= "fpga:kmi0",
		.clk		= &ref24_clk,
	}, {	/* KMI1 */
		.dev_id		= "fpga:kmi1",
		.clk		= &ref24_clk,
	}, {	/* MMC0 */
		.dev_id		= "fpga:mmc0",
		.clk		= &ref24_clk,
	}, {	/* EB:CLCD */
		.dev_id		= "dev:clcd",
		.clk		= &oscvco_clk,
	}, {	/* PB:CLCD */
		.dev_id		= "issp:clcd",
		.clk		= &oscvco_clk,
	}
};

static int __init clk_init(void)
{
	if (machine_is_realview_pb1176())
		oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	else
		oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	return 0;
}
arch_initcall(clk_init);

/*
 * CLCD support.
 */
#define SYS_CLCD_NLCDIOON	(1 << 2)
#define SYS_CLCD_VDDPOSSWITCH	(1 << 3)
#define SYS_CLCD_PWR3V5SWITCH	(1 << 4)
#define SYS_CLCD_ID_MASK	(0x1f << 8)
#define SYS_CLCD_ID_SANYO_3_8	(0x00 << 8)
#define SYS_CLCD_ID_UNKNOWN_8_4	(0x01 << 8)
#define SYS_CLCD_ID_EPSON_2_2	(0x02 << 8)
#define SYS_CLCD_ID_SANYO_2_5	(0x07 << 8)
#define SYS_CLCD_ID_VGA		(0x1f << 8)

static struct clcd_panel vga = {
	.mode		= {
		.name		= "VGA",
		.refresh	= 60,
		.xres		= 640,
		.yres		= 480,
		.pixclock	= 39721,
		.left_margin	= 40,
		.right_margin	= 24,
		.upper_margin	= 32,
		.lower_margin	= 11,
		.hsync_len	= 96,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel xvga = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15748,
		.left_margin	= 152,
		.right_margin	= 48,
		.upper_margin	= 23,
		.lower_margin	= 3,
		.hsync_len	= 104,
		.vsync_len	= 4,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_3_8_in = {
	.mode		= {
		.name		= "Sanyo QVGA",
		.refresh	= 116,
		.xres		= 320,
		.yres		= 240,
		.pixclock	= 100000,
		.left_margin	= 6,
		.right_margin	= 6,
		.upper_margin	= 5,
		.lower_margin	= 5,
		.hsync_len	= 6,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_2_5_in = {
	.mode		= {
		.name		= "Sanyo QVGA Portrait",
		.refresh	= 116,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 100000,
		.left_margin	= 20,
		.right_margin	= 10,
		.upper_margin	= 2,
		.lower_margin	= 2,
		.hsync_len	= 10,
		.vsync_len	= 2,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_IVS | TIM2_IHS | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel epson_2_2_in = {
	.mode		= {
		.name		= "Epson QCIF",
		.refresh	= 390,
		.xres		= 176,
		.yres		= 220,
		.pixclock	= 62500,
		.left_margin	= 3,
		.right_margin	= 2,
		.upper_margin	= 1,
		.lower_margin	= 0,
		.hsync_len	= 3,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

/*
 * Detect which LCD panel is connected, and return the appropriate
 * clcd_panel structure.  Note: we do not have any information on
 * the required timings for the 8.4in panel, so we presently assume
 * VGA timings.
 */
static struct clcd_panel *realview_clcd_panel(void)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	struct clcd_panel *vga_panel;
	struct clcd_panel *panel;
	u32 val;

	if (machine_is_realview_eb())
		vga_panel = &vga;
	else
		vga_panel = &xvga;

	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	if (val == SYS_CLCD_ID_SANYO_3_8)
		panel = &sanyo_3_8_in;
	else if (val == SYS_CLCD_ID_SANYO_2_5)
		panel = &sanyo_2_5_in;
	else if (val == SYS_CLCD_ID_EPSON_2_2)
		panel = &epson_2_2_in;
	else if (val == SYS_CLCD_ID_VGA)
		panel = vga_panel;
	else {
		printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
			val);
		panel = vga_panel;
	}

	return panel;
}

/*
 * Disable all display connectors on the interface module.
 */
static void realview_clcd_disable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	val = readl(sys_clcd);
	val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

/*
 * Enable the relevant connector on the interface module.
 */
static void realview_clcd_enable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	/*
	 * Enable the PSUs
	 */
	val = readl(sys_clcd);
	val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

static int realview_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize;
	dma_addr_t dma;

	if (machine_is_realview_eb())
		/* VGA, 16bpp */
		framesize = 640 * 480 * 2;
	else
		/* XVGA, 16bpp */
		framesize = 1024 * 768 * 2;

	fb->panel		= realview_clcd_panel();

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
						    &dma, GFP_KERNEL | GFP_DMA);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
		return -ENOMEM;
	}

	fb->fb.fix.smem_start	= dma;
	fb->fb.fix.smem_len	= framesize;

	return 0;
}

static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma,
				     fb->fb.screen_base,
				     fb->fb.fix.smem_start,
				     fb->fb.fix.smem_len);
}

static void realview_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
			      fb->fb.screen_base, fb->fb.fix.smem_start);
}

struct clcd_board clcd_plat_data = {
	.name		= "RealView",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.disable	= realview_clcd_disable,
	.enable		= realview_clcd_enable,
	.setup		= realview_clcd_setup,
	.mmap		= realview_clcd_mmap,
	.remove		= realview_clcd_remove,
};

#ifdef CONFIG_LEDS
#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)

void realview_leds_event(led_event_t ledevt)
{
	unsigned long flags;
	u32 val;
	u32 led = 1 << smp_processor_id();

	local_irq_save(flags);
	val = readl(VA_LEDS_BASE);

	switch (ledevt) {
	case led_idle_start:
		val = val & ~led;
		break;

	case led_idle_end:
		val = val | led;
		break;

	case led_timer:
		val = val ^ REALVIEW_SYS_LED7;
		break;

	case led_halted:
		val = 0;
		break;

	default:
		break;
	}

	writel(val, VA_LEDS_BASE);
	local_irq_restore(flags);
}
#endif	/* CONFIG_LEDS */

/*
 * Where is the timer (VA)?
 */
void __iomem *timer0_va_base;
void __iomem *timer1_va_base;
void __iomem *timer2_va_base;
void __iomem *timer3_va_base;

/*
 * Set up the clock source and clock events devices
 */
void __init realview_timer_init(unsigned int timer_irq)
{
	u32 val;

	/* 
	 * set clock frequency: 
	 *	REALVIEW_REFCLK is 32KHz
	 *	REALVIEW_TIMCLK is 1MHz
	 */
	val = readl(__io_address(REALVIEW_SCTL_BASE));
	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | 
	       (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
	       __io_address(REALVIEW_SCTL_BASE));

	/*
	 * Initialise to a known state (all timers off)
	 */
	writel(0, timer0_va_base + TIMER_CTRL);
	writel(0, timer1_va_base + TIMER_CTRL);
	writel(0, timer2_va_base + TIMER_CTRL);
	writel(0, timer3_va_base + TIMER_CTRL);

	sp804_clocksource_init(timer3_va_base);
	sp804_clockevents_init(timer0_va_base, timer_irq);
}

/*
 * Setup the memory banks.
 */
void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
		    struct meminfo *meminfo)
{
	/*
	 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
	 * Half of this is mirrored at 0.
	 */
#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
	meminfo->bank[0].start = 0x70000000;
	meminfo->bank[0].size = SZ_512M;
	meminfo->nr_banks = 1;
#else
	meminfo->bank[0].start = 0;
	meminfo->bank[0].size = SZ_256M;
	meminfo->nr_banks = 1;
#endif
}
Commit	Line	Data
8ad68bbf CM	1	/*
	2	* linux/arch/arm/mach-realview/core.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
8ad68bbf	21	#include <linux/init.h>
1be7228d	22	#include <linux/platform_device.h>
8ad68bbf CM	23	#include <linux/dma-mapping.h>
	24	#include <linux/sysdev.h>
	25	#include <linux/interrupt.h>
a62c80e5 RK	26	#include <linux/amba/bus.h>
a62c80e5 RK	27	#include <linux/amba/clcd.h>
fced80c7	28	#include <linux/io.h>
c5142e84	29	#include <linux/smsc911x.h>
6be62ba2	30	#include <linux/ata_platform.h>
6ef297f8	31	#include <linux/amba/mmci.h>
5a0e3ad6	32	#include <linux/gfp.h>
8ad68bbf	33
cf30fb4a	34	#include <asm/clkdev.h>
8ad68bbf	35	#include <asm/system.h>
a09e64fb	36	#include <mach/hardware.h>
8ad68bbf CM	37	#include <asm/irq.h>
8ad68bbf CM	38	#include <asm/leds.h>
68c3d935	39	#include <asm/mach-types.h>
8ad68bbf	40	#include <asm/hardware/arm_timer.h>
c5a0adb5	41	#include <asm/hardware/icst.h>
8ad68bbf CM	42
	43	#include <asm/mach/arch.h>
	44	#include <asm/mach/flash.h>
	45	#include <asm/mach/irq.h>
8ad68bbf	46	#include <asm/mach/map.h>
8ad68bbf CM	47
	48	#include <asm/hardware/gic.h>
	49
f4b8b319	50	#include <mach/clkdev.h>
ee8c9571 CM	51	#include <mach/platform.h>
ee8c9571 CM	52	#include <mach/irqs.h>
e3887714	53	#include <plat/timer-sp.h>
ee8c9571	54
8ad68bbf	55	#include "core.h"
8ad68bbf	56
1bbdf637	57	/* used by entry-macro.S and platsmp.c */
c4057f52 CM	58	void __iomem *gic_cpu_base_addr;
c4057f52 CM	59
c97c5aa8 CM	60	#ifdef CONFIG_ZONE_DMA
	61	/*
	62	* Adjust the zones if there are restrictions for DMA access.
	63	*/
	64	void __init realview_adjust_zones(int node, unsigned long *size,
	65	unsigned long *hole)
	66	{
	67	unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
	68
	69	if (!machine_is_realview_pbx() \|\| node \|\| (size[0] <= dma_size))
	70	return;
	71
	72	size[ZONE_NORMAL] = size[0] - dma_size;
	73	size[ZONE_DMA] = dma_size;
	74	hole[ZONE_NORMAL] = hole[0];
	75	hole[ZONE_DMA] = 0;
	76	}
	77	#endif
	78
8ad68bbf CM	79
	80	#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
	81
	82	static int realview_flash_init(void)
	83	{
	84	u32 val;
	85
	86	val = __raw_readl(REALVIEW_FLASHCTRL);
	87	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	88	__raw_writel(val, REALVIEW_FLASHCTRL);
	89
	90	return 0;
	91	}
	92
	93	static void realview_flash_exit(void)
	94	{
	95	u32 val;
	96
	97	val = __raw_readl(REALVIEW_FLASHCTRL);
	98	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	99	__raw_writel(val, REALVIEW_FLASHCTRL);
	100	}
	101
	102	static void realview_flash_set_vpp(int on)
	103	{
	104	u32 val;
	105
	106	val = __raw_readl(REALVIEW_FLASHCTRL);
	107	if (on)
	108	val \|= REALVIEW_FLASHPROG_FLVPPEN;
	109	else
	110	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	111	__raw_writel(val, REALVIEW_FLASHCTRL);
	112	}
	113
	114	static struct flash_platform_data realview_flash_data = {
	115	.map_name = "cfi_probe",
	116	.width = 4,
	117	.init = realview_flash_init,
	118	.exit = realview_flash_exit,
	119	.set_vpp = realview_flash_set_vpp,
	120	};
	121
8ad68bbf CM	122	struct platform_device realview_flash_device = {
	123	.name = "armflash",
	124	.id = 0,
	125	.dev = {
	126	.platform_data = &realview_flash_data,
	127	},
8ad68bbf CM	128	};
8ad68bbf CM	129
a44ddfd5 CM	130	int realview_flash_register(struct resource *res, u32 num)
	131	{
	132	realview_flash_device.resource = res;
	133	realview_flash_device.num_resources = num;
	134	return platform_device_register(&realview_flash_device);
	135	}
	136
c5142e84 SG	137	static struct smsc911x_platform_config smsc911x_config = {
	138	.flags = SMSC911X_USE_32BIT,
	139	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	140	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	141	.phy_interface = PHY_INTERFACE_MODE_MII,
0a5b2f6b CM	142	};
0a5b2f6b CM	143
0a381330	144	static struct platform_device realview_eth_device = {
c5142e84	145	.name = "smsc911x",
0a381330 CM	146	.id = 0,
	147	.num_resources = 2,
	148	};
	149
	150	int realview_eth_register(const char name, struct resource res)
	151	{
	152	if (name)
	153	realview_eth_device.name = name;
	154	realview_eth_device.resource = res;
c5142e84 SG	155	if (strcmp(realview_eth_device.name, "smsc911x") == 0)
c5142e84 SG	156	realview_eth_device.dev.platform_data = &smsc911x_config;
0a381330 CM	157
0a381330 CM	158	return platform_device_register(&realview_eth_device);
7db21712 CM	159	}
	160
	161	struct platform_device realview_usb_device = {
	162	.name = "isp1760",
	163	.num_resources = 2,
	164	};
	165
	166	int realview_usb_register(struct resource *res)
	167	{
	168	realview_usb_device.resource = res;
	169	return platform_device_register(&realview_usb_device);
0a381330 CM	170	}
0a381330 CM	171
6be62ba2 CM	172	static struct pata_platform_info pata_platform_data = {
	173	.ioport_shift = 1,
	174	};
	175
	176	static struct resource pata_resources[] = {
	177	[0] = {
	178	.start = REALVIEW_CF_BASE,
	179	.end = REALVIEW_CF_BASE + 0xff,
	180	.flags = IORESOURCE_MEM,
	181	},
	182	[1] = {
	183	.start = REALVIEW_CF_BASE + 0x100,
	184	.end = REALVIEW_CF_BASE + SZ_4K - 1,
	185	.flags = IORESOURCE_MEM,
	186	},
	187	};
	188
	189	struct platform_device realview_cf_device = {
	190	.name = "pata_platform",
	191	.id = -1,
	192	.num_resources = ARRAY_SIZE(pata_resources),
	193	.resource = pata_resources,
	194	.dev = {
	195	.platform_data = &pata_platform_data,
	196	},
	197	};
	198
6b65cd74 RK	199	static struct resource realview_i2c_resource = {
	200	.start = REALVIEW_I2C_BASE,
	201	.end = REALVIEW_I2C_BASE + SZ_4K - 1,
	202	.flags = IORESOURCE_MEM,
	203	};
	204
	205	struct platform_device realview_i2c_device = {
	206	.name = "versatile-i2c",
533ad5e6	207	.id = 0,
6b65cd74 RK	208	.num_resources = 1,
	209	.resource = &realview_i2c_resource,
	210	};
	211
533ad5e6 CM	212	static struct i2c_board_info realview_i2c_board_info[] = {
533ad5e6 CM	213	{
64e8be6e	214	I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6 CM	215	},
	216	};
	217
	218	static int __init realview_i2c_init(void)
	219	{
	220	return i2c_register_board_info(0, realview_i2c_board_info,
	221	ARRAY_SIZE(realview_i2c_board_info));
	222	}
	223	arch_initcall(realview_i2c_init);
	224
8ad68bbf CM	225	#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
8ad68bbf CM	226
98b0979f RK	227	/*
	228	* This is only used if GPIOLIB support is disabled
	229	*/
8ad68bbf CM	230	static unsigned int realview_mmc_status(struct device *dev)
	231	{
	232	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	233	u32 mask;
	234
	235	if (adev->res.start == REALVIEW_MMCI0_BASE)
	236	mask = 1;
	237	else
	238	mask = 2;
	239
b56ba8aa	240	return !(readl(REALVIEW_SYSMCI) & mask);
8ad68bbf CM	241	}
8ad68bbf CM	242
6ef297f8	243	struct mmci_platform_data realview_mmc0_plat_data = {
8ad68bbf CM	244	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
8ad68bbf CM	245	.status = realview_mmc_status,
98b0979f RK	246	.gpio_wp = 17,
98b0979f RK	247	.gpio_cd = 16,
8ad68bbf CM	248	};
8ad68bbf CM	249
6ef297f8	250	struct mmci_platform_data realview_mmc1_plat_data = {
8ad68bbf CM	251	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
8ad68bbf CM	252	.status = realview_mmc_status,
98b0979f RK	253	.gpio_wp = 19,
98b0979f RK	254	.gpio_cd = 18,
8ad68bbf CM	255	};
	256
	257	/*
	258	* Clock handling
	259	*/
39c0cb02	260	static const struct icst_params realview_oscvco_params = {
64fceb1d	261	.ref = 24000000,
4de2edbd	262	.vco_max = ICST307_VCO_MAX,
e73a46a3	263	.vco_min = ICST307_VCO_MIN,
8ad68bbf CM	264	.vd_min = 4 + 8,
	265	.vd_max = 511 + 8,
	266	.rd_min = 1 + 2,
	267	.rd_max = 127 + 2,
232eaf7f RK	268	.s2div = icst307_s2div,
232eaf7f RK	269	.idx2s = icst307_idx2s,
8ad68bbf CM	270	};
8ad68bbf CM	271
39c0cb02	272	static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
8ad68bbf CM	273	{
8ad68bbf CM	274	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
8ad68bbf CM	275	u32 val;
8ad68bbf CM	276
d1914c7e	277	val = readl(clk->vcoreg) & ~0x7ffff;
8ad68bbf CM	278	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	279
	280	writel(0xa05f, sys_lock);
d1914c7e	281	writel(val, clk->vcoreg);
8ad68bbf CM	282	writel(0, sys_lock);
	283	}
	284
9bf5b2ef RK	285	static const struct clk_ops oscvco_clk_ops = {
	286	.round = icst_clk_round,
	287	.set = icst_clk_set,
	288	.setvco = realview_oscvco_set,
	289	};
	290
cf30fb4a	291	static struct clk oscvco_clk = {
9bf5b2ef	292	.ops = &oscvco_clk_ops,
8ad68bbf	293	.params = &realview_oscvco_params,
8ad68bbf CM	294	};
8ad68bbf CM	295
cf30fb4a RK	296	/*
	297	* These are fixed clocks.
	298	*/
	299	static struct clk ref24_clk = {
	300	.rate = 24000000,
	301	};
	302
	303	static struct clk_lookup lookups[] = {
	304	{ /* UART0 */
4321532c	305	.dev_id = "dev:uart0",
cf30fb4a RK	306	.clk = &ref24_clk,
cf30fb4a RK	307	}, { /* UART1 */
4321532c	308	.dev_id = "dev:uart1",
cf30fb4a RK	309	.clk = &ref24_clk,
cf30fb4a RK	310	}, { /* UART2 */
4321532c	311	.dev_id = "dev:uart2",
cf30fb4a RK	312	.clk = &ref24_clk,
cf30fb4a RK	313	}, { /* UART3 */
4321532c	314	.dev_id = "fpga:uart3",
cf30fb4a RK	315	.clk = &ref24_clk,
cf30fb4a RK	316	}, { /* KMI0 */
4321532c	317	.dev_id = "fpga:kmi0",
cf30fb4a RK	318	.clk = &ref24_clk,
cf30fb4a RK	319	}, { /* KMI1 */
4321532c	320	.dev_id = "fpga:kmi1",
cf30fb4a RK	321	.clk = &ref24_clk,
cf30fb4a RK	322	}, { /* MMC0 */
4321532c	323	.dev_id = "fpga:mmc0",
cf30fb4a RK	324	.clk = &ref24_clk,
cf30fb4a RK	325	}, { /* EB:CLCD */
4321532c	326	.dev_id = "dev:clcd",
cf30fb4a RK	327	.clk = &oscvco_clk,
cf30fb4a RK	328	}, { /* PB:CLCD */
4321532c	329	.dev_id = "issp:clcd",
cf30fb4a RK	330	.clk = &oscvco_clk,
	331	}
	332	};
	333
	334	static int __init clk_init(void)
	335	{
d1914c7e RK	336	if (machine_is_realview_pb1176())
	337	oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	338	else
	339	oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
	340
0a0300dc	341	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
d1914c7e	342
cf30fb4a RK	343	return 0;
	344	}
	345	arch_initcall(clk_init);
	346
8ad68bbf CM	347	/*
	348	* CLCD support.
	349	*/
8ad68bbf CM	350	#define SYS_CLCD_NLCDIOON (1 << 2)
	351	#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
	352	#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
	353	#define SYS_CLCD_ID_MASK (0x1f << 8)
	354	#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
	355	#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
	356	#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
	357	#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
	358	#define SYS_CLCD_ID_VGA (0x1f << 8)
	359
	360	static struct clcd_panel vga = {
	361	.mode = {
	362	.name = "VGA",
	363	.refresh = 60,
	364	.xres = 640,
	365	.yres = 480,
	366	.pixclock = 39721,
	367	.left_margin = 40,
	368	.right_margin = 24,
	369	.upper_margin = 32,
	370	.lower_margin = 11,
	371	.hsync_len = 96,
	372	.vsync_len = 2,
	373	.sync = 0,
	374	.vmode = FB_VMODE_NONINTERLACED,
	375	},
	376	.width = -1,
	377	.height = -1,
	378	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	379	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	380	.bpp = 16,
	381	};
	382
c34a1025 CT	383	static struct clcd_panel xvga = {
	384	.mode = {
	385	.name = "XVGA",
	386	.refresh = 60,
	387	.xres = 1024,
	388	.yres = 768,
	389	.pixclock = 15748,
	390	.left_margin = 152,
	391	.right_margin = 48,
	392	.upper_margin = 23,
	393	.lower_margin = 3,
	394	.hsync_len = 104,
	395	.vsync_len = 4,
	396	.sync = 0,
	397	.vmode = FB_VMODE_NONINTERLACED,
	398	},
	399	.width = -1,
	400	.height = -1,
	401	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	402	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	403	.bpp = 16,
	404	};
	405
	406	static struct clcd_panel sanyo_3_8_in = {
	407	.mode = {
	408	.name = "Sanyo QVGA",
	409	.refresh = 116,
	410	.xres = 320,
	411	.yres = 240,
	412	.pixclock = 100000,
	413	.left_margin = 6,
	414	.right_margin = 6,
	415	.upper_margin = 5,
	416	.lower_margin = 5,
	417	.hsync_len = 6,
	418	.vsync_len = 6,
	419	.sync = 0,
	420	.vmode = FB_VMODE_NONINTERLACED,
	421	},
	422	.width = -1,
	423	.height = -1,
	424	.tim2 = TIM2_BCD,
4eccca20	425	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	426	.bpp = 16,
	427	};
	428
	429	static struct clcd_panel sanyo_2_5_in = {
	430	.mode = {
	431	.name = "Sanyo QVGA Portrait",
	432	.refresh = 116,
	433	.xres = 240,
	434	.yres = 320,
	435	.pixclock = 100000,
	436	.left_margin = 20,
	437	.right_margin = 10,
	438	.upper_margin = 2,
	439	.lower_margin = 2,
	440	.hsync_len = 10,
	441	.vsync_len = 2,
	442	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	443	.vmode = FB_VMODE_NONINTERLACED,
	444	},
	445	.width = -1,
	446	.height = -1,
	447	.tim2 = TIM2_IVS \| TIM2_IHS \| TIM2_IPC,
4eccca20	448	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	449	.bpp = 16,
	450	};
	451
	452	static struct clcd_panel epson_2_2_in = {
	453	.mode = {
	454	.name = "Epson QCIF",
	455	.refresh = 390,
	456	.xres = 176,
	457	.yres = 220,
	458	.pixclock = 62500,
	459	.left_margin = 3,
	460	.right_margin = 2,
	461	.upper_margin = 1,
	462	.lower_margin = 0,
	463	.hsync_len = 3,
	464	.vsync_len = 2,
	465	.sync = 0,
	466	.vmode = FB_VMODE_NONINTERLACED,
	467	},
	468	.width = -1,
	469	.height = -1,
	470	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	471	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	472	.bpp = 16,
	473	};
	474
	475	/*
	476	* Detect which LCD panel is connected, and return the appropriate
	477	* clcd_panel structure. Note: we do not have any information on
	478	* the required timings for the 8.4in panel, so we presently assume
	479	* VGA timings.
	480	*/
	481	static struct clcd_panel *realview_clcd_panel(void)
	482	{
	483	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
c34a1025 CT	484	struct clcd_panel *vga_panel;
c34a1025 CT	485	struct clcd_panel *panel;
8ad68bbf CM	486	u32 val;
8ad68bbf CM	487
c34a1025 CT	488	if (machine_is_realview_eb())
	489	vga_panel = &vga;
	490	else
	491	vga_panel = &xvga;
	492
8ad68bbf CM	493	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	494	if (val == SYS_CLCD_ID_SANYO_3_8)
	495	panel = &sanyo_3_8_in;
	496	else if (val == SYS_CLCD_ID_SANYO_2_5)
	497	panel = &sanyo_2_5_in;
	498	else if (val == SYS_CLCD_ID_EPSON_2_2)
	499	panel = &epson_2_2_in;
	500	else if (val == SYS_CLCD_ID_VGA)
c34a1025	501	panel = vga_panel;
8ad68bbf CM	502	else {
	503	printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
	504	val);
c34a1025	505	panel = vga_panel;
8ad68bbf CM	506	}
	507
	508	return panel;
	509	}
	510
	511	/*
	512	* Disable all display connectors on the interface module.
	513	*/
	514	static void realview_clcd_disable(struct clcd_fb *fb)
	515	{
	516	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	517	u32 val;
	518
	519	val = readl(sys_clcd);
	520	val &= ~SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	521	writel(val, sys_clcd);
	522	}
	523
	524	/*
	525	* Enable the relevant connector on the interface module.
	526	*/
	527	static void realview_clcd_enable(struct clcd_fb *fb)
	528	{
	529	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	530	u32 val;
	531
8ad68bbf	532	/*
9e7714d0	533	* Enable the PSUs
8ad68bbf	534	*/
9e7714d0	535	val = readl(sys_clcd);
8ad68bbf CM	536	val \|= SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	537	writel(val, sys_clcd);
	538	}
	539
8ad68bbf CM	540	static int realview_clcd_setup(struct clcd_fb *fb)
8ad68bbf CM	541	{
c34a1025	542	unsigned long framesize;
8ad68bbf CM	543	dma_addr_t dma;
8ad68bbf CM	544
c34a1025 CT	545	if (machine_is_realview_eb())
	546	/* VGA, 16bpp */
	547	framesize = 640 * 480 * 2;
	548	else
	549	/* XVGA, 16bpp */
	550	framesize = 1024 * 768 * 2;
	551
8ad68bbf CM	552	fb->panel = realview_clcd_panel();
	553
	554	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
c97c5aa8	555	&dma, GFP_KERNEL \| GFP_DMA);
8ad68bbf CM	556	if (!fb->fb.screen_base) {
	557	printk(KERN_ERR "CLCD: unable to map framebuffer\n");
	558	return -ENOMEM;
	559	}
	560
	561	fb->fb.fix.smem_start = dma;
	562	fb->fb.fix.smem_len = framesize;
	563
	564	return 0;
	565	}
	566
	567	static int realview_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	568	{
	569	return dma_mmap_writecombine(&fb->dev->dev, vma,
	570	fb->fb.screen_base,
	571	fb->fb.fix.smem_start,
	572	fb->fb.fix.smem_len);
	573	}
	574
	575	static void realview_clcd_remove(struct clcd_fb *fb)
	576	{
	577	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
	578	fb->fb.screen_base, fb->fb.fix.smem_start);
	579	}
	580
	581	struct clcd_board clcd_plat_data = {
	582	.name = "RealView",
	583	.check = clcdfb_check,
	584	.decode = clcdfb_decode,
	585	.disable = realview_clcd_disable,
	586	.enable = realview_clcd_enable,
	587	.setup = realview_clcd_setup,
	588	.mmap = realview_clcd_mmap,
	589	.remove = realview_clcd_remove,
	590	};
	591
	592	#ifdef CONFIG_LEDS
	593	#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
	594
	595	void realview_leds_event(led_event_t ledevt)
	596	{
	597	unsigned long flags;
	598	u32 val;
da055eb5	599	u32 led = 1 << smp_processor_id();
8ad68bbf CM	600
	601	local_irq_save(flags);
	602	val = readl(VA_LEDS_BASE);
	603
	604	switch (ledevt) {
	605	case led_idle_start:
da055eb5	606	val = val & ~led;
8ad68bbf CM	607	break;
	608
	609	case led_idle_end:
da055eb5	610	val = val \| led;
8ad68bbf CM	611	break;
	612
	613	case led_timer:
da055eb5	614	val = val ^ REALVIEW_SYS_LED7;
8ad68bbf CM	615	break;
	616
	617	case led_halted:
	618	val = 0;
	619	break;
	620
	621	default:
	622	break;
	623	}
	624
	625	writel(val, VA_LEDS_BASE);
	626	local_irq_restore(flags);
	627	}
	628	#endif /* CONFIG_LEDS */
	629
	630	/*
	631	* Where is the timer (VA)?
	632	*/
80192735 CM	633	void __iomem *timer0_va_base;
	634	void __iomem *timer1_va_base;
	635	void __iomem *timer2_va_base;
	636	void __iomem *timer3_va_base;
8ad68bbf	637
8ad68bbf	638	/*
a8655e83	639	* Set up the clock source and clock events devices
8ad68bbf	640	*/
8cc4c548	641	void __init realview_timer_init(unsigned int timer_irq)
8ad68bbf CM	642	{
	643	u32 val;
	644
	645	/*
	646	* set clock frequency:
	647	* REALVIEW_REFCLK is 32KHz
	648	* REALVIEW_TIMCLK is 1MHz
	649	*/
	650	val = readl(__io_address(REALVIEW_SCTL_BASE));
	651	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) \|
	652	(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) \|
	653	(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) \|
	654	(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) \| val,
	655	__io_address(REALVIEW_SCTL_BASE));
	656
	657	/*
	658	* Initialise to a known state (all timers off)
	659	*/
80192735 CM	660	writel(0, timer0_va_base + TIMER_CTRL);
	661	writel(0, timer1_va_base + TIMER_CTRL);
	662	writel(0, timer2_va_base + TIMER_CTRL);
	663	writel(0, timer3_va_base + TIMER_CTRL);
8ad68bbf	664
e3887714 RK	665	sp804_clocksource_init(timer3_va_base);
e3887714 RK	666	sp804_clockevents_init(timer0_va_base, timer_irq);
8ad68bbf	667	}
5b39d154 CM	668
	669	/*
	670	* Setup the memory banks.
	671	*/
	672	void realview_fixup(struct machine_desc mdesc, struct tag tags, char **from,
	673	struct meminfo *meminfo)
	674	{
	675	/*
	676	* Most RealView platforms have 512MB contiguous RAM at 0x70000000.
	677	* Half of this is mirrored at 0.
	678	*/
	679	#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
	680	meminfo->bank[0].start = 0x70000000;
	681	meminfo->bank[0].size = SZ_512M;
	682	meminfo->nr_banks = 1;
	683	#else
	684	meminfo->bank[0].start = 0;
	685	meminfo->bank[0].size = SZ_256M;
	686	meminfo->nr_banks = 1;
	687	#endif
	688	}