[deliverable/linux.git] / arch / arm / mach-realview / core.c

/*
 *  linux/arch/arm/mach-realview/core.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/io.h>
#include <linux/smsc911x.h>
#include <linux/ata_platform.h>
#include <linux/amba/mmci.h>
#include <linux/gfp.h>

#include <asm/clkdev.h>
#include <asm/system.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>

#include <asm/hardware/gic.h>

#include <mach/clkdev.h>
#include <mach/platform.h>
#include <mach/irqs.h>
#include <plat/timer-sp.h>

#include "core.h"

/* used by entry-macro.S and platsmp.c */
void __iomem *gic_cpu_base_addr;

#ifdef CONFIG_ZONE_DMA
/*
 * Adjust the zones if there are restrictions for DMA access.
 */
void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
{
	unsigned long dma_size = SZ_256M >> PAGE_SHIFT;

	if (!machine_is_realview_pbx() || size[0] <= dma_size)
		return;

	size[ZONE_NORMAL] = size[0] - dma_size;
	size[ZONE_DMA] = dma_size;
	hole[ZONE_NORMAL] = hole[0];
	hole[ZONE_DMA] = 0;
}
#endif


#define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)

static int realview_flash_init(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);

	return 0;
}

static void realview_flash_exit(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static void realview_flash_set_vpp(int on)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	if (on)
		val |= REALVIEW_FLASHPROG_FLVPPEN;
	else
		val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static struct flash_platform_data realview_flash_data = {
	.map_name		= "cfi_probe",
	.width			= 4,
	.init			= realview_flash_init,
	.exit			= realview_flash_exit,
	.set_vpp		= realview_flash_set_vpp,
};

struct platform_device realview_flash_device = {
	.name			= "armflash",
	.id			= 0,
	.dev			= {
		.platform_data	= &realview_flash_data,
	},
};

int realview_flash_register(struct resource *res, u32 num)
{
	realview_flash_device.resource = res;
	realview_flash_device.num_resources = num;
	return platform_device_register(&realview_flash_device);
}

static struct smsc911x_platform_config smsc911x_config = {
	.flags		= SMSC911X_USE_32BIT,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct platform_device realview_eth_device = {
	.name		= "smsc911x",
	.id		= 0,
	.num_resources	= 2,
};

int realview_eth_register(const char *name, struct resource *res)
{
	if (name)
		realview_eth_device.name = name;
	realview_eth_device.resource = res;
	if (strcmp(realview_eth_device.name, "smsc911x") == 0)
		realview_eth_device.dev.platform_data = &smsc911x_config;

	return platform_device_register(&realview_eth_device);
}

struct platform_device realview_usb_device = {
	.name			= "isp1760",
	.num_resources		= 2,
};

int realview_usb_register(struct resource *res)
{
	realview_usb_device.resource = res;
	return platform_device_register(&realview_usb_device);
}

static struct pata_platform_info pata_platform_data = {
	.ioport_shift		= 1,
};

static struct resource pata_resources[] = {
	[0] = {
		.start		= REALVIEW_CF_BASE,
		.end		= REALVIEW_CF_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= REALVIEW_CF_BASE + 0x100,
		.end		= REALVIEW_CF_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

struct platform_device realview_cf_device = {
	.name			= "pata_platform",
	.id			= -1,
	.num_resources		= ARRAY_SIZE(pata_resources),
	.resource		= pata_resources,
	.dev			= {
		.platform_data	= &pata_platform_data,
	},
};

static struct resource realview_i2c_resource = {
	.start		= REALVIEW_I2C_BASE,
	.end		= REALVIEW_I2C_BASE + SZ_4K - 1,
	.flags		= IORESOURCE_MEM,
};

struct platform_device realview_i2c_device = {
	.name		= "versatile-i2c",
	.id		= 0,
	.num_resources	= 1,
	.resource	= &realview_i2c_resource,
};

static struct i2c_board_info realview_i2c_board_info[] = {
	{
		I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
	},
};

static int __init realview_i2c_init(void)
{
	return i2c_register_board_info(0, realview_i2c_board_info,
				       ARRAY_SIZE(realview_i2c_board_info));
}
arch_initcall(realview_i2c_init);

#define REALVIEW_SYSMCI	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)

/*
 * This is only used if GPIOLIB support is disabled
 */
static unsigned int realview_mmc_status(struct device *dev)
{
	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	u32 mask;

	if (machine_is_realview_pb1176()) {
		static bool inserted = false;

		/*
		 * The PB1176 does not have the status register,
		 * assume it is inserted at startup, then invert
		 * for each call so card insertion/removal will
		 * be detected anyway. This will not be called if
		 * GPIO on PL061 is active, which is the proper
		 * way to do this on the PB1176.
		 */
		inserted = !inserted;
		return inserted ? 0 : 1;
	}

	if (adev->res.start == REALVIEW_MMCI0_BASE)
		mask = 1;
	else
		mask = 2;

	return readl(REALVIEW_SYSMCI) & mask;
}

struct mmci_platform_data realview_mmc0_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
	.gpio_wp	= 17,
	.gpio_cd	= 16,
	.cd_invert	= true,
};

struct mmci_platform_data realview_mmc1_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
	.gpio_wp	= 19,
	.gpio_cd	= 18,
	.cd_invert	= true,
};

/*
 * Clock handling
 */
static const struct icst_params realview_oscvco_params = {
	.ref		= 24000000,
	.vco_max	= ICST307_VCO_MAX,
	.vco_min	= ICST307_VCO_MIN,
	.vd_min		= 4 + 8,
	.vd_max		= 511 + 8,
	.rd_min		= 1 + 2,
	.rd_max		= 127 + 2,
	.s2div		= icst307_s2div,
	.idx2s		= icst307_idx2s,
};

static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
{
	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
	u32 val;

	val = readl(clk->vcoreg) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, sys_lock);
	writel(val, clk->vcoreg);
	writel(0, sys_lock);
}

static const struct clk_ops oscvco_clk_ops = {
	.round	= icst_clk_round,
	.set	= icst_clk_set,
	.setvco	= realview_oscvco_set,
};

static struct clk oscvco_clk = {
	.ops	= &oscvco_clk_ops,
	.params	= &realview_oscvco_params,
};

/*
 * These are fixed clocks.
 */
static struct clk ref24_clk = {
	.rate	= 24000000,
};

static struct clk dummy_apb_pclk;

static struct clk_lookup lookups[] = {
	{	/* Bus clock */
		.con_id		= "apb_pclk",
		.clk		= &dummy_apb_pclk,
	}, {	/* UART0 */
		.dev_id		= "dev:uart0",
		.clk		= &ref24_clk,
	}, {	/* UART1 */
		.dev_id		= "dev:uart1",
		.clk		= &ref24_clk,
	}, {	/* UART2 */
		.dev_id		= "dev:uart2",
		.clk		= &ref24_clk,
	}, {	/* UART3 */
		.dev_id		= "fpga:uart3",
		.clk		= &ref24_clk,
	}, {	/* UART3 is on the dev chip in PB1176 */
		.dev_id		= "dev:uart3",
		.clk		= &ref24_clk,
	}, {	/* UART4 only exists in PB1176 */
		.dev_id		= "fpga:uart4",
		.clk		= &ref24_clk,
	}, {	/* KMI0 */
		.dev_id		= "fpga:kmi0",
		.clk		= &ref24_clk,
	}, {	/* KMI1 */
		.dev_id		= "fpga:kmi1",
		.clk		= &ref24_clk,
	}, {	/* MMC0 */
		.dev_id		= "fpga:mmc0",
		.clk		= &ref24_clk,
	}, {	/* CLCD is in the PB1176 and EB DevChip */
		.dev_id		= "dev:clcd",
		.clk		= &oscvco_clk,
	}, {	/* PB:CLCD */
		.dev_id		= "issp:clcd",
		.clk		= &oscvco_clk,
	}, {	/* SSP */
		.dev_id		= "dev:ssp0",
		.clk		= &ref24_clk,
	}
};

static int __init clk_init(void)
{
	if (machine_is_realview_pb1176())
		oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	else
		oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	return 0;
}
core_initcall(clk_init);

/*
 * CLCD support.
 */
#define SYS_CLCD_NLCDIOON	(1 << 2)
#define SYS_CLCD_VDDPOSSWITCH	(1 << 3)
#define SYS_CLCD_PWR3V5SWITCH	(1 << 4)
#define SYS_CLCD_ID_MASK	(0x1f << 8)
#define SYS_CLCD_ID_SANYO_3_8	(0x00 << 8)
#define SYS_CLCD_ID_UNKNOWN_8_4	(0x01 << 8)
#define SYS_CLCD_ID_EPSON_2_2	(0x02 << 8)
#define SYS_CLCD_ID_SANYO_2_5	(0x07 << 8)
#define SYS_CLCD_ID_VGA		(0x1f << 8)

static struct clcd_panel vga = {
	.mode		= {
		.name		= "VGA",
		.refresh	= 60,
		.xres		= 640,
		.yres		= 480,
		.pixclock	= 39721,
		.left_margin	= 40,
		.right_margin	= 24,
		.upper_margin	= 32,
		.lower_margin	= 11,
		.hsync_len	= 96,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel xvga = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15748,
		.left_margin	= 152,
		.right_margin	= 48,
		.upper_margin	= 23,
		.lower_margin	= 3,
		.hsync_len	= 104,
		.vsync_len	= 4,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_3_8_in = {
	.mode		= {
		.name		= "Sanyo QVGA",
		.refresh	= 116,
		.xres		= 320,
		.yres		= 240,
		.pixclock	= 100000,
		.left_margin	= 6,
		.right_margin	= 6,
		.upper_margin	= 5,
		.lower_margin	= 5,
		.hsync_len	= 6,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_2_5_in = {
	.mode		= {
		.name		= "Sanyo QVGA Portrait",
		.refresh	= 116,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 100000,
		.left_margin	= 20,
		.right_margin	= 10,
		.upper_margin	= 2,
		.lower_margin	= 2,
		.hsync_len	= 10,
		.vsync_len	= 2,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_IVS | TIM2_IHS | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel epson_2_2_in = {
	.mode		= {
		.name		= "Epson QCIF",
		.refresh	= 390,
		.xres		= 176,
		.yres		= 220,
		.pixclock	= 62500,
		.left_margin	= 3,
		.right_margin	= 2,
		.upper_margin	= 1,
		.lower_margin	= 0,
		.hsync_len	= 3,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

/*
 * Detect which LCD panel is connected, and return the appropriate
 * clcd_panel structure.  Note: we do not have any information on
 * the required timings for the 8.4in panel, so we presently assume
 * VGA timings.
 */
static struct clcd_panel *realview_clcd_panel(void)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	struct clcd_panel *vga_panel;
	struct clcd_panel *panel;
	u32 val;

	if (machine_is_realview_eb())
		vga_panel = &vga;
	else
		vga_panel = &xvga;

	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	if (val == SYS_CLCD_ID_SANYO_3_8)
		panel = &sanyo_3_8_in;
	else if (val == SYS_CLCD_ID_SANYO_2_5)
		panel = &sanyo_2_5_in;
	else if (val == SYS_CLCD_ID_EPSON_2_2)
		panel = &epson_2_2_in;
	else if (val == SYS_CLCD_ID_VGA)
		panel = vga_panel;
	else {
		printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
			val);
		panel = vga_panel;
	}

	return panel;
}

/*
 * Disable all display connectors on the interface module.
 */
static void realview_clcd_disable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	val = readl(sys_clcd);
	val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

/*
 * Enable the relevant connector on the interface module.
 */
static void realview_clcd_enable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	/*
	 * Enable the PSUs
	 */
	val = readl(sys_clcd);
	val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

static int realview_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize;
	dma_addr_t dma;

	if (machine_is_realview_eb())
		/* VGA, 16bpp */
		framesize = 640 * 480 * 2;
	else
		/* XVGA, 16bpp */
		framesize = 1024 * 768 * 2;

	fb->panel		= realview_clcd_panel();

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
						    &dma, GFP_KERNEL | GFP_DMA);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
		return -ENOMEM;
	}

	fb->fb.fix.smem_start	= dma;
	fb->fb.fix.smem_len	= framesize;

	return 0;
}

static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma,
				     fb->fb.screen_base,
				     fb->fb.fix.smem_start,
				     fb->fb.fix.smem_len);
}

static void realview_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
			      fb->fb.screen_base, fb->fb.fix.smem_start);
}

struct clcd_board clcd_plat_data = {
	.name		= "RealView",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.disable	= realview_clcd_disable,
	.enable		= realview_clcd_enable,
	.setup		= realview_clcd_setup,
	.mmap		= realview_clcd_mmap,
	.remove		= realview_clcd_remove,
};

#ifdef CONFIG_LEDS
#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)

void realview_leds_event(led_event_t ledevt)
{
	unsigned long flags;
	u32 val;
	u32 led = 1 << smp_processor_id();

	local_irq_save(flags);
	val = readl(VA_LEDS_BASE);

	switch (ledevt) {
	case led_idle_start:
		val = val & ~led;
		break;

	case led_idle_end:
		val = val | led;
		break;

	case led_timer:
		val = val ^ REALVIEW_SYS_LED7;
		break;

	case led_halted:
		val = 0;
		break;

	default:
		break;
	}

	writel(val, VA_LEDS_BASE);
	local_irq_restore(flags);
}
#endif	/* CONFIG_LEDS */

/*
 * Where is the timer (VA)?
 */
void __iomem *timer0_va_base;
void __iomem *timer1_va_base;
void __iomem *timer2_va_base;
void __iomem *timer3_va_base;

/*
 * Set up the clock source and clock events devices
 */
void __init realview_timer_init(unsigned int timer_irq)
{
	u32 val;

	/* 
	 * set clock frequency: 
	 *	REALVIEW_REFCLK is 32KHz
	 *	REALVIEW_TIMCLK is 1MHz
	 */
	val = readl(__io_address(REALVIEW_SCTL_BASE));
	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | 
	       (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
	       __io_address(REALVIEW_SCTL_BASE));

	/*
	 * Initialise to a known state (all timers off)
	 */
	writel(0, timer0_va_base + TIMER_CTRL);
	writel(0, timer1_va_base + TIMER_CTRL);
	writel(0, timer2_va_base + TIMER_CTRL);
	writel(0, timer3_va_base + TIMER_CTRL);

	sp804_clocksource_init(timer3_va_base);
	sp804_clockevents_init(timer0_va_base, timer_irq);
}

/*
 * Setup the memory banks.
 */
void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
		    struct meminfo *meminfo)
{
	/*
	 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
	 * Half of this is mirrored at 0.
	 */
#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
	meminfo->bank[0].start = 0x70000000;
	meminfo->bank[0].size = SZ_512M;
	meminfo->nr_banks = 1;
#else
	meminfo->bank[0].start = 0;
	meminfo->bank[0].size = SZ_256M;
	meminfo->nr_banks = 1;
#endif
}
Commit	Line	Data
8ad68bbf CM	1	/*
	2	* linux/arch/arm/mach-realview/core.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
8ad68bbf	21	#include <linux/init.h>
1be7228d	22	#include <linux/platform_device.h>
8ad68bbf CM	23	#include <linux/dma-mapping.h>
	24	#include <linux/sysdev.h>
	25	#include <linux/interrupt.h>
a62c80e5 RK	26	#include <linux/amba/bus.h>
a62c80e5 RK	27	#include <linux/amba/clcd.h>
fced80c7	28	#include <linux/io.h>
c5142e84	29	#include <linux/smsc911x.h>
6be62ba2	30	#include <linux/ata_platform.h>
6ef297f8	31	#include <linux/amba/mmci.h>
5a0e3ad6	32	#include <linux/gfp.h>
8ad68bbf	33
cf30fb4a	34	#include <asm/clkdev.h>
8ad68bbf	35	#include <asm/system.h>
a09e64fb	36	#include <mach/hardware.h>
8ad68bbf CM	37	#include <asm/irq.h>
8ad68bbf CM	38	#include <asm/leds.h>
68c3d935	39	#include <asm/mach-types.h>
8ad68bbf	40	#include <asm/hardware/arm_timer.h>
c5a0adb5	41	#include <asm/hardware/icst.h>
8ad68bbf CM	42
	43	#include <asm/mach/arch.h>
	44	#include <asm/mach/flash.h>
	45	#include <asm/mach/irq.h>
8ad68bbf	46	#include <asm/mach/map.h>
8ad68bbf CM	47
	48	#include <asm/hardware/gic.h>
	49
f4b8b319	50	#include <mach/clkdev.h>
ee8c9571 CM	51	#include <mach/platform.h>
ee8c9571 CM	52	#include <mach/irqs.h>
e3887714	53	#include <plat/timer-sp.h>
ee8c9571	54
8ad68bbf	55	#include "core.h"
8ad68bbf	56
1bbdf637	57	/* used by entry-macro.S and platsmp.c */
c4057f52 CM	58	void __iomem *gic_cpu_base_addr;
c4057f52 CM	59
c97c5aa8 CM	60	#ifdef CONFIG_ZONE_DMA
	61	/*
	62	* Adjust the zones if there are restrictions for DMA access.
	63	*/
b65b4781	64	void __init realview_adjust_zones(unsigned long size, unsigned long hole)
c97c5aa8 CM	65	{
	66	unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
	67
b65b4781	68	if (!machine_is_realview_pbx() \|\| size[0] <= dma_size)
c97c5aa8 CM	69	return;
	70
	71	size[ZONE_NORMAL] = size[0] - dma_size;
	72	size[ZONE_DMA] = dma_size;
	73	hole[ZONE_NORMAL] = hole[0];
	74	hole[ZONE_DMA] = 0;
	75	}
	76	#endif
	77
8ad68bbf CM	78
	79	#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
	80
	81	static int realview_flash_init(void)
	82	{
	83	u32 val;
	84
	85	val = __raw_readl(REALVIEW_FLASHCTRL);
	86	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	87	__raw_writel(val, REALVIEW_FLASHCTRL);
	88
	89	return 0;
	90	}
	91
	92	static void realview_flash_exit(void)
	93	{
	94	u32 val;
	95
	96	val = __raw_readl(REALVIEW_FLASHCTRL);
	97	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	98	__raw_writel(val, REALVIEW_FLASHCTRL);
	99	}
	100
	101	static void realview_flash_set_vpp(int on)
	102	{
	103	u32 val;
	104
	105	val = __raw_readl(REALVIEW_FLASHCTRL);
	106	if (on)
	107	val \|= REALVIEW_FLASHPROG_FLVPPEN;
	108	else
	109	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	110	__raw_writel(val, REALVIEW_FLASHCTRL);
	111	}
	112
	113	static struct flash_platform_data realview_flash_data = {
	114	.map_name = "cfi_probe",
	115	.width = 4,
	116	.init = realview_flash_init,
	117	.exit = realview_flash_exit,
	118	.set_vpp = realview_flash_set_vpp,
	119	};
	120
8ad68bbf CM	121	struct platform_device realview_flash_device = {
	122	.name = "armflash",
	123	.id = 0,
	124	.dev = {
	125	.platform_data = &realview_flash_data,
	126	},
8ad68bbf CM	127	};
8ad68bbf CM	128
a44ddfd5 CM	129	int realview_flash_register(struct resource *res, u32 num)
	130	{
	131	realview_flash_device.resource = res;
	132	realview_flash_device.num_resources = num;
	133	return platform_device_register(&realview_flash_device);
	134	}
	135
c5142e84 SG	136	static struct smsc911x_platform_config smsc911x_config = {
	137	.flags = SMSC911X_USE_32BIT,
	138	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	139	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	140	.phy_interface = PHY_INTERFACE_MODE_MII,
0a5b2f6b CM	141	};
0a5b2f6b CM	142
0a381330	143	static struct platform_device realview_eth_device = {
c5142e84	144	.name = "smsc911x",
0a381330 CM	145	.id = 0,
	146	.num_resources = 2,
	147	};
	148
	149	int realview_eth_register(const char name, struct resource res)
	150	{
	151	if (name)
	152	realview_eth_device.name = name;
	153	realview_eth_device.resource = res;
c5142e84 SG	154	if (strcmp(realview_eth_device.name, "smsc911x") == 0)
c5142e84 SG	155	realview_eth_device.dev.platform_data = &smsc911x_config;
0a381330 CM	156
0a381330 CM	157	return platform_device_register(&realview_eth_device);
7db21712 CM	158	}
	159
	160	struct platform_device realview_usb_device = {
	161	.name = "isp1760",
	162	.num_resources = 2,
	163	};
	164
	165	int realview_usb_register(struct resource *res)
	166	{
	167	realview_usb_device.resource = res;
	168	return platform_device_register(&realview_usb_device);
0a381330 CM	169	}
0a381330 CM	170
6be62ba2 CM	171	static struct pata_platform_info pata_platform_data = {
	172	.ioport_shift = 1,
	173	};
	174
	175	static struct resource pata_resources[] = {
	176	[0] = {
	177	.start = REALVIEW_CF_BASE,
	178	.end = REALVIEW_CF_BASE + 0xff,
	179	.flags = IORESOURCE_MEM,
	180	},
	181	[1] = {
	182	.start = REALVIEW_CF_BASE + 0x100,
	183	.end = REALVIEW_CF_BASE + SZ_4K - 1,
	184	.flags = IORESOURCE_MEM,
	185	},
	186	};
	187
	188	struct platform_device realview_cf_device = {
	189	.name = "pata_platform",
	190	.id = -1,
	191	.num_resources = ARRAY_SIZE(pata_resources),
	192	.resource = pata_resources,
	193	.dev = {
	194	.platform_data = &pata_platform_data,
	195	},
	196	};
	197
6b65cd74 RK	198	static struct resource realview_i2c_resource = {
	199	.start = REALVIEW_I2C_BASE,
	200	.end = REALVIEW_I2C_BASE + SZ_4K - 1,
	201	.flags = IORESOURCE_MEM,
	202	};
	203
	204	struct platform_device realview_i2c_device = {
	205	.name = "versatile-i2c",
533ad5e6	206	.id = 0,
6b65cd74 RK	207	.num_resources = 1,
	208	.resource = &realview_i2c_resource,
	209	};
	210
533ad5e6 CM	211	static struct i2c_board_info realview_i2c_board_info[] = {
533ad5e6 CM	212	{
64e8be6e	213	I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6 CM	214	},
	215	};
	216
	217	static int __init realview_i2c_init(void)
	218	{
	219	return i2c_register_board_info(0, realview_i2c_board_info,
	220	ARRAY_SIZE(realview_i2c_board_info));
	221	}
	222	arch_initcall(realview_i2c_init);
	223
8ad68bbf CM	224	#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
8ad68bbf CM	225
98b0979f RK	226	/*
	227	* This is only used if GPIOLIB support is disabled
	228	*/
8ad68bbf CM	229	static unsigned int realview_mmc_status(struct device *dev)
	230	{
	231	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	232	u32 mask;
	233
48f1d5a3 LW	234	if (machine_is_realview_pb1176()) {
	235	static bool inserted = false;
	236
	237	/*
	238	* The PB1176 does not have the status register,
	239	* assume it is inserted at startup, then invert
	240	* for each call so card insertion/removal will
	241	* be detected anyway. This will not be called if
	242	* GPIO on PL061 is active, which is the proper
	243	* way to do this on the PB1176.
	244	*/
	245	inserted = !inserted;
	246	return inserted ? 0 : 1;
	247	}
	248
8ad68bbf CM	249	if (adev->res.start == REALVIEW_MMCI0_BASE)
	250	mask = 1;
	251	else
	252	mask = 2;
	253
74bc8093	254	return readl(REALVIEW_SYSMCI) & mask;
8ad68bbf CM	255	}
8ad68bbf CM	256
6ef297f8	257	struct mmci_platform_data realview_mmc0_plat_data = {
8ad68bbf CM	258	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
8ad68bbf CM	259	.status = realview_mmc_status,
98b0979f RK	260	.gpio_wp = 17,
98b0979f RK	261	.gpio_cd = 16,
29719445	262	.cd_invert = true,
8ad68bbf CM	263	};
8ad68bbf CM	264
6ef297f8	265	struct mmci_platform_data realview_mmc1_plat_data = {
8ad68bbf CM	266	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
8ad68bbf CM	267	.status = realview_mmc_status,
98b0979f RK	268	.gpio_wp = 19,
98b0979f RK	269	.gpio_cd = 18,
29719445	270	.cd_invert = true,
8ad68bbf CM	271	};
	272
	273	/*
	274	* Clock handling
	275	*/
39c0cb02	276	static const struct icst_params realview_oscvco_params = {
64fceb1d	277	.ref = 24000000,
4de2edbd	278	.vco_max = ICST307_VCO_MAX,
e73a46a3	279	.vco_min = ICST307_VCO_MIN,
8ad68bbf CM	280	.vd_min = 4 + 8,
	281	.vd_max = 511 + 8,
	282	.rd_min = 1 + 2,
	283	.rd_max = 127 + 2,
232eaf7f RK	284	.s2div = icst307_s2div,
232eaf7f RK	285	.idx2s = icst307_idx2s,
8ad68bbf CM	286	};
8ad68bbf CM	287
39c0cb02	288	static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
8ad68bbf CM	289	{
8ad68bbf CM	290	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
8ad68bbf CM	291	u32 val;
8ad68bbf CM	292
d1914c7e	293	val = readl(clk->vcoreg) & ~0x7ffff;
8ad68bbf CM	294	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	295
	296	writel(0xa05f, sys_lock);
d1914c7e	297	writel(val, clk->vcoreg);
8ad68bbf CM	298	writel(0, sys_lock);
	299	}
	300
9bf5b2ef RK	301	static const struct clk_ops oscvco_clk_ops = {
	302	.round = icst_clk_round,
	303	.set = icst_clk_set,
	304	.setvco = realview_oscvco_set,
	305	};
	306
cf30fb4a	307	static struct clk oscvco_clk = {
9bf5b2ef	308	.ops = &oscvco_clk_ops,
8ad68bbf	309	.params = &realview_oscvco_params,
8ad68bbf CM	310	};
8ad68bbf CM	311
cf30fb4a RK	312	/*
	313	* These are fixed clocks.
	314	*/
	315	static struct clk ref24_clk = {
	316	.rate = 24000000,
	317	};
	318
3126c7bc RK	319	static struct clk dummy_apb_pclk;
3126c7bc RK	320
cf30fb4a	321	static struct clk_lookup lookups[] = {
3126c7bc RK	322	{ /* Bus clock */
	323	.con_id = "apb_pclk",
	324	.clk = &dummy_apb_pclk,
	325	}, { /* UART0 */
4321532c	326	.dev_id = "dev:uart0",
cf30fb4a RK	327	.clk = &ref24_clk,
cf30fb4a RK	328	}, { /* UART1 */
4321532c	329	.dev_id = "dev:uart1",
cf30fb4a RK	330	.clk = &ref24_clk,
cf30fb4a RK	331	}, { /* UART2 */
4321532c	332	.dev_id = "dev:uart2",
cf30fb4a RK	333	.clk = &ref24_clk,
cf30fb4a RK	334	}, { /* UART3 */
4321532c	335	.dev_id = "fpga:uart3",
cf30fb4a	336	.clk = &ref24_clk,
48f1d5a3 LW	337	}, { /* UART3 is on the dev chip in PB1176 */
	338	.dev_id = "dev:uart3",
	339	.clk = &ref24_clk,
	340	}, { /* UART4 only exists in PB1176 */
	341	.dev_id = "fpga:uart4",
	342	.clk = &ref24_clk,
cf30fb4a	343	}, { /* KMI0 */
4321532c	344	.dev_id = "fpga:kmi0",
cf30fb4a RK	345	.clk = &ref24_clk,
cf30fb4a RK	346	}, { /* KMI1 */
4321532c	347	.dev_id = "fpga:kmi1",
cf30fb4a RK	348	.clk = &ref24_clk,
cf30fb4a RK	349	}, { /* MMC0 */
4321532c	350	.dev_id = "fpga:mmc0",
cf30fb4a	351	.clk = &ref24_clk,
48f1d5a3	352	}, { /* CLCD is in the PB1176 and EB DevChip */
4321532c	353	.dev_id = "dev:clcd",
cf30fb4a RK	354	.clk = &oscvco_clk,
cf30fb4a RK	355	}, { /* PB:CLCD */
4321532c	356	.dev_id = "issp:clcd",
cf30fb4a	357	.clk = &oscvco_clk,
d6ada860 LW	358	}, { /* SSP */
	359	.dev_id = "dev:ssp0",
	360	.clk = &ref24_clk,
cf30fb4a RK	361	}
	362	};
	363
	364	static int __init clk_init(void)
	365	{
d1914c7e RK	366	if (machine_is_realview_pb1176())
	367	oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	368	else
	369	oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
	370
0a0300dc	371	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
d1914c7e	372
cf30fb4a RK	373	return 0;
cf30fb4a RK	374	}
06385e49	375	core_initcall(clk_init);
cf30fb4a	376
8ad68bbf CM	377	/*
	378	* CLCD support.
	379	*/
8ad68bbf CM	380	#define SYS_CLCD_NLCDIOON (1 << 2)
	381	#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
	382	#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
	383	#define SYS_CLCD_ID_MASK (0x1f << 8)
	384	#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
	385	#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
	386	#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
	387	#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
	388	#define SYS_CLCD_ID_VGA (0x1f << 8)
	389
	390	static struct clcd_panel vga = {
	391	.mode = {
	392	.name = "VGA",
	393	.refresh = 60,
	394	.xres = 640,
	395	.yres = 480,
	396	.pixclock = 39721,
	397	.left_margin = 40,
	398	.right_margin = 24,
	399	.upper_margin = 32,
	400	.lower_margin = 11,
	401	.hsync_len = 96,
	402	.vsync_len = 2,
	403	.sync = 0,
	404	.vmode = FB_VMODE_NONINTERLACED,
	405	},
	406	.width = -1,
	407	.height = -1,
	408	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	409	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	410	.bpp = 16,
	411	};
	412
c34a1025 CT	413	static struct clcd_panel xvga = {
	414	.mode = {
	415	.name = "XVGA",
	416	.refresh = 60,
	417	.xres = 1024,
	418	.yres = 768,
	419	.pixclock = 15748,
	420	.left_margin = 152,
	421	.right_margin = 48,
	422	.upper_margin = 23,
	423	.lower_margin = 3,
	424	.hsync_len = 104,
	425	.vsync_len = 4,
	426	.sync = 0,
	427	.vmode = FB_VMODE_NONINTERLACED,
	428	},
	429	.width = -1,
	430	.height = -1,
	431	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	432	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	433	.bpp = 16,
	434	};
	435
	436	static struct clcd_panel sanyo_3_8_in = {
	437	.mode = {
	438	.name = "Sanyo QVGA",
	439	.refresh = 116,
	440	.xres = 320,
	441	.yres = 240,
	442	.pixclock = 100000,
	443	.left_margin = 6,
	444	.right_margin = 6,
	445	.upper_margin = 5,
	446	.lower_margin = 5,
	447	.hsync_len = 6,
	448	.vsync_len = 6,
	449	.sync = 0,
	450	.vmode = FB_VMODE_NONINTERLACED,
	451	},
	452	.width = -1,
	453	.height = -1,
	454	.tim2 = TIM2_BCD,
4eccca20	455	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	456	.bpp = 16,
	457	};
	458
	459	static struct clcd_panel sanyo_2_5_in = {
	460	.mode = {
	461	.name = "Sanyo QVGA Portrait",
	462	.refresh = 116,
	463	.xres = 240,
	464	.yres = 320,
	465	.pixclock = 100000,
	466	.left_margin = 20,
	467	.right_margin = 10,
	468	.upper_margin = 2,
	469	.lower_margin = 2,
	470	.hsync_len = 10,
	471	.vsync_len = 2,
	472	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	473	.vmode = FB_VMODE_NONINTERLACED,
	474	},
	475	.width = -1,
	476	.height = -1,
	477	.tim2 = TIM2_IVS \| TIM2_IHS \| TIM2_IPC,
4eccca20	478	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	479	.bpp = 16,
	480	};
	481
	482	static struct clcd_panel epson_2_2_in = {
	483	.mode = {
	484	.name = "Epson QCIF",
	485	.refresh = 390,
	486	.xres = 176,
	487	.yres = 220,
	488	.pixclock = 62500,
	489	.left_margin = 3,
	490	.right_margin = 2,
	491	.upper_margin = 1,
	492	.lower_margin = 0,
	493	.hsync_len = 3,
	494	.vsync_len = 2,
	495	.sync = 0,
	496	.vmode = FB_VMODE_NONINTERLACED,
	497	},
	498	.width = -1,
	499	.height = -1,
	500	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	501	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	502	.bpp = 16,
	503	};
	504
	505	/*
	506	* Detect which LCD panel is connected, and return the appropriate
	507	* clcd_panel structure. Note: we do not have any information on
	508	* the required timings for the 8.4in panel, so we presently assume
	509	* VGA timings.
	510	*/
	511	static struct clcd_panel *realview_clcd_panel(void)
	512	{
	513	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
c34a1025 CT	514	struct clcd_panel *vga_panel;
c34a1025 CT	515	struct clcd_panel *panel;
8ad68bbf CM	516	u32 val;
8ad68bbf CM	517
c34a1025 CT	518	if (machine_is_realview_eb())
	519	vga_panel = &vga;
	520	else
	521	vga_panel = &xvga;
	522
8ad68bbf CM	523	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	524	if (val == SYS_CLCD_ID_SANYO_3_8)
	525	panel = &sanyo_3_8_in;
	526	else if (val == SYS_CLCD_ID_SANYO_2_5)
	527	panel = &sanyo_2_5_in;
	528	else if (val == SYS_CLCD_ID_EPSON_2_2)
	529	panel = &epson_2_2_in;
	530	else if (val == SYS_CLCD_ID_VGA)
c34a1025	531	panel = vga_panel;
8ad68bbf CM	532	else {
	533	printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
	534	val);
c34a1025	535	panel = vga_panel;
8ad68bbf CM	536	}
	537
	538	return panel;
	539	}
	540
	541	/*
	542	* Disable all display connectors on the interface module.
	543	*/
	544	static void realview_clcd_disable(struct clcd_fb *fb)
	545	{
	546	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	547	u32 val;
	548
	549	val = readl(sys_clcd);
	550	val &= ~SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	551	writel(val, sys_clcd);
	552	}
	553
	554	/*
	555	* Enable the relevant connector on the interface module.
	556	*/
	557	static void realview_clcd_enable(struct clcd_fb *fb)
	558	{
	559	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	560	u32 val;
	561
8ad68bbf	562	/*
9e7714d0	563	* Enable the PSUs
8ad68bbf	564	*/
9e7714d0	565	val = readl(sys_clcd);
8ad68bbf CM	566	val \|= SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	567	writel(val, sys_clcd);
	568	}
	569
8ad68bbf CM	570	static int realview_clcd_setup(struct clcd_fb *fb)
8ad68bbf CM	571	{
c34a1025	572	unsigned long framesize;
8ad68bbf CM	573	dma_addr_t dma;
8ad68bbf CM	574
c34a1025 CT	575	if (machine_is_realview_eb())
	576	/* VGA, 16bpp */
	577	framesize = 640 * 480 * 2;
	578	else
	579	/* XVGA, 16bpp */
	580	framesize = 1024 * 768 * 2;
	581
8ad68bbf CM	582	fb->panel = realview_clcd_panel();
	583
	584	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
c97c5aa8	585	&dma, GFP_KERNEL \| GFP_DMA);
8ad68bbf CM	586	if (!fb->fb.screen_base) {
	587	printk(KERN_ERR "CLCD: unable to map framebuffer\n");
	588	return -ENOMEM;
	589	}
	590
	591	fb->fb.fix.smem_start = dma;
	592	fb->fb.fix.smem_len = framesize;
	593
	594	return 0;
	595	}
	596
	597	static int realview_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	598	{
	599	return dma_mmap_writecombine(&fb->dev->dev, vma,
	600	fb->fb.screen_base,
	601	fb->fb.fix.smem_start,
	602	fb->fb.fix.smem_len);
	603	}
	604
	605	static void realview_clcd_remove(struct clcd_fb *fb)
	606	{
	607	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
	608	fb->fb.screen_base, fb->fb.fix.smem_start);
	609	}
	610
	611	struct clcd_board clcd_plat_data = {
	612	.name = "RealView",
	613	.check = clcdfb_check,
	614	.decode = clcdfb_decode,
	615	.disable = realview_clcd_disable,
	616	.enable = realview_clcd_enable,
	617	.setup = realview_clcd_setup,
	618	.mmap = realview_clcd_mmap,
	619	.remove = realview_clcd_remove,
	620	};
	621
	622	#ifdef CONFIG_LEDS
	623	#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
	624
	625	void realview_leds_event(led_event_t ledevt)
	626	{
	627	unsigned long flags;
	628	u32 val;
da055eb5	629	u32 led = 1 << smp_processor_id();
8ad68bbf CM	630
	631	local_irq_save(flags);
	632	val = readl(VA_LEDS_BASE);
	633
	634	switch (ledevt) {
	635	case led_idle_start:
da055eb5	636	val = val & ~led;
8ad68bbf CM	637	break;
	638
	639	case led_idle_end:
da055eb5	640	val = val \| led;
8ad68bbf CM	641	break;
	642
	643	case led_timer:
da055eb5	644	val = val ^ REALVIEW_SYS_LED7;
8ad68bbf CM	645	break;
	646
	647	case led_halted:
	648	val = 0;
	649	break;
	650
	651	default:
	652	break;
	653	}
	654
	655	writel(val, VA_LEDS_BASE);
	656	local_irq_restore(flags);
	657	}
	658	#endif /* CONFIG_LEDS */
	659
	660	/*
	661	* Where is the timer (VA)?
	662	*/
80192735 CM	663	void __iomem *timer0_va_base;
	664	void __iomem *timer1_va_base;
	665	void __iomem *timer2_va_base;
	666	void __iomem *timer3_va_base;
8ad68bbf	667
8ad68bbf	668	/*
a8655e83	669	* Set up the clock source and clock events devices
8ad68bbf	670	*/
8cc4c548	671	void __init realview_timer_init(unsigned int timer_irq)
8ad68bbf CM	672	{
	673	u32 val;
	674
	675	/*
	676	* set clock frequency:
	677	* REALVIEW_REFCLK is 32KHz
	678	* REALVIEW_TIMCLK is 1MHz
	679	*/
	680	val = readl(__io_address(REALVIEW_SCTL_BASE));
	681	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) \|
	682	(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) \|
	683	(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) \|
	684	(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) \| val,
	685	__io_address(REALVIEW_SCTL_BASE));
	686
	687	/*
	688	* Initialise to a known state (all timers off)
	689	*/
80192735 CM	690	writel(0, timer0_va_base + TIMER_CTRL);
	691	writel(0, timer1_va_base + TIMER_CTRL);
	692	writel(0, timer2_va_base + TIMER_CTRL);
	693	writel(0, timer3_va_base + TIMER_CTRL);
8ad68bbf	694
e3887714 RK	695	sp804_clocksource_init(timer3_va_base);
e3887714 RK	696	sp804_clockevents_init(timer0_va_base, timer_irq);
8ad68bbf	697	}
5b39d154 CM	698
	699	/*
	700	* Setup the memory banks.
	701	*/
	702	void realview_fixup(struct machine_desc mdesc, struct tag tags, char **from,
	703	struct meminfo *meminfo)
	704	{
	705	/*
	706	* Most RealView platforms have 512MB contiguous RAM at 0x70000000.
	707	* Half of this is mirrored at 0.
	708	*/
	709	#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
	710	meminfo->bank[0].start = 0x70000000;
	711	meminfo->bank[0].size = SZ_512M;
	712	meminfo->nr_banks = 1;
	713	#else
	714	meminfo->bank[0].start = 0;
	715	meminfo->bank[0].size = SZ_256M;
	716	meminfo->nr_banks = 1;
	717	#endif
	718	}