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Merge branch 'slab/next' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg...
[deliverable/linux.git] / arch / arm / mach-realview / realview_eb.c
CommitLineData
8ad68bbf
CM		 1/*
2 * linux/arch/arm/mach-realview/realview_eb.c
3 *
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
8ad68bbf 22#include <linux/init.h>
1be7228d 23#include <linux/platform_device.h>
edbaa603 24#include <linux/device.h>
a62c80e5 25#include <linux/amba/bus.h>
eb7fffa3 26#include <linux/amba/pl061.h>
6ef297f8 27#include <linux/amba/mmci.h>
d6ada860 28#include <linux/amba/pl022.h>
fced80c7 29#include <linux/io.h>
520f7bd7 30#include <linux/irqchip/arm-gic.h>
f9a6aa43 31#include <linux/platform_data/clk-realview.h>
7b6d864b 32#include <linux/reboot.h>
8ad68bbf 33
a09e64fb 34#include <mach/hardware.h>
8ad68bbf 35#include <asm/irq.h>
8ad68bbf 36#include <asm/mach-types.h>
cc9897df 37#include <asm/pgtable.h>
7770bddb 38#include <asm/hardware/cache-l2x0.h>
7c380f27 39#include <asm/smp_twd.h>
8ad68bbf
CM		 40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
8cc4c548 43#include <asm/mach/time.h>
8ad68bbf 44
a09e64fb
RK		 45#include <mach/board-eb.h>
46#include <mach/irqs.h>
8ad68bbf
CM		 47
48#include "core.h"
8ad68bbf
CM		 49
50static struct map_desc realview_eb_io_desc[] __initdata = {
1ffedce7
RK		 51 {
52 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
53 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
54 .length = SZ_4K,
55 .type = MT_DEVICE,
56 }, {
073b6ff3
CM		 57 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
58 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
1ffedce7
RK		 59 .length = SZ_4K,
60 .type = MT_DEVICE,
61 }, {
073b6ff3
CM		 62 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
63 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
1ffedce7
RK		 64 .length = SZ_4K,
65 .type = MT_DEVICE,
66 }, {
67 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
68 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
69 .length = SZ_4K,
70 .type = MT_DEVICE,
71 }, {
80192735
CM		 72 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
73 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
1ffedce7
RK		 74 .length = SZ_4K,
75 .type = MT_DEVICE,
76 }, {
80192735
CM		 77 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
78 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
1ffedce7
RK		 79 .length = SZ_4K,
80 .type = MT_DEVICE,
81 },
8ad68bbf 82#ifdef CONFIG_DEBUG_LL
1ffedce7 83 {
9a386f06
CM		 84 .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
85 .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
1ffedce7
RK		 86 .length = SZ_4K,
87 .type = MT_DEVICE,
88 }
8ad68bbf
CM		 89#endif
90};
91
7dd19e75
CM		 92static struct map_desc realview_eb11mp_io_desc[] __initdata = {
93 {
34ae6c96
MZ		 94 .virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE),
95 .pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE),
96 .length = REALVIEW_EB11MP_PRIV_MEM_SIZE,
7dd19e75
CM		 97 .type = MT_DEVICE,
98 }, {
99 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
100 .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
101 .length = SZ_8K,
102 .type = MT_DEVICE,
103 }
104};
105
8ad68bbf
CM		 106static void __init realview_eb_map_io(void)
107{
108 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
4c3ea371 109 if (core_tile_eb11mp() || core_tile_a9mp())
7dd19e75 110 iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
8ad68bbf
CM		 111}
112
eb7fffa3
RK		 113static struct pl061_platform_data gpio0_plat_data = {
114 .gpio_base = 0,
eb7fffa3
RK		 115};
116
117static struct pl061_platform_data gpio1_plat_data = {
118 .gpio_base = 8,
eb7fffa3
RK		 119};
120
121static struct pl061_platform_data gpio2_plat_data = {
122 .gpio_base = 16,
eb7fffa3
RK		 123};
124
d6ada860
LW		 125static struct pl022_ssp_controller ssp0_plat_data = {
126 .bus_id = 0,
127 .enable_dma = 0,
128 .num_chipselect = 1,
129};
130
0fc2a161
CM		 131/*
132 * RealView EB AMBA devices
133 */
134
135/*
136 * These devices are connected via the core APB bridge
137 */
0dada61a
RK		 138#define GPIO2_IRQ { IRQ_EB_GPIO2 }
139#define GPIO3_IRQ { IRQ_EB_GPIO3 }
0fc2a161 140
0dada61a 141#define AACI_IRQ { IRQ_EB_AACI }
0fc2a161 142#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
0dada61a
RK		 143#define KMI0_IRQ { IRQ_EB_KMI0 }
144#define KMI1_IRQ { IRQ_EB_KMI1 }
0fc2a161
CM		 145
146/*
147 * These devices are connected directly to the multi-layer AHB switch
148 */
0dada61a
RK		 149#define EB_SMC_IRQ { }
150#define MPMC_IRQ { }
151#define EB_CLCD_IRQ { IRQ_EB_CLCD }
152#define DMAC_IRQ { IRQ_EB_DMA }
0fc2a161
CM		 153
154/*
155 * These devices are connected via the core APB bridge
156 */
0dada61a
RK		 157#define SCTL_IRQ { }
158#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG }
159#define EB_GPIO0_IRQ { IRQ_EB_GPIO0 }
160#define GPIO1_IRQ { IRQ_EB_GPIO1 }
161#define EB_RTC_IRQ { IRQ_EB_RTC }
0fc2a161
CM		 162
163/*
164 * These devices are connected via the DMA APB bridge
165 */
0dada61a
RK		 166#define SCI_IRQ { IRQ_EB_SCI }
167#define EB_UART0_IRQ { IRQ_EB_UART0 }
168#define EB_UART1_IRQ { IRQ_EB_UART1 }
169#define EB_UART2_IRQ { IRQ_EB_UART2 }
170#define EB_UART3_IRQ { IRQ_EB_UART3 }
171#define EB_SSP_IRQ { IRQ_EB_SSP }
0fc2a161 172
8ad68bbf 173/* FPGA Primecells */
9199340b
RK		 174APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
175APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
176APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
177APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
178APB_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
8ad68bbf
CM		 179
180/* DevChip Primecells */
9199340b
RK		 181AHB_DEVICE(smc, "dev:smc", EB_SMC, NULL);
182AHB_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data);
183AHB_DEVICE(dmac, "dev:dmac", DMAC, NULL);
184AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
185APB_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL);
186APB_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
187APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
188APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
189APB_DEVICE(rtc, "dev:rtc", EB_RTC, NULL);
190APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
191APB_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
192APB_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
193APB_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
194APB_DEVICE(ssp0, "dev:ssp0", EB_SSP, &ssp0_plat_data);
8ad68bbf
CM		 195
196static struct amba_device *amba_devs[] __initdata = {
197 &dmac_device,
198 &uart0_device,
199 &uart1_device,
200 &uart2_device,
201 &uart3_device,
202 &smc_device,
203 &clcd_device,
204 &sctl_device,
205 &wdog_device,
206 &gpio0_device,
207 &gpio1_device,
208 &gpio2_device,
209 &rtc_device,
210 &sci0_device,
211 &ssp0_device,
212 &aaci_device,
213 &mmc0_device,
214 &kmi0_device,
215 &kmi1_device,
216};
217
0fc2a161
CM		 218/*
219 * RealView EB platform devices
220 */
a44ddfd5
CM		 221static struct resource realview_eb_flash_resource = {
222 .start = REALVIEW_EB_FLASH_BASE,
223 .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
224 .flags = IORESOURCE_MEM,
225};
0fc2a161 226
be4f3c86 227static struct resource realview_eb_eth_resources[] = {
0fc2a161 228 [0] = {
393538e6
CM		 229 .start = REALVIEW_EB_ETH_BASE,
230 .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
0fc2a161
CM		 231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = IRQ_EB_ETH,
235 .end = IRQ_EB_ETH,
236 .flags = IORESOURCE_IRQ,
237 },
238};
239
be4f3c86
CM		 240/*
241 * Detect and register the correct Ethernet device. RealView/EB rev D
242 * platforms use the newer SMSC LAN9118 Ethernet chip
243 */
244static int eth_device_register(void)
245{
393538e6 246 void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
0a381330 247 const char *name = NULL;
be4f3c86
CM		 248 u32 idrev;
249
250 if (!eth_addr)
251 return -ENOMEM;
252
253 idrev = readl(eth_addr + 0x50);
0a381330
CM		 254 if ((idrev & 0xFFFF0000) != 0x01180000)
255 /* SMSC LAN9118 not present, use LAN91C111 instead */
256 name = "smc91x";
be4f3c86
CM		 257
258 iounmap(eth_addr);
0a381330 259 return realview_eth_register(name, realview_eb_eth_resources);
be4f3c86
CM		 260}
261
7db21712
CM		 262static struct resource realview_eb_isp1761_resources[] = {
263 [0] = {
264 .start = REALVIEW_EB_USB_BASE,
265 .end = REALVIEW_EB_USB_BASE + SZ_128K - 1,
266 .flags = IORESOURCE_MEM,
267 },
268 [1] = {
269 .start = IRQ_EB_USB,
270 .end = IRQ_EB_USB,
271 .flags = IORESOURCE_IRQ,
272 },
273};
274
f417cbad
WD		 275static struct resource pmu_resources[] = {
276 [0] = {
277 .start = IRQ_EB11MP_PMU_CPU0,
278 .end = IRQ_EB11MP_PMU_CPU0,
279 .flags = IORESOURCE_IRQ,
280 },
281 [1] = {
282 .start = IRQ_EB11MP_PMU_CPU1,
283 .end = IRQ_EB11MP_PMU_CPU1,
284 .flags = IORESOURCE_IRQ,
285 },
286 [2] = {
287 .start = IRQ_EB11MP_PMU_CPU2,
288 .end = IRQ_EB11MP_PMU_CPU2,
289 .flags = IORESOURCE_IRQ,
290 },
291 [3] = {
292 .start = IRQ_EB11MP_PMU_CPU3,
293 .end = IRQ_EB11MP_PMU_CPU3,
294 .flags = IORESOURCE_IRQ,
295 },
296};
297
298static struct platform_device pmu_device = {
299 .name = "arm-pmu",
df3d17e0 300 .id = -1,
f417cbad
WD		 301 .num_resources = ARRAY_SIZE(pmu_resources),
302 .resource = pmu_resources,
303};
304
d161edfb
LW		 305static struct resource char_lcd_resources[] = {
306 {
307 .start = REALVIEW_CHAR_LCD_BASE,
308 .end = (REALVIEW_CHAR_LCD_BASE + SZ_4K - 1),
309 .flags = IORESOURCE_MEM,
310 },
311 {
312 .start = IRQ_EB_CHARLCD,
313 .end = IRQ_EB_CHARLCD,
314 .flags = IORESOURCE_IRQ,
315 },
316};
317
318static struct platform_device char_lcd_device = {
319 .name = "arm-charlcd",
320 .id = -1,
321 .num_resources = ARRAY_SIZE(char_lcd_resources),
322 .resource = char_lcd_resources,
323};
324
8ad68bbf
CM		 325static void __init gic_init_irq(void)
326{
4c3ea371 327 if (core_tile_eb11mp() || core_tile_a9mp()) {
7dd19e75
CM		 328 unsigned int pldctrl;
329
330 /* new irq mode */
331 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
332 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
333 pldctrl |= 0x00800000;
334 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
335 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
336
337 /* core tile GIC, primary */
b580b899 338 gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE),
ff2e27ae 339 __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
7dd19e75 340
41579f49 341#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
7dd19e75 342 /* board GIC, secondary */
0efc48ec 343 gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE),
b580b899 344 __io_address(REALVIEW_EB_GIC_CPU_BASE));
7dd19e75 345 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
3edf22ab 346#endif
7dd19e75
CM		 347 } else {
348 /* board GIC, primary */
b580b899 349 gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE),
ff2e27ae 350 __io_address(REALVIEW_EB_GIC_CPU_BASE));
7dd19e75 351 }
8ad68bbf
CM		 352}
353
0fc2a161
CM		 354/*
355 * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
356 */
357static void realview_eb11mp_fixup(void)
358{
359 /* AMBA devices */
360 dmac_device.irq[0] = IRQ_EB11MP_DMA;
361 uart0_device.irq[0] = IRQ_EB11MP_UART0;
362 uart1_device.irq[0] = IRQ_EB11MP_UART1;
363 uart2_device.irq[0] = IRQ_EB11MP_UART2;
364 uart3_device.irq[0] = IRQ_EB11MP_UART3;
365 clcd_device.irq[0] = IRQ_EB11MP_CLCD;
366 wdog_device.irq[0] = IRQ_EB11MP_WDOG;
367 gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
368 gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
369 gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
370 rtc_device.irq[0] = IRQ_EB11MP_RTC;
371 sci0_device.irq[0] = IRQ_EB11MP_SCI;
372 ssp0_device.irq[0] = IRQ_EB11MP_SSP;
373 aaci_device.irq[0] = IRQ_EB11MP_AACI;
374 mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
375 mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
376 kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
377 kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
378
379 /* platform devices */
be4f3c86
CM		 380 realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
381 realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
7db21712
CM		 382 realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB;
383 realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB;
0fc2a161 384}
0fc2a161 385
7c380f27
MZ		 386#ifdef CONFIG_HAVE_ARM_TWD
387static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
388 REALVIEW_EB11MP_TWD_BASE,
389 IRQ_LOCALTIMER);
390
391static void __init realview_eb_twd_init(void)
392{
393 if (core_tile_eb11mp() || core_tile_a9mp()) {
394 int err = twd_local_timer_register(&twd_local_timer);
395 if (err)
396 pr_err("twd_local_timer_register failed %d\n", err);
397 }
398}
399#else
400#define realview_eb_twd_init() do { } while(0)
401#endif
402
8cc4c548
CM		 403static void __init realview_eb_timer_init(void)
404{
405 unsigned int timer_irq;
406
80192735
CM		 407 timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
408 timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
409 timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
410 timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
411
7c380f27 412 if (core_tile_eb11mp() || core_tile_a9mp())
8cc4c548 413 timer_irq = IRQ_EB11MP_TIMER0_1;
7c380f27 414 else
8cc4c548
CM		 415 timer_irq = IRQ_EB_TIMER0_1;
416
f9a6aa43 417 realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
8cc4c548 418 realview_timer_init(timer_irq);
7c380f27 419 realview_eb_twd_init();
8cc4c548
CM		 420}
421
7b6d864b 422static void realview_eb_restart(enum reboot_mode mode, const char *cmd)
4c9f8be7
CT		 423{
424 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
425 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
426
427 /*
428 * To reset, we hit the on-board reset register
429 * in the system FPGA
430 */
431 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
432 if (core_tile_eb11mp())
433 __raw_writel(0x0008, reset_ctrl);
47cacdd4 434 dsb();
4c9f8be7
CT		 435}
436
8ad68bbf
CM		 437static void __init realview_eb_init(void)
438{
439 int i;
440
4c3ea371 441 if (core_tile_eb11mp() || core_tile_a9mp()) {
7dd19e75
CM		 442 realview_eb11mp_fixup();
443
ba927951 444#ifdef CONFIG_CACHE_L2X0
7dd19e75
CM		 445 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
446 * Bits: .... ...0 0111 1001 0000 .... .... .... */
447 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
ba927951 448#endif
f417cbad 449 platform_device_register(&pmu_device);
7dd19e75 450 }
0fc2a161 451
a44ddfd5 452 realview_flash_register(&realview_eb_flash_resource, 1);
6b65cd74 453 platform_device_register(&realview_i2c_device);
d161edfb 454 platform_device_register(&char_lcd_device);
be4f3c86 455 eth_device_register();
7db21712 456 realview_usb_register(realview_eb_isp1761_resources);
8ad68bbf
CM		 457
458 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
459 struct amba_device *d = amba_devs[i];
460 amba_device_register(d, &iomem_resource);
461 }
8ad68bbf
CM		 462}
463
464MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
465 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
9ddea57e 466 .atag_offset = 0x100,
810883f0 467 .smp = smp_ops(realview_smp_ops),
5b39d154 468 .fixup = realview_fixup,
8ad68bbf 469 .map_io = realview_eb_map_io,
631e55f9 470 .init_early = realview_init_early,
8ad68bbf 471 .init_irq = gic_init_irq,
6bb27d73 472 .init_time = realview_eb_timer_init,
8ad68bbf 473 .init_machine = realview_eb_init,
00e9125e
NP		 474#ifdef CONFIG_ZONE_DMA
475 .dma_zone_size = SZ_256M,
476#endif
47cacdd4 477 .restart = realview_eb_restart,
8ad68bbf 478MACHINE_END
Linux kernel - Deliverables
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