[deliverable/linux.git] / arch / arm / mach-s3c2410 / include / mach / dma.h

/* arch/arm/mach-s3c2410/include/mach/dma.h
 *
 * Copyright (C) 2003-2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C24XX DMA support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__

#include <plat/dma.h>
#include <linux/sysdev.h>

#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */

/* We use `virtual` dma channels to hide the fact we have only a limited
 * number of DMA channels, and not of all of them (dependent on the device)
 * can be attached to any DMA source. We therefore let the DMA core handle
 * the allocation of hardware channels to clients.
*/

enum dma_ch {
	DMACH_XD0,
	DMACH_XD1,
	DMACH_SDI,
	DMACH_SPI0,
	DMACH_SPI1,
	DMACH_UART0,
	DMACH_UART1,
	DMACH_UART2,
	DMACH_TIMER,
	DMACH_I2S_IN,
	DMACH_I2S_OUT,
	DMACH_PCM_IN,
	DMACH_PCM_OUT,
	DMACH_MIC_IN,
	DMACH_USB_EP1,
	DMACH_USB_EP2,
	DMACH_USB_EP3,
	DMACH_USB_EP4,
	DMACH_UART0_SRC2,	/* s3c2412 second uart sources */
	DMACH_UART1_SRC2,
	DMACH_UART2_SRC2,
	DMACH_UART3,		/* s3c2443 has extra uart */
	DMACH_UART3_SRC2,
	DMACH_MAX,		/* the end entry */
};

#define DMACH_LOW_LEVEL	(1<<28)	/* use this to specifiy hardware ch no */

/* we have 4 dma channels */
#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
#define S3C_DMA_CHANNELS		(4)
#else
#define S3C_DMA_CHANNELS		(6)
#endif

/* types */

enum s3c2410_dma_state {
	S3C2410_DMA_IDLE,
	S3C2410_DMA_RUNNING,
	S3C2410_DMA_PAUSED
};

/* enum s3c2410_dma_loadst
 *
 * This represents the state of the DMA engine, wrt to the loaded / running
 * transfers. Since we don't have any way of knowing exactly the state of
 * the DMA transfers, we need to know the state to make decisions on wether
 * we can
 *
 * S3C2410_DMA_NONE
 *
 * There are no buffers loaded (the channel should be inactive)
 *
 * S3C2410_DMA_1LOADED
 *
 * There is one buffer loaded, however it has not been confirmed to be
 * loaded by the DMA engine. This may be because the channel is not
 * yet running, or the DMA driver decided that it was too costly to
 * sit and wait for it to happen.
 *
 * S3C2410_DMA_1RUNNING
 *
 * The buffer has been confirmed running, and not finisged
 *
 * S3C2410_DMA_1LOADED_1RUNNING
 *
 * There is a buffer waiting to be loaded by the DMA engine, and one
 * currently running.
*/

enum s3c2410_dma_loadst {
	S3C2410_DMALOAD_NONE,
	S3C2410_DMALOAD_1LOADED,
	S3C2410_DMALOAD_1RUNNING,
	S3C2410_DMALOAD_1LOADED_1RUNNING,
};


/* flags */

#define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
					    * waiting for reloads */
#define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */

#define S3C2410_DMAF_CIRCULAR	(1 << 2)	/* no circular dma support */

/* dma buffer */

struct s3c2410_dma_buf;

/* s3c2410_dma_buf
 *
 * internally used buffer structure to describe a queued or running
 * buffer.
*/

struct s3c2410_dma_buf {
	struct s3c2410_dma_buf	*next;
	int			 magic;		/* magic */
	int			 size;		/* buffer size in bytes */
	dma_addr_t		 data;		/* start of DMA data */
	dma_addr_t		 ptr;		/* where the DMA got to [1] */
	void			*id;		/* client's id */
};

/* [1] is this updated for both recv/send modes? */

struct s3c2410_dma_stats {
	unsigned long		loads;
	unsigned long		timeout_longest;
	unsigned long		timeout_shortest;
	unsigned long		timeout_avg;
	unsigned long		timeout_failed;
};

struct s3c2410_dma_map;

/* struct s3c2410_dma_chan
 *
 * full state information for each DMA channel
*/

struct s3c2410_dma_chan {
	/* channel state flags and information */
	unsigned char		 number;      /* number of this dma channel */
	unsigned char		 in_use;      /* channel allocated */
	unsigned char		 irq_claimed; /* irq claimed for channel */
	unsigned char		 irq_enabled; /* irq enabled for channel */
	unsigned char		 xfer_unit;   /* size of an transfer */

	/* channel state */

	enum s3c2410_dma_state	 state;
	enum s3c2410_dma_loadst	 load_state;
	struct s3c2410_dma_client *client;

	/* channel configuration */
	enum s3c2410_dmasrc	 source;
	enum dma_ch		 req_ch;
	unsigned long		 dev_addr;
	unsigned long		 load_timeout;
	unsigned int		 flags;		/* channel flags */

	struct s3c24xx_dma_map	*map;		/* channel hw maps */

	/* channel's hardware position and configuration */
	void __iomem		*regs;		/* channels registers */
	void __iomem		*addr_reg;	/* data address register */
	unsigned int		 irq;		/* channel irq */
	unsigned long		 dcon;		/* default value of DCON */

	/* driver handles */
	s3c2410_dma_cbfn_t	 callback_fn;	/* buffer done callback */
	s3c2410_dma_opfn_t	 op_fn;		/* channel op callback */

	/* stats gathering */
	struct s3c2410_dma_stats *stats;
	struct s3c2410_dma_stats  stats_store;

	/* buffer list and information */
	struct s3c2410_dma_buf	*curr;		/* current dma buffer */
	struct s3c2410_dma_buf	*next;		/* next buffer to load */
	struct s3c2410_dma_buf	*end;		/* end of queue */

	/* system device */
	struct sys_device	dev;
};

typedef unsigned long dma_device_t;

static inline bool s3c_dma_has_circular(void)
{
	return false;
}

#endif /* __ASM_ARCH_DMA_H */
Commit	Line	Data
a09e64fb	1	/* arch/arm/mach-s3c2410/include/mach/dma.h
1da177e4	2	*
ccae941e	3	* Copyright (C) 2003-2006 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <ben@simtec.co.uk>
1da177e4 LT	5	*
44dc9404	6	* Samsung S3C24XX DMA support
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#ifndef __ASM_ARCH_DMA_H
	14	#define __ASM_ARCH_DMA_H __FILE__
	15
c133c290	16	#include <plat/dma.h>
1da177e4	17	#include <linux/sysdev.h>
1da177e4	18
1da177e4 LT	19	#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
1da177e4 LT	20
505788cc	21	/* We use `virtual` dma channels to hide the fact we have only a limited
25985edc	22	* number of DMA channels, and not of all of them (dependent on the device)
505788cc BD	23	* can be attached to any DMA source. We therefore let the DMA core handle
	24	* the allocation of hardware channels to clients.
	25	*/
	26
	27	enum dma_ch {
	28	DMACH_XD0,
	29	DMACH_XD1,
	30	DMACH_SDI,
	31	DMACH_SPI0,
	32	DMACH_SPI1,
	33	DMACH_UART0,
	34	DMACH_UART1,
	35	DMACH_UART2,
	36	DMACH_TIMER,
	37	DMACH_I2S_IN,
	38	DMACH_I2S_OUT,
	39	DMACH_PCM_IN,
	40	DMACH_PCM_OUT,
	41	DMACH_MIC_IN,
	42	DMACH_USB_EP1,
	43	DMACH_USB_EP2,
	44	DMACH_USB_EP3,
	45	DMACH_USB_EP4,
34348012 BD	46	DMACH_UART0_SRC2, /* s3c2412 second uart sources */
	47	DMACH_UART1_SRC2,
	48	DMACH_UART2_SRC2,
15e4db7b BD	49	DMACH_UART3, /* s3c2443 has extra uart */
15e4db7b BD	50	DMACH_UART3_SRC2,
505788cc BD	51	DMACH_MAX, /* the end entry */
	52	};
	53
	54	#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
	55
1da177e4	56	/* we have 4 dma channels */
7cfdee9f	57	#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
97c1b145	58	#define S3C_DMA_CHANNELS (4)
15e4db7b	59	#else
97c1b145	60	#define S3C_DMA_CHANNELS (6)
15e4db7b	61	#endif
1da177e4 LT	62
	63	/* types */
	64
f105a7df	65	enum s3c2410_dma_state {
1da177e4 LT	66	S3C2410_DMA_IDLE,
	67	S3C2410_DMA_RUNNING,
	68	S3C2410_DMA_PAUSED
f105a7df	69	};
1da177e4	70
f105a7df	71	/* enum s3c2410_dma_loadst
1da177e4 LT	72	*
	73	* This represents the state of the DMA engine, wrt to the loaded / running
	74	* transfers. Since we don't have any way of knowing exactly the state of
	75	* the DMA transfers, we need to know the state to make decisions on wether
	76	* we can
	77	*
	78	* S3C2410_DMA_NONE
	79	*
	80	* There are no buffers loaded (the channel should be inactive)
	81	*
	82	* S3C2410_DMA_1LOADED
	83	*
	84	* There is one buffer loaded, however it has not been confirmed to be
	85	* loaded by the DMA engine. This may be because the channel is not
	86	* yet running, or the DMA driver decided that it was too costly to
	87	* sit and wait for it to happen.
	88	*
	89	* S3C2410_DMA_1RUNNING
	90	*
	91	* The buffer has been confirmed running, and not finisged
	92	*
	93	* S3C2410_DMA_1LOADED_1RUNNING
	94	*
	95	* There is a buffer waiting to be loaded by the DMA engine, and one
	96	* currently running.
	97	*/
	98
f105a7df	99	enum s3c2410_dma_loadst {
1da177e4 LT	100	S3C2410_DMALOAD_NONE,
	101	S3C2410_DMALOAD_1LOADED,
	102	S3C2410_DMALOAD_1RUNNING,
	103	S3C2410_DMALOAD_1LOADED_1RUNNING,
f105a7df	104	};
1da177e4	105
1da177e4	106
1da177e4 LT	107	/* flags */
	108
	109	#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
	110	* waiting for reloads */
	111	#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
	112
e3d80248 BD	113	#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
e3d80248 BD	114
1da177e4 LT	115	/* dma buffer */
1da177e4 LT	116
c133c290	117	struct s3c2410_dma_buf;
1da177e4	118
c133c290	119	/* s3c2410_dma_buf
1da177e4 LT	120	*
	121	* internally used buffer structure to describe a queued or running
	122	* buffer.
	123	*/
	124
f105a7df	125	struct s3c2410_dma_buf {
57bcdafc BD	126	struct s3c2410_dma_buf *next;
	127	int magic; /* magic */
	128	int size; /* buffer size in bytes */
	129	dma_addr_t data; /* start of DMA data */
	130	dma_addr_t ptr; /* where the DMA got to [1] */
	131	void id; / client's id */
1da177e4 LT	132	};
	133
	134	/* [1] is this updated for both recv/send modes? */
	135
f105a7df	136	struct s3c2410_dma_stats {
57bcdafc BD	137	unsigned long loads;
	138	unsigned long timeout_longest;
	139	unsigned long timeout_shortest;
	140	unsigned long timeout_avg;
	141	unsigned long timeout_failed;
1da177e4 LT	142	};
1da177e4 LT	143
505788cc BD	144	struct s3c2410_dma_map;
505788cc BD	145
f105a7df	146	/* struct s3c2410_dma_chan
1da177e4 LT	147	*
	148	* full state information for each DMA channel
	149	*/
	150
f105a7df	151	struct s3c2410_dma_chan {
1da177e4	152	/* channel state flags and information */
57bcdafc BD	153	unsigned char number; /* number of this dma channel */
	154	unsigned char in_use; /* channel allocated */
	155	unsigned char irq_claimed; /* irq claimed for channel */
	156	unsigned char irq_enabled; /* irq enabled for channel */
	157	unsigned char xfer_unit; /* size of an transfer */
1da177e4 LT	158
	159	/* channel state */
	160
57bcdafc BD	161	enum s3c2410_dma_state state;
	162	enum s3c2410_dma_loadst load_state;
	163	struct s3c2410_dma_client *client;
1da177e4 LT	164
1da177e4 LT	165	/* channel configuration */
57bcdafc	166	enum s3c2410_dmasrc source;
8970ef47	167	enum dma_ch req_ch;
57bcdafc BD	168	unsigned long dev_addr;
	169	unsigned long load_timeout;
	170	unsigned int flags; /* channel flags */
1da177e4	171
505788cc BD	172	struct s3c24xx_dma_map map; / channel hw maps */
505788cc BD	173
1da177e4	174	/* channel's hardware position and configuration */
57bcdafc BD	175	void __iomem regs; / channels registers */
	176	void __iomem addr_reg; / data address register */
	177	unsigned int irq; /* channel irq */
	178	unsigned long dcon; /* default value of DCON */
1da177e4 LT	179
1da177e4 LT	180	/* driver handles */
57bcdafc BD	181	s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
57bcdafc BD	182	s3c2410_dma_opfn_t op_fn; /* channel op callback */
1da177e4 LT	183
1da177e4 LT	184	/* stats gathering */
57bcdafc BD	185	struct s3c2410_dma_stats *stats;
57bcdafc BD	186	struct s3c2410_dma_stats stats_store;
1da177e4 LT	187
1da177e4 LT	188	/* buffer list and information */
57bcdafc BD	189	struct s3c2410_dma_buf curr; / current dma buffer */
	190	struct s3c2410_dma_buf next; / next buffer to load */
	191	struct s3c2410_dma_buf end; / end of queue */
1da177e4 LT	192
	193	/* system device */
	194	struct sys_device dev;
	195	};
	196
1da177e4 LT	197	typedef unsigned long dma_device_t;
1da177e4 LT	198
e3d80248 BD	199	static inline bool s3c_dma_has_circular(void)
	200	{
	201	return false;
	202	}
	203
1da177e4	204	#endif /* __ASM_ARCH_DMA_H */