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1 | /* linux/arch/arm/mach-s3c2443/irq.c |
2 | * | |
3 | * Copyright (c) 2007 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/ioport.h> | |
4a858cfc | 26 | #include <linux/device.h> |
fced80c7 | 27 | #include <linux/io.h> |
e4d06e39 | 28 | |
a09e64fb | 29 | #include <mach/hardware.h> |
e4d06e39 | 30 | #include <asm/irq.h> |
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31 | |
32 | #include <asm/mach/irq.h> | |
33 | ||
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34 | #include <mach/regs-irq.h> |
35 | #include <mach/regs-gpio.h> | |
e4d06e39 | 36 | |
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37 | #include <plat/cpu.h> |
38 | #include <plat/pm.h> | |
39 | #include <plat/irq.h> | |
e4d06e39 | 40 | |
72262e8b | 41 | #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) |
e4d06e39 | 42 | |
72262e8b | 43 | static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len) |
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44 | { |
45 | unsigned int subsrc, submsk; | |
72262e8b | 46 | unsigned int end; |
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47 | |
48 | /* read the current pending interrupts, and the mask | |
49 | * for what it is available */ | |
50 | ||
51 | subsrc = __raw_readl(S3C2410_SUBSRCPND); | |
52 | submsk = __raw_readl(S3C2410_INTSUBMSK); | |
53 | ||
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54 | subsrc &= ~submsk; |
55 | subsrc >>= (irq - S3C2410_IRQSUB(0)); | |
56 | subsrc &= (1 << len)-1; | |
57 | ||
58 | end = len + irq; | |
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59 | |
60 | for (; irq < end && subsrc; irq++) { | |
61 | if (subsrc & 1) | |
d8aa0251 | 62 | generic_handle_irq(irq); |
72262e8b | 63 | |
72262e8b | 64 | subsrc >>= 1; |
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65 | } |
66 | } | |
67 | ||
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68 | /* WDT/AC97 sub interrupts */ |
69 | ||
70 | static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc) | |
71 | { | |
72 | s3c2443_irq_demux(IRQ_S3C2443_WDT, 4); | |
73 | } | |
e4d06e39 | 74 | |
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75 | #define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) |
76 | #define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) | |
e4d06e39 | 77 | |
57436c2d | 78 | static void s3c2443_irq_wdtac97_mask(struct irq_data *data) |
e4d06e39 | 79 | { |
57436c2d | 80 | s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); |
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81 | } |
82 | ||
57436c2d | 83 | static void s3c2443_irq_wdtac97_unmask(struct irq_data *data) |
e4d06e39 | 84 | { |
57436c2d | 85 | s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97); |
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86 | } |
87 | ||
57436c2d | 88 | static void s3c2443_irq_wdtac97_ack(struct irq_data *data) |
e4d06e39 | 89 | { |
57436c2d | 90 | s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); |
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91 | } |
92 | ||
72262e8b | 93 | static struct irq_chip s3c2443_irq_wdtac97 = { |
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94 | .irq_mask = s3c2443_irq_wdtac97_mask, |
95 | .irq_unmask = s3c2443_irq_wdtac97_unmask, | |
96 | .irq_ack = s3c2443_irq_wdtac97_ack, | |
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97 | }; |
98 | ||
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99 | /* LCD sub interrupts */ |
100 | ||
101 | static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) | |
e4d06e39 | 102 | { |
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103 | s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4); |
104 | } | |
e4d06e39 | 105 | |
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106 | #define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) |
107 | #define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) | |
108 | ||
57436c2d | 109 | static void s3c2443_irq_lcd_mask(struct irq_data *data) |
72262e8b | 110 | { |
57436c2d | 111 | s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD); |
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112 | } |
113 | ||
57436c2d | 114 | static void s3c2443_irq_lcd_unmask(struct irq_data *data) |
72262e8b | 115 | { |
57436c2d | 116 | s3c_irqsub_unmask(data->irq, INTMSK_LCD); |
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117 | } |
118 | ||
57436c2d | 119 | static void s3c2443_irq_lcd_ack(struct irq_data *data) |
72262e8b | 120 | { |
57436c2d | 121 | s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD); |
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122 | } |
123 | ||
124 | static struct irq_chip s3c2443_irq_lcd = { | |
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125 | .irq_mask = s3c2443_irq_lcd_mask, |
126 | .irq_unmask = s3c2443_irq_lcd_unmask, | |
127 | .irq_ack = s3c2443_irq_lcd_ack, | |
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128 | }; |
129 | ||
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130 | /* DMA sub interrupts */ |
131 | ||
132 | static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc) | |
133 | { | |
5455a51e | 134 | s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6); |
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135 | } |
136 | ||
137 | #define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) | |
138 | #define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) | |
139 | ||
57436c2d | 140 | static void s3c2443_irq_dma_mask(struct irq_data *data) |
72262e8b | 141 | { |
57436c2d | 142 | s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA); |
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143 | } |
144 | ||
57436c2d | 145 | static void s3c2443_irq_dma_unmask(struct irq_data *data) |
72262e8b | 146 | { |
57436c2d | 147 | s3c_irqsub_unmask(data->irq, INTMSK_DMA); |
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148 | } |
149 | ||
57436c2d | 150 | static void s3c2443_irq_dma_ack(struct irq_data *data) |
72262e8b | 151 | { |
57436c2d | 152 | s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA); |
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153 | } |
154 | ||
155 | static struct irq_chip s3c2443_irq_dma = { | |
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156 | .irq_mask = s3c2443_irq_dma_mask, |
157 | .irq_unmask = s3c2443_irq_dma_unmask, | |
158 | .irq_ack = s3c2443_irq_dma_ack, | |
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159 | }; |
160 | ||
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161 | /* UART3 sub interrupts */ |
162 | ||
163 | static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) | |
164 | { | |
18ad782c | 165 | s3c2443_irq_demux(IRQ_S3C2443_RX3, 3); |
72262e8b | 166 | } |
e4d06e39 | 167 | |
72262e8b | 168 | #define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) |
35bbcfe6 | 169 | #define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) |
e4d06e39 | 170 | |
57436c2d | 171 | static void s3c2443_irq_uart3_mask(struct irq_data *data) |
72262e8b | 172 | { |
57436c2d | 173 | s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3); |
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174 | } |
175 | ||
57436c2d | 176 | static void s3c2443_irq_uart3_unmask(struct irq_data *data) |
72262e8b | 177 | { |
57436c2d | 178 | s3c_irqsub_unmask(data->irq, INTMSK_UART3); |
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179 | } |
180 | ||
57436c2d | 181 | static void s3c2443_irq_uart3_ack(struct irq_data *data) |
72262e8b | 182 | { |
57436c2d | 183 | s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3); |
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184 | } |
185 | ||
186 | static struct irq_chip s3c2443_irq_uart3 = { | |
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187 | .irq_mask = s3c2443_irq_uart3_mask, |
188 | .irq_unmask = s3c2443_irq_uart3_unmask, | |
189 | .irq_ack = s3c2443_irq_uart3_ack, | |
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190 | }; |
191 | ||
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192 | /* CAM sub interrupts */ |
193 | ||
194 | static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc) | |
195 | { | |
196 | s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4); | |
197 | } | |
198 | ||
199 | #define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) | |
200 | #define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P) | |
201 | ||
57436c2d | 202 | static void s3c2443_irq_cam_mask(struct irq_data *data) |
72262e8b | 203 | { |
57436c2d | 204 | s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM); |
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205 | } |
206 | ||
57436c2d | 207 | static void s3c2443_irq_cam_unmask(struct irq_data *data) |
72262e8b | 208 | { |
57436c2d | 209 | s3c_irqsub_unmask(data->irq, INTMSK_CAM); |
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210 | } |
211 | ||
57436c2d | 212 | static void s3c2443_irq_cam_ack(struct irq_data *data) |
72262e8b | 213 | { |
57436c2d | 214 | s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM); |
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215 | } |
216 | ||
217 | static struct irq_chip s3c2443_irq_cam = { | |
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218 | .irq_mask = s3c2443_irq_cam_mask, |
219 | .irq_unmask = s3c2443_irq_cam_unmask, | |
220 | .irq_ack = s3c2443_irq_cam_ack, | |
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221 | }; |
222 | ||
223 | /* IRQ initialisation code */ | |
224 | ||
225 | static int __init s3c2443_add_sub(unsigned int base, | |
226 | void (*demux)(unsigned int, | |
227 | struct irq_desc *), | |
228 | struct irq_chip *chip, | |
229 | unsigned int start, unsigned int end) | |
230 | { | |
231 | unsigned int irqno; | |
232 | ||
f38c02f3 | 233 | irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); |
6845664a | 234 | irq_set_chained_handler(base, demux); |
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235 | |
236 | for (irqno = start; irqno <= end; irqno++) { | |
f38c02f3 | 237 | irq_set_chip_and_handler(irqno, chip, handle_level_irq); |
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238 | set_irq_flags(irqno, IRQF_VALID); |
239 | } | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
4a858cfc | 244 | static int __init s3c2443_irq_add(struct device *dev) |
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245 | { |
246 | printk("S3C2443: IRQ Support\n"); | |
247 | ||
248 | s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam, | |
249 | IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P); | |
250 | ||
251 | s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd, | |
252 | IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4); | |
253 | ||
254 | s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma, | |
255 | &s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5); | |
256 | ||
257 | s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3, | |
258 | &s3c2443_irq_uart3, | |
259 | IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3); | |
260 | ||
261 | s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97, | |
262 | &s3c2443_irq_wdtac97, | |
263 | IRQ_S3C2443_WDT, IRQ_S3C2443_AC97); | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
4a858cfc KS |
268 | static struct subsys_interface s3c2443_irq_interface = { |
269 | .name = "s3c2443_irq", | |
270 | .subsys = &s3c2443_subsys, | |
271 | .add_dev = s3c2443_irq_add, | |
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272 | }; |
273 | ||
008d931c | 274 | static int __init s3c2443_irq_init(void) |
e4d06e39 | 275 | { |
4a858cfc | 276 | return subsys_interface_register(&s3c2443_irq_interface); |
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277 | } |
278 | ||
279 | arch_initcall(s3c2443_irq_init); | |
280 |