[deliverable/linux.git] / arch / arm / mach-s3c24xx / dma-s3c2440.c

/* linux/arch/arm/mach-s3c2440/dma.c
 *
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2440 DMA selection
 *
 * http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/serial_core.h>

#include <mach/map.h>
#include <mach/dma.h>

#include <plat/dma-s3c24xx.h>
#include <plat/cpu.h>

#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <plat/regs-iis.h>
#include <plat/regs-spi.h>

static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
	[DMACH_XD0] = {
		.name		= "xdreq0",
		.channels[0]	= S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
	},
	[DMACH_XD1] = {
		.name		= "xdreq1",
		.channels[1]	= S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
	},
	[DMACH_SDI] = {
		.name		= "sdi",
		.channels[0]	= S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
		.channels[1]	= S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
		.channels[3]	= S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
	},
	[DMACH_SPI0] = {
		.name		= "spi0",
		.channels[1]	= S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
	},
	[DMACH_SPI1] = {
		.name		= "spi1",
		.channels[3]	= S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
	},
	[DMACH_UART0] = {
		.name		= "uart0",
		.channels[0]	= S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
	},
	[DMACH_UART1] = {
		.name		= "uart1",
		.channels[1]	= S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
	},
      	[DMACH_UART2] = {
		.name		= "uart2",
		.channels[3]	= S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
	},
	[DMACH_TIMER] = {
		.name		= "timer",
		.channels[0]	= S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
		.channels[3]	= S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
	},
	[DMACH_I2S_IN] = {
		.name		= "i2s-sdi",
		.channels[1]	= S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
	},
	[DMACH_I2S_OUT] = {
		.name		= "i2s-sdo",
		.channels[0]	= S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
	},
	[DMACH_PCM_IN] = {
		.name		= "pcm-in",
		.channels[0]	= S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
		.channels[2]	= S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
	},
	[DMACH_PCM_OUT] = {
		.name		= "pcm-out",
		.channels[1]	= S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
		.channels[3]	= S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
	},
	[DMACH_MIC_IN] = {
		.name		= "mic-in",
		.channels[2]	= S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
		.channels[3]	= S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
	},
	[DMACH_USB_EP1] = {
		.name		= "usb-ep1",
		.channels[0]	= S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
	},
	[DMACH_USB_EP2] = {
		.name		= "usb-ep2",
		.channels[1]	= S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
	},
	[DMACH_USB_EP3] = {
		.name		= "usb-ep3",
		.channels[2]	= S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
	},
	[DMACH_USB_EP4] = {
		.name		= "usb-ep4",
		.channels[3]	= S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
	},
};

static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
			       struct s3c24xx_dma_map *map)
{
	chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
}

static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
	.select		= s3c2440_dma_select,
	.dcon_mask	= 7 << 24,
	.map		= s3c2440_dma_mappings,
	.map_size	= ARRAY_SIZE(s3c2440_dma_mappings),
};

static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
	.channels	= {
		[DMACH_SDI]	= {
			.list	= {
				[0]	= 3 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
				[2]	= 1 | DMA_CH_VALID,
				[3]	= 0 | DMA_CH_VALID,
			},
		},
		[DMACH_I2S_IN]	= {
			.list	= {
				[0]	= 1 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
			},
		},
		[DMACH_I2S_OUT]	= {
			.list	= {
				[0]	= 2 | DMA_CH_VALID,
				[1]	= 1 | DMA_CH_VALID,
			},
		},
		[DMACH_PCM_IN] = {
			.list	= {
				[0]	= 2 | DMA_CH_VALID,
				[1]	= 1 | DMA_CH_VALID,
			},
		},
		[DMACH_PCM_OUT] = {
			.list	= {
				[0]	= 1 | DMA_CH_VALID,
				[1]	= 3 | DMA_CH_VALID,
			},
		},
		[DMACH_MIC_IN] = {
			.list	= {
				[0]	= 3 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
			},
		},
	},
};

static int __init s3c2440_dma_add(struct device *dev,
				  struct subsys_interface *sif)
{
	s3c2410_dma_init();
	s3c24xx_dma_order_set(&s3c2440_dma_order);
	return s3c24xx_dma_init_map(&s3c2440_dma_sel);
}

static struct subsys_interface s3c2440_dma_interface = {
	.name		= "s3c2440_dma",
	.subsys		= &s3c2440_subsys,
	.add_dev	= s3c2440_dma_add,
};

static int __init s3c2440_dma_init(void)
{
	return subsys_interface_register(&s3c2440_dma_interface);
}

arch_initcall(s3c2440_dma_init);
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/dma.c
98c418a0	2	*
c16f7bd8	3	* Copyright (c) 2006 Simtec Electronics
98c418a0 BD	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* S3C2440 DMA selection
	7	*
	8	* http://armlinux.simtec.co.uk/
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
4a858cfc	17	#include <linux/device.h>
b6d1f542	18	#include <linux/serial_core.h>
98c418a0	19
44dc9404	20	#include <mach/map.h>
a09e64fb	21	#include <mach/dma.h>
98c418a0	22
992426bf	23	#include <plat/dma-s3c24xx.h>
a2b7ba9c	24	#include <plat/cpu.h>
98c418a0	25
a2b7ba9c	26	#include <plat/regs-serial.h>
a09e64fb	27	#include <mach/regs-gpio.h>
f74c95c2	28	#include <plat/regs-ac97.h>
44dc9404	29	#include <plat/regs-dma.h>
a09e64fb RK	30	#include <mach/regs-mem.h>
	31	#include <mach/regs-lcd.h>
	32	#include <mach/regs-sdi.h>
8150bc88	33	#include <plat/regs-iis.h>
13622708	34	#include <plat/regs-spi.h>
98c418a0 BD	35
	36	static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
	37	[DMACH_XD0] = {
	38	.name = "xdreq0",
	39	.channels[0] = S3C2410_DCON_CH0_XDREQ0 \| DMA_CH_VALID,
	40	},
	41	[DMACH_XD1] = {
	42	.name = "xdreq1",
	43	.channels[1] = S3C2410_DCON_CH1_XDREQ1 \| DMA_CH_VALID,
	44	},
	45	[DMACH_SDI] = {
	46	.name = "sdi",
	47	.channels[0] = S3C2410_DCON_CH0_SDI \| DMA_CH_VALID,
	48	.channels[1] = S3C2440_DCON_CH1_SDI \| DMA_CH_VALID,
	49	.channels[2] = S3C2410_DCON_CH2_SDI \| DMA_CH_VALID,
	50	.channels[3] = S3C2410_DCON_CH3_SDI \| DMA_CH_VALID,
98c418a0 BD	51	},
	52	[DMACH_SPI0] = {
	53	.name = "spi0",
	54	.channels[1] = S3C2410_DCON_CH1_SPI \| DMA_CH_VALID,
98c418a0 BD	55	},
	56	[DMACH_SPI1] = {
	57	.name = "spi1",
	58	.channels[3] = S3C2410_DCON_CH3_SPI \| DMA_CH_VALID,
98c418a0 BD	59	},
	60	[DMACH_UART0] = {
	61	.name = "uart0",
	62	.channels[0] = S3C2410_DCON_CH0_UART0 \| DMA_CH_VALID,
98c418a0 BD	63	},
	64	[DMACH_UART1] = {
	65	.name = "uart1",
	66	.channels[1] = S3C2410_DCON_CH1_UART1 \| DMA_CH_VALID,
98c418a0 BD	67	},
	68	[DMACH_UART2] = {
	69	.name = "uart2",
	70	.channels[3] = S3C2410_DCON_CH3_UART2 \| DMA_CH_VALID,
98c418a0 BD	71	},
	72	[DMACH_TIMER] = {
	73	.name = "timer",
	74	.channels[0] = S3C2410_DCON_CH0_TIMER \| DMA_CH_VALID,
	75	.channels[2] = S3C2410_DCON_CH2_TIMER \| DMA_CH_VALID,
	76	.channels[3] = S3C2410_DCON_CH3_TIMER \| DMA_CH_VALID,
	77	},
	78	[DMACH_I2S_IN] = {
	79	.name = "i2s-sdi",
	80	.channels[1] = S3C2410_DCON_CH1_I2SSDI \| DMA_CH_VALID,
	81	.channels[2] = S3C2410_DCON_CH2_I2SSDI \| DMA_CH_VALID,
98c418a0 BD	82	},
	83	[DMACH_I2S_OUT] = {
	84	.name = "i2s-sdo",
	85	.channels[0] = S3C2440_DCON_CH0_I2SSDO \| DMA_CH_VALID,
	86	.channels[2] = S3C2410_DCON_CH2_I2SSDO \| DMA_CH_VALID,
98c418a0 BD	87	},
	88	[DMACH_PCM_IN] = {
	89	.name = "pcm-in",
	90	.channels[0] = S3C2440_DCON_CH0_PCMIN \| DMA_CH_VALID,
	91	.channels[2] = S3C2440_DCON_CH2_PCMIN \| DMA_CH_VALID,
98c418a0 BD	92	},
	93	[DMACH_PCM_OUT] = {
	94	.name = "pcm-out",
	95	.channels[1] = S3C2440_DCON_CH1_PCMOUT \| DMA_CH_VALID,
	96	.channels[3] = S3C2440_DCON_CH3_PCMOUT \| DMA_CH_VALID,
98c418a0 BD	97	},
	98	[DMACH_MIC_IN] = {
	99	.name = "mic-in",
	100	.channels[2] = S3C2440_DCON_CH2_MICIN \| DMA_CH_VALID,
	101	.channels[3] = S3C2440_DCON_CH3_MICIN \| DMA_CH_VALID,
98c418a0 BD	102	},
	103	[DMACH_USB_EP1] = {
	104	.name = "usb-ep1",
	105	.channels[0] = S3C2410_DCON_CH0_USBEP1 \| DMA_CH_VALID,
	106	},
	107	[DMACH_USB_EP2] = {
	108	.name = "usb-ep2",
	109	.channels[1] = S3C2410_DCON_CH1_USBEP2 \| DMA_CH_VALID,
	110	},
	111	[DMACH_USB_EP3] = {
	112	.name = "usb-ep3",
	113	.channels[2] = S3C2410_DCON_CH2_USBEP3 \| DMA_CH_VALID,
	114	},
	115	[DMACH_USB_EP4] = {
	116	.name = "usb-ep4",
	117	.channels[3] = S3C2410_DCON_CH3_USBEP4 \| DMA_CH_VALID,
	118	},
	119	};
	120
	121	static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
	122	struct s3c24xx_dma_map *map)
	123	{
	124	chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
	125	}
	126
	127	static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
	128	.select = s3c2440_dma_select,
	129	.dcon_mask = 7 << 24,
	130	.map = s3c2440_dma_mappings,
	131	.map_size = ARRAY_SIZE(s3c2440_dma_mappings),
	132	};
	133
bd65c82b BD	134	static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
	135	.channels = {
	136	[DMACH_SDI] = {
	137	.list = {
	138	[0] = 3 \| DMA_CH_VALID,
	139	[1] = 2 \| DMA_CH_VALID,
	140	[2] = 1 \| DMA_CH_VALID,
	141	[3] = 0 \| DMA_CH_VALID,
	142	},
	143	},
	144	[DMACH_I2S_IN] = {
	145	.list = {
	146	[0] = 1 \| DMA_CH_VALID,
	147	[1] = 2 \| DMA_CH_VALID,
	148	},
	149	},
	150	[DMACH_I2S_OUT] = {
	151	.list = {
	152	[0] = 2 \| DMA_CH_VALID,
	153	[1] = 1 \| DMA_CH_VALID,
	154	},
	155	},
	156	[DMACH_PCM_IN] = {
	157	.list = {
	158	[0] = 2 \| DMA_CH_VALID,
	159	[1] = 1 \| DMA_CH_VALID,
	160	},
	161	},
	162	[DMACH_PCM_OUT] = {
	163	.list = {
	164	[0] = 1 \| DMA_CH_VALID,
	165	[1] = 3 \| DMA_CH_VALID,
	166	},
	167	},
	168	[DMACH_MIC_IN] = {
	169	.list = {
	170	[0] = 3 \| DMA_CH_VALID,
	171	[1] = 2 \| DMA_CH_VALID,
	172	},
	173	},
	174	},
	175	};
	176
04511a6f HS	177	static int __init s3c2440_dma_add(struct device *dev,
04511a6f HS	178	struct subsys_interface *sif)
98c418a0	179	{
48adbcf3	180	s3c2410_dma_init();
bd65c82b	181	s3c24xx_dma_order_set(&s3c2440_dma_order);
98c418a0 BD	182	return s3c24xx_dma_init_map(&s3c2440_dma_sel);
	183	}
	184
4a858cfc KS	185	static struct subsys_interface s3c2440_dma_interface = {
	186	.name = "s3c2440_dma",
	187	.subsys = &s3c2440_subsys,
	188	.add_dev = s3c2440_dma_add,
98c418a0 BD	189	};
	190
	191	static int __init s3c2440_dma_init(void)
	192	{
4a858cfc	193	return subsys_interface_register(&s3c2440_dma_interface);
98c418a0 BD	194	}
	195
	196	arch_initcall(s3c2440_dma_init);
	197