projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| acf2d41d | 1 | /* |
| e02f8664 | 2 | * Copyright (c) 2006-2007 Simtec Electronics |
| 78278d6a BD |
3 | * http://armlinux.simtec.co.uk/ |
| 4 | * Ben Dooks <ben@simtec.co.uk> | |
| 5 | * Vincent Sanders <vince@arm.linux.org.uk> | |
| 6 | * | |
| 7 | * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal) | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | */ | |
| 13 | ||
| 14 | #include <linux/types.h> | |
| 15 | #include <linux/kernel.h> | |
| 4a858cfc | 16 | #include <linux/device.h> |
| 78278d6a BD |
17 | #include <linux/clk.h> |
| 18 | #include <linux/err.h> | |
| 19 | ||
| 20 | #include <plat/cpu.h> | |
| 21 | #include <plat/cpu-freq-core.h> | |
| 22 | ||
| da81593a | 23 | /* This array should be sorted in ascending order of the frequencies */ |
| 62f49ee2 | 24 | static struct cpufreq_frequency_table s3c2440_plls_12[] = { |
| 50701588 VK |
25 | { .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ |
| 26 | { .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ | |
| 27 | { .frequency = 90000000, .driver_data = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */ | |
| 28 | { .frequency = 100000000, .driver_data = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */ | |
| 29 | { .frequency = 110000000, .driver_data = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */ | |
| 30 | { .frequency = 120000000, .driver_data = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */ | |
| 31 | { .frequency = 150000000, .driver_data = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */ | |
| 32 | { .frequency = 160000000, .driver_data = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */ | |
| 33 | { .frequency = 170000000, .driver_data = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */ | |
| 34 | { .frequency = 180000000, .driver_data = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */ | |
| 35 | { .frequency = 190000000, .driver_data = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */ | |
| 36 | { .frequency = 200000000, .driver_data = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */ | |
| 37 | { .frequency = 210000000, .driver_data = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */ | |
| 38 | { .frequency = 220000000, .driver_data = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */ | |
| 39 | { .frequency = 230000000, .driver_data = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */ | |
| 40 | { .frequency = 240000000, .driver_data = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */ | |
| 41 | { .frequency = 300000000, .driver_data = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */ | |
| 42 | { .frequency = 310000000, .driver_data = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */ | |
| 43 | { .frequency = 320000000, .driver_data = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */ | |
| 44 | { .frequency = 330000000, .driver_data = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */ | |
| 45 | { .frequency = 340000000, .driver_data = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */ | |
| 46 | { .frequency = 350000000, .driver_data = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */ | |
| 47 | { .frequency = 360000000, .driver_data = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */ | |
| 48 | { .frequency = 370000000, .driver_data = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */ | |
| 49 | { .frequency = 380000000, .driver_data = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */ | |
| 50 | { .frequency = 390000000, .driver_data = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */ | |
| 51 | { .frequency = 400000000, .driver_data = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ | |
| 78278d6a BD |
52 | }; |
| 53 | ||
| 04511a6f | 54 | static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif) |
| 78278d6a BD |
55 | { |
| 56 | struct clk *xtal_clk; | |
| 57 | unsigned long xtal; | |
| 58 | ||
| 59 | xtal_clk = clk_get(NULL, "xtal"); | |
| 60 | if (IS_ERR(xtal_clk)) | |
| 61 | return PTR_ERR(xtal_clk); | |
| 62 | ||
| 63 | xtal = clk_get_rate(xtal_clk); | |
| 64 | clk_put(xtal_clk); | |
| 65 | ||
| 66 | if (xtal == 12000000) { | |
| 67 | printk(KERN_INFO "Using PLL table for 12MHz crystal\n"); | |
| 68 | return s3c_plltab_register(s3c2440_plls_12, | |
| 69 | ARRAY_SIZE(s3c2440_plls_12)); | |
| 70 | } | |
| 71 | ||
| 72 | return 0; | |
| 73 | } | |
| 74 | ||
| 4a858cfc KS |
75 | static struct subsys_interface s3c2440_plls12_interface = { |
| 76 | .name = "s3c2440_plls12", | |
| 77 | .subsys = &s3c2440_subsys, | |
| 78 | .add_dev = s3c2440_plls12_add, | |
| 78278d6a BD |
79 | }; |
| 80 | ||
| 81 | static int __init s3c2440_pll_12mhz(void) | |
| 82 | { | |
| 4a858cfc | 83 | return subsys_interface_register(&s3c2440_plls12_interface); |
| 78278d6a BD |
84 | |
| 85 | } | |
| 78278d6a BD |
86 | arch_initcall(s3c2440_pll_12mhz); |
| 87 | ||
| 4a858cfc KS |
88 | static struct subsys_interface s3c2442_plls12_interface = { |
| 89 | .name = "s3c2442_plls12", | |
| 90 | .subsys = &s3c2442_subsys, | |
| 91 | .add_dev = s3c2440_plls12_add, | |
| 78278d6a BD |
92 | }; |
| 93 | ||
| 94 | static int __init s3c2442_pll_12mhz(void) | |
| 95 | { | |
| 4a858cfc | 96 | return subsys_interface_register(&s3c2442_plls12_interface); |
| 78278d6a BD |
97 | |
| 98 | } | |
| 78278d6a | 99 | arch_initcall(s3c2442_pll_12mhz); |