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1 | /* linux/arch/arm/plat-s3c64xx/cpufreq.c |
2 | * | |
3 | * Copyright 2009 Wolfson Microelectronics plc | |
4 | * | |
5 | * S3C64xx CPUfreq Support | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/cpufreq.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/regulator/consumer.h> | |
19 | ||
20 | static struct clk *armclk; | |
21 | static struct regulator *vddarm; | |
43f1069e | 22 | static unsigned long regulator_latency; |
b3748ddd MB |
23 | |
24 | #ifdef CONFIG_CPU_S3C6410 | |
25 | struct s3c64xx_dvfs { | |
26 | unsigned int vddarm_min; | |
27 | unsigned int vddarm_max; | |
28 | }; | |
29 | ||
30 | static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { | |
e9c08f0d MB |
31 | [0] = { 1000000, 1150000 }, |
32 | [1] = { 1050000, 1150000 }, | |
33 | [2] = { 1100000, 1150000 }, | |
34 | [3] = { 1200000, 1350000 }, | |
b3748ddd MB |
35 | }; |
36 | ||
37 | static struct cpufreq_frequency_table s3c64xx_freq_table[] = { | |
38 | { 0, 66000 }, | |
39 | { 0, 133000 }, | |
40 | { 1, 222000 }, | |
41 | { 1, 266000 }, | |
42 | { 2, 333000 }, | |
43 | { 2, 400000 }, | |
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44 | { 2, 532000 }, |
45 | { 2, 533000 }, | |
46 | { 3, 667000 }, | |
b3748ddd MB |
47 | { 0, CPUFREQ_TABLE_END }, |
48 | }; | |
49 | #endif | |
50 | ||
51 | static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy) | |
52 | { | |
53 | if (policy->cpu != 0) | |
54 | return -EINVAL; | |
55 | ||
56 | return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table); | |
57 | } | |
58 | ||
59 | static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu) | |
60 | { | |
61 | if (cpu != 0) | |
62 | return 0; | |
63 | ||
64 | return clk_get_rate(armclk) / 1000; | |
65 | } | |
66 | ||
67 | static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, | |
68 | unsigned int target_freq, | |
69 | unsigned int relation) | |
70 | { | |
71 | int ret; | |
72 | unsigned int i; | |
73 | struct cpufreq_freqs freqs; | |
74 | struct s3c64xx_dvfs *dvfs; | |
75 | ||
76 | ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table, | |
77 | target_freq, relation, &i); | |
78 | if (ret != 0) | |
79 | return ret; | |
80 | ||
81 | freqs.cpu = 0; | |
82 | freqs.old = clk_get_rate(armclk) / 1000; | |
83 | freqs.new = s3c64xx_freq_table[i].frequency; | |
84 | freqs.flags = 0; | |
85 | dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index]; | |
86 | ||
87 | if (freqs.old == freqs.new) | |
88 | return 0; | |
89 | ||
90 | pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new); | |
91 | ||
92 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
93 | ||
94 | #ifdef CONFIG_REGULATOR | |
95 | if (vddarm && freqs.new > freqs.old) { | |
96 | ret = regulator_set_voltage(vddarm, | |
97 | dvfs->vddarm_min, | |
98 | dvfs->vddarm_max); | |
99 | if (ret != 0) { | |
100 | pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", | |
101 | freqs.new, ret); | |
102 | goto err; | |
103 | } | |
104 | } | |
105 | #endif | |
106 | ||
107 | ret = clk_set_rate(armclk, freqs.new * 1000); | |
108 | if (ret < 0) { | |
109 | pr_err("cpufreq: Failed to set rate %dkHz: %d\n", | |
110 | freqs.new, ret); | |
111 | goto err; | |
112 | } | |
113 | ||
114 | #ifdef CONFIG_REGULATOR | |
115 | if (vddarm && freqs.new < freqs.old) { | |
116 | ret = regulator_set_voltage(vddarm, | |
117 | dvfs->vddarm_min, | |
118 | dvfs->vddarm_max); | |
119 | if (ret != 0) { | |
120 | pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", | |
121 | freqs.new, ret); | |
122 | goto err_clk; | |
123 | } | |
124 | } | |
125 | #endif | |
126 | ||
127 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
128 | ||
129 | pr_debug("cpufreq: Set actual frequency %lukHz\n", | |
130 | clk_get_rate(armclk) / 1000); | |
131 | ||
132 | return 0; | |
133 | ||
134 | err_clk: | |
135 | if (clk_set_rate(armclk, freqs.old * 1000) < 0) | |
136 | pr_err("Failed to restore original clock rate\n"); | |
137 | err: | |
138 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
139 | ||
140 | return ret; | |
141 | } | |
142 | ||
143 | #ifdef CONFIG_REGULATOR | |
43f1069e | 144 | static void __init s3c64xx_cpufreq_config_regulator(void) |
b3748ddd MB |
145 | { |
146 | int count, v, i, found; | |
147 | struct cpufreq_frequency_table *freq; | |
148 | struct s3c64xx_dvfs *dvfs; | |
149 | ||
150 | count = regulator_count_voltages(vddarm); | |
151 | if (count < 0) { | |
152 | pr_err("cpufreq: Unable to check supported voltages\n"); | |
b3748ddd MB |
153 | } |
154 | ||
155 | freq = s3c64xx_freq_table; | |
43f1069e | 156 | while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) { |
b3748ddd MB |
157 | if (freq->frequency == CPUFREQ_ENTRY_INVALID) |
158 | continue; | |
159 | ||
160 | dvfs = &s3c64xx_dvfs_table[freq->index]; | |
161 | found = 0; | |
162 | ||
163 | for (i = 0; i < count; i++) { | |
164 | v = regulator_list_voltage(vddarm, i); | |
165 | if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) | |
166 | found = 1; | |
167 | } | |
168 | ||
169 | if (!found) { | |
170 | pr_debug("cpufreq: %dkHz unsupported by regulator\n", | |
171 | freq->frequency); | |
172 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
173 | } | |
174 | ||
175 | freq++; | |
176 | } | |
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177 | |
178 | /* Guess based on having to do an I2C/SPI write; in future we | |
179 | * will be able to query the regulator performance here. */ | |
180 | regulator_latency = 1 * 1000 * 1000; | |
b3748ddd MB |
181 | } |
182 | #endif | |
183 | ||
184 | static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) | |
185 | { | |
186 | int ret; | |
187 | struct cpufreq_frequency_table *freq; | |
188 | ||
189 | if (policy->cpu != 0) | |
190 | return -EINVAL; | |
191 | ||
192 | if (s3c64xx_freq_table == NULL) { | |
193 | pr_err("cpufreq: No frequency information for this CPU\n"); | |
194 | return -ENODEV; | |
195 | } | |
196 | ||
197 | armclk = clk_get(NULL, "armclk"); | |
198 | if (IS_ERR(armclk)) { | |
199 | pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n", | |
200 | PTR_ERR(armclk)); | |
201 | return PTR_ERR(armclk); | |
202 | } | |
203 | ||
204 | #ifdef CONFIG_REGULATOR | |
205 | vddarm = regulator_get(NULL, "vddarm"); | |
206 | if (IS_ERR(vddarm)) { | |
207 | ret = PTR_ERR(vddarm); | |
208 | pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret); | |
209 | pr_err("cpufreq: Only frequency scaling available\n"); | |
210 | vddarm = NULL; | |
211 | } else { | |
43f1069e | 212 | s3c64xx_cpufreq_config_regulator(); |
b3748ddd MB |
213 | } |
214 | #endif | |
215 | ||
216 | freq = s3c64xx_freq_table; | |
217 | while (freq->frequency != CPUFREQ_TABLE_END) { | |
218 | unsigned long r; | |
219 | ||
220 | /* Check for frequencies we can generate */ | |
221 | r = clk_round_rate(armclk, freq->frequency * 1000); | |
222 | r /= 1000; | |
383af9c2 MB |
223 | if (r != freq->frequency) { |
224 | pr_debug("cpufreq: %dkHz unsupported by clock\n", | |
225 | freq->frequency); | |
b3748ddd | 226 | freq->frequency = CPUFREQ_ENTRY_INVALID; |
383af9c2 | 227 | } |
b3748ddd MB |
228 | |
229 | /* If we have no regulator then assume startup | |
230 | * frequency is the maximum we can support. */ | |
231 | if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0)) | |
232 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
233 | ||
234 | freq++; | |
235 | } | |
236 | ||
237 | policy->cur = clk_get_rate(armclk) / 1000; | |
238 | ||
43f1069e MB |
239 | /* Datasheet says PLL stabalisation time (if we were to use |
240 | * the PLLs, which we don't currently) is ~300us worst case, | |
241 | * but add some fudge. | |
242 | */ | |
243 | policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency; | |
b3748ddd MB |
244 | |
245 | ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table); | |
246 | if (ret != 0) { | |
247 | pr_err("cpufreq: Failed to configure frequency table: %d\n", | |
248 | ret); | |
249 | regulator_put(vddarm); | |
250 | clk_put(armclk); | |
251 | } | |
252 | ||
253 | return ret; | |
254 | } | |
255 | ||
256 | static struct cpufreq_driver s3c64xx_cpufreq_driver = { | |
257 | .owner = THIS_MODULE, | |
258 | .flags = 0, | |
259 | .verify = s3c64xx_cpufreq_verify_speed, | |
260 | .target = s3c64xx_cpufreq_set_target, | |
261 | .get = s3c64xx_cpufreq_get_speed, | |
262 | .init = s3c64xx_cpufreq_driver_init, | |
263 | .name = "s3c", | |
264 | }; | |
265 | ||
266 | static int __init s3c64xx_cpufreq_init(void) | |
267 | { | |
268 | return cpufreq_register_driver(&s3c64xx_cpufreq_driver); | |
269 | } | |
270 | module_init(s3c64xx_cpufreq_init); |