projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 431fb7df | 1 | /* linux/arch/arm/mach-s3c64xx/include/mach/pm-core.h |
| bd117bd1 BD |
2 | * |
| 3 | * Copyright 2008 Openmoko, Inc. | |
| 4 | * Copyright 2008 Simtec Electronics | |
| 5 | * Ben Dooks <ben@simtec.co.uk> | |
| 6 | * http://armlinux.simtec.co.uk/ | |
| 7 | * | |
| 8 | * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License version 2 as | |
| 12 | * published by the Free Software Foundation. | |
| 13 | */ | |
| 14 | ||
| 42be66f8 SK |
15 | #ifndef __MACH_S3C64XX_PM_CORE_H |
| 16 | #define __MACH_S3C64XX_PM_CORE_H __FILE__ | |
| 17 | ||
| 3501c9ae | 18 | #include <mach/regs-gpio.h> |
| bd117bd1 BD |
19 | |
| 20 | static inline void s3c_pm_debug_init_uart(void) | |
| 21 | { | |
| 22 | u32 tmp = __raw_readl(S3C_PCLK_GATE); | |
| 23 | ||
| 24 | /* As a note, since the S3C64XX UARTs generally have multiple | |
| 25 | * clock sources, we simply enable PCLK at the moment and hope | |
| 26 | * that the resume settings for the UART are suitable for the | |
| 27 | * use with PCLK. | |
| 28 | */ | |
| 29 | ||
| 30 | tmp |= S3C_CLKCON_PCLK_UART0; | |
| 31 | tmp |= S3C_CLKCON_PCLK_UART1; | |
| 32 | tmp |= S3C_CLKCON_PCLK_UART2; | |
| 33 | tmp |= S3C_CLKCON_PCLK_UART3; | |
| 34 | ||
| 35 | __raw_writel(tmp, S3C_PCLK_GATE); | |
| 36 | udelay(10); | |
| 37 | } | |
| 38 | ||
| 39 | static inline void s3c_pm_arch_prepare_irqs(void) | |
| 40 | { | |
| 41 | /* VIC should have already been taken care of */ | |
| 42 | ||
| 43 | /* clear any pending EINT0 interrupts */ | |
| 44 | __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); | |
| 45 | } | |
| 46 | ||
| 47 | static inline void s3c_pm_arch_stop_clocks(void) | |
| 48 | { | |
| 49 | } | |
| 50 | ||
| 51 | static inline void s3c_pm_arch_show_resume_irqs(void) | |
| 52 | { | |
| 53 | } | |
| 54 | ||
| 55 | /* make these defines, we currently do not have any need to change | |
| 56 | * the IRQ wake controls depending on the CPU we are running on */ | |
| 57 | ||
| 58 | #define s3c_irqwake_eintallow ((1 << 28) - 1) | |
| c17afc0a | 59 | #define s3c_irqwake_intallow (~0) |
| bd117bd1 BD |
60 | |
| 61 | static inline void s3c_pm_arch_update_uart(void __iomem *regs, | |
| 62 | struct pm_uart_save *save) | |
| 63 | { | |
| 64 | u32 ucon = __raw_readl(regs + S3C2410_UCON); | |
| 65 | u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; | |
| 66 | u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; | |
| 67 | u32 new_ucon; | |
| 68 | u32 delta; | |
| 69 | ||
| 70 | /* S3C64XX UART blocks only support level interrupts, so ensure that | |
| 71 | * when we restore unused UART blocks we force the level interrupt | |
| 72 | * settigs. */ | |
| 73 | save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; | |
| 74 | ||
| 75 | /* We have a constraint on changing the clock type of the UART | |
| 76 | * between UCLKx and PCLK, so ensure that when we restore UCON | |
| 77 | * that the CLK field is correctly modified if the bootloader | |
| 78 | * has changed anything. | |
| 79 | */ | |
| 80 | if (ucon_clk != save_clk) { | |
| 81 | new_ucon = save->ucon; | |
| 82 | delta = ucon_clk ^ save_clk; | |
| 83 | ||
| 84 | /* change from UCLKx => wrong PCLK, | |
| 85 | * either UCLK can be tested for by a bit-test | |
| 86 | * with UCLK0 */ | |
| 87 | if (ucon_clk & S3C6400_UCON_UCLK0 && | |
| 88 | !(save_clk & S3C6400_UCON_UCLK0) && | |
| 89 | delta & S3C6400_UCON_PCLK2) { | |
| 90 | new_ucon &= ~S3C6400_UCON_UCLK0; | |
| 91 | } else if (delta == S3C6400_UCON_PCLK2) { | |
| 92 | /* as an precaution, don't change from | |
| 93 | * PCLK2 => PCLK or vice-versa */ | |
| 94 | new_ucon ^= S3C6400_UCON_PCLK2; | |
| 95 | } | |
| 96 | ||
| 97 | S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", | |
| 98 | ucon, new_ucon, save->ucon); | |
| 99 | save->ucon = new_ucon; | |
| 100 | } | |
| 101 | } | |
| 1bac282a BD |
102 | |
| 103 | static inline void s3c_pm_restored_gpios(void) | |
| 104 | { | |
| 105 | /* ensure sleep mode has been cleared from the system */ | |
| 106 | ||
| 107 | __raw_writel(0, S3C64XX_SLPEN); | |
| 108 | } | |
| 109 | ||
| 782d8a3c | 110 | static inline void samsung_pm_saved_gpios(void) |
| 1bac282a BD |
111 | { |
| 112 | /* turn on the sleep mode and keep it there, as it seems that during | |
| 113 | * suspend the xCON registers get re-set and thus you can end up with | |
| 114 | * problems between going to sleep and resuming. | |
| 115 | */ | |
| 116 | ||
| 117 | __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); | |
| 118 | } | |
| 42be66f8 | 119 | #endif /* __MACH_S3C64XX_PM_CORE_H */ |