projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d9b79fb5 BD |
1 | /* arch/arm/plat-s3c64xx/irq.c |
| 2 | * | |
| 3 | * Copyright 2008 Openmoko, Inc. | |
| 4 | * Copyright 2008 Simtec Electronics | |
| 5 | * Ben Dooks <ben@simtec.co.uk> | |
| 6 | * http://armlinux.simtec.co.uk/ | |
| 7 | * | |
| 8 | * S3C64XX - Interrupt handling | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License version 2 as | |
| 12 | * published by the Free Software Foundation. | |
| 13 | */ | |
| 14 | ||
| 15 | #include <linux/kernel.h> | |
| 16 | #include <linux/interrupt.h> | |
| 966bcc14 | 17 | #include <linux/serial_core.h> |
| f982dc53 | 18 | #include <linux/irq.h> |
| d9b79fb5 BD |
19 | #include <linux/io.h> |
| 20 | ||
| 21 | #include <asm/hardware/vic.h> | |
| d9b79fb5 BD |
22 | |
| 23 | #include <mach/map.h> | |
| 7162ba03 | 24 | #include <plat/irq-vic-timer.h> |
| 51022cf6 | 25 | #include <plat/irq-uart.h> |
| d9b79fb5 BD |
26 | #include <plat/cpu.h> |
| 27 | ||
| 51022cf6 | 28 | static struct s3c_uart_irq uart_irqs[] = { |
| 3e694d4b BD |
29 | [0] = { |
| 30 | .regs = S3C_VA_UART0, | |
| 31 | .base_irq = IRQ_S3CUART_BASE0, | |
| 32 | .parent_irq = IRQ_UART0, | |
| 33 | }, | |
| 34 | [1] = { | |
| 35 | .regs = S3C_VA_UART1, | |
| 36 | .base_irq = IRQ_S3CUART_BASE1, | |
| 37 | .parent_irq = IRQ_UART1, | |
| 38 | }, | |
| 39 | [2] = { | |
| 40 | .regs = S3C_VA_UART2, | |
| 41 | .base_irq = IRQ_S3CUART_BASE2, | |
| 42 | .parent_irq = IRQ_UART2, | |
| 43 | }, | |
| 44 | [3] = { | |
| 45 | .regs = S3C_VA_UART3, | |
| 46 | .base_irq = IRQ_S3CUART_BASE3, | |
| 47 | .parent_irq = IRQ_UART3, | |
| 48 | }, | |
| 49 | }; | |
| 50 | ||
| 3e694d4b | 51 | |
| d9b79fb5 BD |
52 | void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) |
| 53 | { | |
| 39669f59 | 54 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); |
| d9b79fb5 BD |
55 | |
| 56 | /* initialise the pair of VICs */ | |
| 5b39be46 BD |
57 | vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); |
| 58 | vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); | |
| f982dc53 BD |
59 | |
| 60 | /* add the timer sub-irqs */ | |
| 61 | ||
| 7162ba03 BD |
62 | s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); |
| 63 | s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); | |
| 64 | s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); | |
| 65 | s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); | |
| 66 | s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); | |
| 3e694d4b | 67 | |
| 51022cf6 | 68 | s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); |
| d9b79fb5 | 69 | } |