[deliverable/linux.git] / arch / arm / mach-s3c64xx / mach-anw6410.c

/* linux/arch/arm/mach-s3c64xx/mach-anw6410.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 * Copyright 2009 Kwangwoo Lee
 * 	Kwangwoo Lee <kwangwoo.lee@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/dm9000.h>

#include <video/platform_lcd.h>
#include <video/samsung_fimd.h>

#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/hardware.h>
#include <mach/map.h>

#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/regs-serial.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/fb.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>

#include "common.h"

/* DM9000 */
#define ANW6410_PA_DM9000	(0x18000000)

/* A hardware buffer to control external devices is mapped at 0x30000000.
 * It can not be read. So current status must be kept in anw6410_extdev_status.
 */
#define ANW6410_VA_EXTDEV	S3C_ADDR(0x02000000)
#define ANW6410_PA_EXTDEV	(0x30000000)

#define ANW6410_EN_DM9000	(1<<11)
#define ANW6410_EN_LCD		(1<<14)

static __u32 anw6410_extdev_status;

static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = 0x3c5,
		.ulcon	     = 0x03,
		.ufcon	     = 0x51,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = 0x3c5,
		.ulcon	     = 0x03,
		.ufcon	     = 0x51,
	},
};

/* framebuffer and LCD setup. */
static void __init anw6410_lcd_mode_set(void)
{
	u32 tmp;

	/* set the LCD type */
	tmp = __raw_readl(S3C64XX_SPCON);
	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
	__raw_writel(tmp, S3C64XX_SPCON);

	/* remove the LCD bypass */
	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	tmp &= ~MIFPCON_LCD_BYPASS;
	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}

/* GPF1 = LCD panel power
 * GPF4 = LCD backlight control
 */
static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
				   unsigned int power)
{
	if (power) {
		anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
		__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);

		gpio_direction_output(S3C64XX_GPF(1), 1);
		gpio_direction_output(S3C64XX_GPF(4), 1);
	} else {
		anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
		__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);

		gpio_direction_output(S3C64XX_GPF(1), 0);
		gpio_direction_output(S3C64XX_GPF(4), 0);
	}
}

static struct plat_lcd_data anw6410_lcd_power_data = {
	.set_power	= anw6410_lcd_power_set,
};

static struct platform_device anw6410_lcd_powerdev = {
	.name			= "platform-lcd",
	.dev.parent		= &s3c_device_fb.dev,
	.dev.platform_data	= &anw6410_lcd_power_data,
};

static struct s3c_fb_pd_win anw6410_fb_win0 = {
	.max_bpp	= 32,
	.default_bpp	= 16,
	.xres		= 800,
	.yres		= 480,
};

static struct fb_videomode anw6410_lcd_timing = {
	.left_margin	= 8,
	.right_margin	= 13,
	.upper_margin	= 7,
	.lower_margin	= 5,
	.hsync_len	= 3,
	.vsync_len	= 1,
	.xres		= 800,
	.yres		= 480,
};

/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
	.vtiming	= &anw6410_lcd_timing,
	.win[0]		= &anw6410_fb_win0,
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};

/* DM9000AEP 10/100 ethernet controller */
static void __init anw6410_dm9000_enable(void)
{
	anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
	__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
}

static struct resource anw6410_dm9000_resource[] = {
	[0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4),
	[1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501),
	[2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \
					| IRQF_TRIGGER_HIGH),
};

static struct dm9000_plat_data anw6410_dm9000_pdata = {
	.flags	  = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
	/* dev_addr can be set to provide hwaddr. */
};

static struct platform_device anw6410_device_eth = {
	.name	= "dm9000",
	.id	= -1,
	.num_resources	= ARRAY_SIZE(anw6410_dm9000_resource),
	.resource	= anw6410_dm9000_resource,
	.dev	= {
		.platform_data  = &anw6410_dm9000_pdata,
	},
};

static struct map_desc anw6410_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)ANW6410_VA_EXTDEV,
		.pfn		= __phys_to_pfn(ANW6410_PA_EXTDEV),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	},
};

static struct platform_device *anw6410_devices[] __initdata = {
	&s3c_device_fb,
	&anw6410_lcd_powerdev,
	&anw6410_device_eth,
};

static void __init anw6410_map_io(void)
{
	s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
	s3c24xx_init_clocks(12000000);
	s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));

	anw6410_lcd_mode_set();
}

static void __init anw6410_machine_init(void)
{
	s3c_fb_set_platdata(&anw6410_lcd_pdata);

	gpio_request(S3C64XX_GPF(1), "panel power");
	gpio_request(S3C64XX_GPF(4), "LCD backlight");

	anw6410_dm9000_enable();

	platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
}

MACHINE_START(ANW6410, "A&W6410")
	/* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
	.atag_offset	= 0x100,

	.init_irq	= s3c6410_init_irq,
	.map_io		= anw6410_map_io,
	.init_machine	= anw6410_machine_init,
	.init_late	= s3c64xx_init_late,
	.timer		= &s3c24xx_timer,
	.restart	= s3c64xx_restart,
MACHINE_END
Commit	Line	Data
431107ea	1	/* linux/arch/arm/mach-s3c64xx/mach-anw6410.c
1f26a8a0 KL	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	* Copyright 2009 Kwangwoo Lee
	8	* Kwangwoo Lee <kwangwoo.lee@gmail.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/types.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/list.h>
	20	#include <linux/timer.h>
	21	#include <linux/init.h>
	22	#include <linux/serial_core.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/io.h>
	25	#include <linux/i2c.h>
	26	#include <linux/fb.h>
	27	#include <linux/gpio.h>
	28	#include <linux/delay.h>
	29	#include <linux/dm9000.h>
	30
	31	#include <video/platform_lcd.h>
5a213a55	32	#include <video/samsung_fimd.h>
1f26a8a0	33
774b51f8	34	#include <asm/hardware/vic.h>
1f26a8a0 KL	35	#include <asm/mach/arch.h>
	36	#include <asm/mach/map.h>
	37	#include <asm/mach/irq.h>
	38
	39	#include <mach/hardware.h>
1f26a8a0 KL	40	#include <mach/map.h>
	41
	42	#include <asm/irq.h>
	43	#include <asm/mach-types.h>
	44
	45	#include <plat/regs-serial.h>
436d42c6	46	#include <linux/platform_data/i2c-s3c2410.h>
1f26a8a0 KL	47	#include <plat/fb.h>
1f26a8a0 KL	48
1f26a8a0 KL	49	#include <plat/clock.h>
	50	#include <plat/devs.h>
	51	#include <plat/cpu.h>
3501c9ae BD	52	#include <mach/regs-gpio.h>
3501c9ae BD	53	#include <mach/regs-modem.h>
1f26a8a0	54
b024043b KK	55	#include "common.h"
b024043b KK	56
1f26a8a0 KL	57	/* DM9000 */
	58	#define ANW6410_PA_DM9000 (0x18000000)
	59
	60	/* A hardware buffer to control external devices is mapped at 0x30000000.
	61	* It can not be read. So current status must be kept in anw6410_extdev_status.
	62	*/
	63	#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
	64	#define ANW6410_PA_EXTDEV (0x30000000)
	65
	66	#define ANW6410_EN_DM9000 (1<<11)
	67	#define ANW6410_EN_LCD (1<<14)
	68
	69	static __u32 anw6410_extdev_status;
	70
	71	static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
	72	[0] = {
	73	.hwport = 0,
	74	.flags = 0,
	75	.ucon = 0x3c5,
	76	.ulcon = 0x03,
	77	.ufcon = 0x51,
	78	},
	79	[1] = {
	80	.hwport = 1,
	81	.flags = 0,
	82	.ucon = 0x3c5,
	83	.ulcon = 0x03,
	84	.ufcon = 0x51,
	85	},
	86	};
	87
	88	/* framebuffer and LCD setup. */
	89	static void __init anw6410_lcd_mode_set(void)
	90	{
	91	u32 tmp;
	92
	93	/* set the LCD type */
	94	tmp = __raw_readl(S3C64XX_SPCON);
	95	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
	96	tmp \|= S3C64XX_SPCON_LCD_SEL_RGB;
	97	__raw_writel(tmp, S3C64XX_SPCON);
	98
	99	/* remove the LCD bypass */
	100	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
	101	tmp &= ~MIFPCON_LCD_BYPASS;
	102	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
	103	}
	104
	105	/* GPF1 = LCD panel power
	106	* GPF4 = LCD backlight control
	107	*/
	108	static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
	109	unsigned int power)
	110	{
	111	if (power) {
	112	anw6410_extdev_status \|= (ANW6410_EN_LCD << 16);
	113	__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
	114
	115	gpio_direction_output(S3C64XX_GPF(1), 1);
	116	gpio_direction_output(S3C64XX_GPF(4), 1);
	117	} else {
	118	anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
	119	__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
	120
121	gpio_direction_output(S3C64XX_GPF(1), 0);
122	gpio_direction_output(S3C64XX_GPF(4), 0);
123	}
124	}
125
126	static struct plat_lcd_data anw6410_lcd_power_data = {
127	.set_power = anw6410_lcd_power_set,
128	};
129
130	static struct platform_device anw6410_lcd_powerdev = {
131	.name = "platform-lcd",
132	.dev.parent = &s3c_device_fb.dev,
133	.dev.platform_data = &anw6410_lcd_power_data,
134	};
135
136	static struct s3c_fb_pd_win anw6410_fb_win0 = {
1f26a8a0 KL	137	.max_bpp = 32,
1f26a8a0 KL	138	.default_bpp = 16,
79d3c41a TA	139	.xres = 800,
	140	.yres = 480,
	141	};
	142
	143	static struct fb_videomode anw6410_lcd_timing = {
	144	.left_margin = 8,
	145	.right_margin = 13,
	146	.upper_margin = 7,
	147	.lower_margin = 5,
	148	.hsync_len = 3,
	149	.vsync_len = 1,
	150	.xres = 800,
	151	.yres = 480,
1f26a8a0 KL	152	};
	153
	154	/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
	155	static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
	156	.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
79d3c41a	157	.vtiming = &anw6410_lcd_timing,
1f26a8a0 KL	158	.win[0] = &anw6410_fb_win0,
	159	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	160	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	161	};
	162
	163	/* DM9000AEP 10/100 ethernet controller */
	164	static void __init anw6410_dm9000_enable(void)
	165	{
	166	anw6410_extdev_status \|= (ANW6410_EN_DM9000 << 16);
	167	__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
	168	}
	169
	170	static struct resource anw6410_dm9000_resource[] = {
178e7126 TB	171	[0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4),
	172	[1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501),
	173	[2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \
	174	\| IRQF_TRIGGER_HIGH),
1f26a8a0 KL	175	};
	176
	177	static struct dm9000_plat_data anw6410_dm9000_pdata = {
	178	.flags = (DM9000_PLATF_16BITONLY \| DM9000_PLATF_NO_EEPROM),
	179	/* dev_addr can be set to provide hwaddr. */
	180	};
	181
	182	static struct platform_device anw6410_device_eth = {
	183	.name = "dm9000",
	184	.id = -1,
	185	.num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
	186	.resource = anw6410_dm9000_resource,
	187	.dev = {
	188	.platform_data = &anw6410_dm9000_pdata,
	189	},
	190	};
	191
	192	static struct map_desc anw6410_iodesc[] __initdata = {
	193	{
	194	.virtual = (unsigned long)ANW6410_VA_EXTDEV,
	195	.pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
	196	.length = SZ_64K,
	197	.type = MT_DEVICE,
	198	},
	199	};
	200
	201	static struct platform_device *anw6410_devices[] __initdata = {
	202	&s3c_device_fb,
	203	&anw6410_lcd_powerdev,
	204	&anw6410_device_eth,
	205	};
	206
	207	static void __init anw6410_map_io(void)
	208	{
	209	s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
	210	s3c24xx_init_clocks(12000000);
	211	s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
	212
	213	anw6410_lcd_mode_set();
	214	}
	215
	216	static void __init anw6410_machine_init(void)
	217	{
	218	s3c_fb_set_platdata(&anw6410_lcd_pdata);
	219
	220	gpio_request(S3C64XX_GPF(1), "panel power");
	221	gpio_request(S3C64XX_GPF(4), "LCD backlight");
	222
	223	anw6410_dm9000_enable();
	224
	225	platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
	226	}
	227
	228	MACHINE_START(ANW6410, "A&W6410")
	229	/* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
170a5908	230	.atag_offset = 0x100,
1f26a8a0 KL	231
	232	.init_irq = s3c6410_init_irq,
	233	.map_io = anw6410_map_io,
	234	.init_machine = anw6410_machine_init,
cc8f252b	235	.init_late = s3c64xx_init_late,
1f26a8a0	236	.timer = &s3c24xx_timer,
ff84ded2	237	.restart = s3c64xx_restart,
1f26a8a0	238	MACHINE_END