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a443a637 TA |
1 | /* linux/arch/arm/mach-s5pc100/clock.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5PC100 - Clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/io.h> | |
20 | ||
21 | #include <mach/map.h> | |
22 | ||
23 | #include <plat/cpu-freq.h> | |
24 | #include <mach/regs-clock.h> | |
25 | #include <plat/clock.h> | |
26 | #include <plat/cpu.h> | |
27 | #include <plat/pll.h> | |
28 | #include <plat/s5p-clock.h> | |
29 | #include <plat/clock-clksrc.h> | |
30 | #include <plat/s5pc100.h> | |
31 | ||
32 | static struct clk s5p_clk_otgphy = { | |
33 | .name = "otg_phy", | |
34 | .id = -1, | |
35 | }; | |
36 | ||
37 | static struct clk *clk_src_mout_href_list[] = { | |
38 | [0] = &s5p_clk_27m, | |
39 | [1] = &clk_fin_hpll, | |
40 | }; | |
41 | ||
42 | static struct clksrc_sources clk_src_mout_href = { | |
43 | .sources = clk_src_mout_href_list, | |
44 | .nr_sources = ARRAY_SIZE(clk_src_mout_href_list), | |
45 | }; | |
46 | ||
47 | static struct clksrc_clk clk_mout_href = { | |
48 | .clk = { | |
49 | .name = "mout_href", | |
50 | .id = -1, | |
51 | }, | |
52 | .sources = &clk_src_mout_href, | |
53 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | |
54 | }; | |
55 | ||
56 | static struct clk *clk_src_mout_48m_list[] = { | |
57 | [0] = &clk_xusbxti, | |
58 | [1] = &s5p_clk_otgphy, | |
59 | }; | |
60 | ||
61 | static struct clksrc_sources clk_src_mout_48m = { | |
62 | .sources = clk_src_mout_48m_list, | |
63 | .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list), | |
64 | }; | |
65 | ||
66 | static struct clksrc_clk clk_mout_48m = { | |
67 | .clk = { | |
68 | .name = "mout_48m", | |
69 | .id = -1, | |
70 | }, | |
71 | .sources = &clk_src_mout_48m, | |
72 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, | |
73 | }; | |
74 | ||
75 | static struct clksrc_clk clk_mout_mpll = { | |
76 | .clk = { | |
77 | .name = "mout_mpll", | |
78 | .id = -1, | |
79 | }, | |
80 | .sources = &clk_src_mpll, | |
81 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | |
82 | }; | |
83 | ||
84 | ||
85 | static struct clksrc_clk clk_mout_apll = { | |
86 | .clk = { | |
87 | .name = "mout_apll", | |
88 | .id = -1, | |
89 | }, | |
90 | .sources = &clk_src_apll, | |
91 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | |
92 | }; | |
93 | ||
94 | static struct clksrc_clk clk_mout_epll = { | |
95 | .clk = { | |
96 | .name = "mout_epll", | |
97 | .id = -1, | |
98 | }, | |
99 | .sources = &clk_src_epll, | |
100 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | |
101 | }; | |
102 | ||
103 | static struct clk *clk_src_mout_hpll_list[] = { | |
104 | [0] = &s5p_clk_27m, | |
105 | }; | |
106 | ||
107 | static struct clksrc_sources clk_src_mout_hpll = { | |
108 | .sources = clk_src_mout_hpll_list, | |
109 | .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list), | |
110 | }; | |
111 | ||
112 | static struct clksrc_clk clk_mout_hpll = { | |
113 | .clk = { | |
114 | .name = "mout_hpll", | |
115 | .id = -1, | |
116 | }, | |
117 | .sources = &clk_src_mout_hpll, | |
118 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | |
119 | }; | |
120 | ||
121 | static struct clksrc_clk clk_div_apll = { | |
122 | .clk = { | |
123 | .name = "div_apll", | |
124 | .id = -1, | |
125 | .parent = &clk_mout_apll.clk, | |
126 | }, | |
127 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, | |
128 | }; | |
129 | ||
130 | static struct clksrc_clk clk_div_arm = { | |
131 | .clk = { | |
132 | .name = "div_arm", | |
133 | .id = -1, | |
134 | .parent = &clk_div_apll.clk, | |
135 | }, | |
136 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | |
137 | }; | |
138 | ||
139 | static struct clksrc_clk clk_div_d0_bus = { | |
140 | .clk = { | |
141 | .name = "div_d0_bus", | |
142 | .id = -1, | |
143 | .parent = &clk_div_arm.clk, | |
144 | }, | |
145 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | |
146 | }; | |
147 | ||
148 | static struct clksrc_clk clk_div_pclkd0 = { | |
149 | .clk = { | |
150 | .name = "div_pclkd0", | |
151 | .id = -1, | |
152 | .parent = &clk_div_d0_bus.clk, | |
153 | }, | |
154 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | |
155 | }; | |
156 | ||
157 | static struct clksrc_clk clk_div_secss = { | |
158 | .clk = { | |
159 | .name = "div_secss", | |
160 | .id = -1, | |
161 | .parent = &clk_div_d0_bus.clk, | |
162 | }, | |
163 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, | |
164 | }; | |
165 | ||
166 | static struct clksrc_clk clk_div_apll2 = { | |
167 | .clk = { | |
168 | .name = "div_apll2", | |
169 | .id = -1, | |
170 | .parent = &clk_mout_apll.clk, | |
171 | }, | |
172 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, | |
173 | }; | |
174 | ||
175 | static struct clk *clk_src_mout_am_list[] = { | |
176 | [0] = &clk_mout_mpll.clk, | |
177 | [1] = &clk_div_apll2.clk, | |
178 | }; | |
179 | ||
180 | struct clksrc_sources clk_src_mout_am = { | |
181 | .sources = clk_src_mout_am_list, | |
182 | .nr_sources = ARRAY_SIZE(clk_src_mout_am_list), | |
183 | }; | |
184 | ||
185 | static struct clksrc_clk clk_mout_am = { | |
186 | .clk = { | |
187 | .name = "mout_am", | |
188 | .id = -1, | |
189 | }, | |
190 | .sources = &clk_src_mout_am, | |
191 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | |
192 | }; | |
193 | ||
194 | static struct clksrc_clk clk_div_d1_bus = { | |
195 | .clk = { | |
196 | .name = "div_d1_bus", | |
197 | .id = -1, | |
198 | .parent = &clk_mout_am.clk, | |
199 | }, | |
200 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, | |
201 | }; | |
202 | ||
203 | static struct clksrc_clk clk_div_mpll2 = { | |
204 | .clk = { | |
205 | .name = "div_mpll2", | |
206 | .id = -1, | |
207 | .parent = &clk_mout_am.clk, | |
208 | }, | |
209 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, | |
210 | }; | |
211 | ||
212 | static struct clksrc_clk clk_div_mpll = { | |
213 | .clk = { | |
214 | .name = "div_mpll", | |
215 | .id = -1, | |
216 | .parent = &clk_mout_am.clk, | |
217 | }, | |
218 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, | |
219 | }; | |
220 | ||
221 | static struct clk *clk_src_mout_onenand_list[] = { | |
222 | [0] = &clk_div_d0_bus.clk, | |
223 | [1] = &clk_div_d1_bus.clk, | |
224 | }; | |
225 | ||
226 | struct clksrc_sources clk_src_mout_onenand = { | |
227 | .sources = clk_src_mout_onenand_list, | |
228 | .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list), | |
229 | }; | |
230 | ||
231 | static struct clksrc_clk clk_mout_onenand = { | |
232 | .clk = { | |
233 | .name = "mout_onenand", | |
234 | .id = -1, | |
235 | }, | |
236 | .sources = &clk_src_mout_onenand, | |
237 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | |
238 | }; | |
239 | ||
240 | static struct clksrc_clk clk_div_onenand = { | |
241 | .clk = { | |
242 | .name = "div_onenand", | |
243 | .id = -1, | |
244 | .parent = &clk_mout_onenand.clk, | |
245 | }, | |
246 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, | |
247 | }; | |
248 | ||
249 | static struct clksrc_clk clk_div_pclkd1 = { | |
250 | .clk = { | |
251 | .name = "div_pclkd1", | |
252 | .id = -1, | |
253 | .parent = &clk_div_d1_bus.clk, | |
254 | }, | |
255 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, | |
256 | }; | |
257 | ||
258 | static struct clksrc_clk clk_div_cam = { | |
259 | .clk = { | |
260 | .name = "div_cam", | |
261 | .id = -1, | |
262 | .parent = &clk_div_mpll2.clk, | |
263 | }, | |
264 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, | |
265 | }; | |
266 | ||
267 | static struct clksrc_clk clk_div_hdmi = { | |
268 | .clk = { | |
269 | .name = "div_hdmi", | |
270 | .id = -1, | |
271 | .parent = &clk_mout_hpll.clk, | |
272 | }, | |
273 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, | |
274 | }; | |
275 | ||
a443a637 TA |
276 | static u32 epll_div[][4] = { |
277 | { 32750000, 131, 3, 4 }, | |
278 | { 32768000, 131, 3, 4 }, | |
279 | { 36000000, 72, 3, 3 }, | |
280 | { 45000000, 90, 3, 3 }, | |
281 | { 45158000, 90, 3, 3 }, | |
282 | { 45158400, 90, 3, 3 }, | |
283 | { 48000000, 96, 3, 3 }, | |
284 | { 49125000, 131, 4, 3 }, | |
285 | { 49152000, 131, 4, 3 }, | |
286 | { 60000000, 120, 3, 3 }, | |
287 | { 67737600, 226, 5, 3 }, | |
288 | { 67738000, 226, 5, 3 }, | |
289 | { 73800000, 246, 5, 3 }, | |
290 | { 73728000, 246, 5, 3 }, | |
291 | { 72000000, 144, 3, 3 }, | |
292 | { 84000000, 168, 3, 3 }, | |
293 | { 96000000, 96, 3, 2 }, | |
294 | { 144000000, 144, 3, 2 }, | |
295 | { 192000000, 96, 3, 1 } | |
296 | }; | |
297 | ||
298 | static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate) | |
299 | { | |
300 | unsigned int epll_con; | |
301 | unsigned int i; | |
302 | ||
303 | if (clk->rate == rate) /* Return if nothing changed */ | |
304 | return 0; | |
305 | ||
306 | epll_con = __raw_readl(S5P_EPLL_CON); | |
307 | ||
308 | epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK); | |
309 | ||
310 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | |
311 | if (epll_div[i][0] == rate) { | |
312 | epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) | | |
313 | (epll_div[i][2] << PLL65XX_PDIV_SHIFT) | | |
314 | (epll_div[i][3] << PLL65XX_SDIV_SHIFT); | |
315 | break; | |
316 | } | |
317 | } | |
318 | ||
319 | if (i == ARRAY_SIZE(epll_div)) { | |
320 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); | |
321 | return -EINVAL; | |
322 | } | |
323 | ||
324 | __raw_writel(epll_con, S5P_EPLL_CON); | |
325 | ||
9616674a SY |
326 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", |
327 | clk->rate, rate); | |
328 | ||
a443a637 TA |
329 | clk->rate = rate; |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | static struct clk_ops s5pc100_epll_ops = { | |
d4b34c6c | 335 | .get_rate = s5p_epll_get_rate, |
a443a637 TA |
336 | .set_rate = s5pc100_epll_set_rate, |
337 | }; | |
338 | ||
339 | static int s5pc100_d0_0_ctrl(struct clk *clk, int enable) | |
340 | { | |
341 | return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable); | |
342 | } | |
343 | ||
344 | static int s5pc100_d0_1_ctrl(struct clk *clk, int enable) | |
345 | { | |
346 | return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable); | |
347 | } | |
348 | ||
349 | static int s5pc100_d0_2_ctrl(struct clk *clk, int enable) | |
350 | { | |
351 | return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable); | |
352 | } | |
353 | ||
354 | static int s5pc100_d1_0_ctrl(struct clk *clk, int enable) | |
355 | { | |
356 | return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable); | |
357 | } | |
358 | ||
359 | static int s5pc100_d1_1_ctrl(struct clk *clk, int enable) | |
360 | { | |
361 | return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable); | |
362 | } | |
363 | ||
364 | static int s5pc100_d1_2_ctrl(struct clk *clk, int enable) | |
365 | { | |
366 | return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable); | |
367 | } | |
368 | ||
369 | static int s5pc100_d1_3_ctrl(struct clk *clk, int enable) | |
370 | { | |
371 | return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable); | |
372 | } | |
373 | ||
374 | static int s5pc100_d1_4_ctrl(struct clk *clk, int enable) | |
375 | { | |
376 | return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable); | |
377 | } | |
378 | ||
379 | static int s5pc100_d1_5_ctrl(struct clk *clk, int enable) | |
380 | { | |
381 | return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable); | |
382 | } | |
383 | ||
384 | static int s5pc100_sclk0_ctrl(struct clk *clk, int enable) | |
385 | { | |
386 | return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable); | |
387 | } | |
388 | ||
389 | static int s5pc100_sclk1_ctrl(struct clk *clk, int enable) | |
390 | { | |
391 | return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable); | |
392 | } | |
393 | ||
394 | /* | |
395 | * The following clocks will be disabled during clock initialization. It is | |
396 | * recommended to keep the following clocks disabled until the driver requests | |
397 | * for enabling the clock. | |
398 | */ | |
399 | static struct clk init_clocks_disable[] = { | |
400 | { | |
401 | .name = "cssys", | |
402 | .id = -1, | |
403 | .parent = &clk_div_d0_bus.clk, | |
404 | .enable = s5pc100_d0_0_ctrl, | |
405 | .ctrlbit = (1 << 6), | |
406 | }, { | |
407 | .name = "secss", | |
408 | .id = -1, | |
409 | .parent = &clk_div_d0_bus.clk, | |
410 | .enable = s5pc100_d0_0_ctrl, | |
411 | .ctrlbit = (1 << 5), | |
412 | }, { | |
413 | .name = "g2d", | |
414 | .id = -1, | |
415 | .parent = &clk_div_d0_bus.clk, | |
416 | .enable = s5pc100_d0_0_ctrl, | |
417 | .ctrlbit = (1 << 4), | |
418 | }, { | |
419 | .name = "mdma", | |
420 | .id = -1, | |
421 | .parent = &clk_div_d0_bus.clk, | |
422 | .enable = s5pc100_d0_0_ctrl, | |
423 | .ctrlbit = (1 << 3), | |
424 | }, { | |
425 | .name = "cfcon", | |
426 | .id = -1, | |
427 | .parent = &clk_div_d0_bus.clk, | |
428 | .enable = s5pc100_d0_0_ctrl, | |
429 | .ctrlbit = (1 << 2), | |
430 | }, { | |
431 | .name = "nfcon", | |
432 | .id = -1, | |
433 | .parent = &clk_div_d0_bus.clk, | |
434 | .enable = s5pc100_d0_1_ctrl, | |
435 | .ctrlbit = (1 << 3), | |
436 | }, { | |
437 | .name = "onenandc", | |
438 | .id = -1, | |
439 | .parent = &clk_div_d0_bus.clk, | |
440 | .enable = s5pc100_d0_1_ctrl, | |
441 | .ctrlbit = (1 << 2), | |
442 | }, { | |
443 | .name = "sdm", | |
444 | .id = -1, | |
445 | .parent = &clk_div_d0_bus.clk, | |
446 | .enable = s5pc100_d0_2_ctrl, | |
447 | .ctrlbit = (1 << 2), | |
448 | }, { | |
449 | .name = "seckey", | |
450 | .id = -1, | |
451 | .parent = &clk_div_d0_bus.clk, | |
452 | .enable = s5pc100_d0_2_ctrl, | |
453 | .ctrlbit = (1 << 1), | |
454 | }, { | |
455 | .name = "hsmmc", | |
456 | .id = 2, | |
457 | .parent = &clk_div_d1_bus.clk, | |
458 | .enable = s5pc100_d1_0_ctrl, | |
459 | .ctrlbit = (1 << 7), | |
460 | }, { | |
461 | .name = "hsmmc", | |
462 | .id = 1, | |
463 | .parent = &clk_div_d1_bus.clk, | |
464 | .enable = s5pc100_d1_0_ctrl, | |
465 | .ctrlbit = (1 << 6), | |
466 | }, { | |
467 | .name = "hsmmc", | |
468 | .id = 0, | |
469 | .parent = &clk_div_d1_bus.clk, | |
470 | .enable = s5pc100_d1_0_ctrl, | |
471 | .ctrlbit = (1 << 5), | |
472 | }, { | |
473 | .name = "modemif", | |
474 | .id = -1, | |
475 | .parent = &clk_div_d1_bus.clk, | |
476 | .enable = s5pc100_d1_0_ctrl, | |
477 | .ctrlbit = (1 << 4), | |
478 | }, { | |
479 | .name = "otg", | |
480 | .id = -1, | |
481 | .parent = &clk_div_d1_bus.clk, | |
482 | .enable = s5pc100_d1_0_ctrl, | |
483 | .ctrlbit = (1 << 3), | |
484 | }, { | |
485 | .name = "usbhost", | |
486 | .id = -1, | |
487 | .parent = &clk_div_d1_bus.clk, | |
488 | .enable = s5pc100_d1_0_ctrl, | |
489 | .ctrlbit = (1 << 2), | |
490 | }, { | |
491 | .name = "pdma", | |
492 | .id = 1, | |
493 | .parent = &clk_div_d1_bus.clk, | |
494 | .enable = s5pc100_d1_0_ctrl, | |
495 | .ctrlbit = (1 << 1), | |
496 | }, { | |
497 | .name = "pdma", | |
498 | .id = 0, | |
499 | .parent = &clk_div_d1_bus.clk, | |
500 | .enable = s5pc100_d1_0_ctrl, | |
501 | .ctrlbit = (1 << 0), | |
502 | }, { | |
503 | .name = "lcd", | |
504 | .id = -1, | |
505 | .parent = &clk_div_d1_bus.clk, | |
506 | .enable = s5pc100_d1_1_ctrl, | |
507 | .ctrlbit = (1 << 0), | |
508 | }, { | |
509 | .name = "rotator", | |
510 | .id = -1, | |
511 | .parent = &clk_div_d1_bus.clk, | |
512 | .enable = s5pc100_d1_1_ctrl, | |
513 | .ctrlbit = (1 << 1), | |
514 | }, { | |
515 | .name = "fimc", | |
516 | .id = 0, | |
517 | .parent = &clk_div_d1_bus.clk, | |
518 | .enable = s5pc100_d1_1_ctrl, | |
519 | .ctrlbit = (1 << 2), | |
520 | }, { | |
521 | .name = "fimc", | |
522 | .id = 1, | |
523 | .parent = &clk_div_d1_bus.clk, | |
524 | .enable = s5pc100_d1_1_ctrl, | |
525 | .ctrlbit = (1 << 3), | |
526 | }, { | |
527 | .name = "fimc", | |
528 | .id = 2, | |
529 | .parent = &clk_div_d1_bus.clk, | |
530 | .enable = s5pc100_d1_1_ctrl, | |
531 | .ctrlbit = (1 << 4), | |
532 | }, { | |
533 | .name = "jpeg", | |
534 | .id = -1, | |
535 | .parent = &clk_div_d1_bus.clk, | |
536 | .enable = s5pc100_d1_1_ctrl, | |
537 | .ctrlbit = (1 << 5), | |
538 | }, { | |
539 | .name = "mipi-dsim", | |
540 | .id = -1, | |
541 | .parent = &clk_div_d1_bus.clk, | |
542 | .enable = s5pc100_d1_1_ctrl, | |
543 | .ctrlbit = (1 << 6), | |
544 | }, { | |
545 | .name = "mipi-csis", | |
546 | .id = -1, | |
547 | .parent = &clk_div_d1_bus.clk, | |
548 | .enable = s5pc100_d1_1_ctrl, | |
549 | .ctrlbit = (1 << 7), | |
550 | }, { | |
551 | .name = "g3d", | |
552 | .id = 0, | |
553 | .parent = &clk_div_d1_bus.clk, | |
554 | .enable = s5pc100_d1_0_ctrl, | |
555 | .ctrlbit = (1 << 8), | |
556 | }, { | |
557 | .name = "tv", | |
558 | .id = -1, | |
559 | .parent = &clk_div_d1_bus.clk, | |
560 | .enable = s5pc100_d1_2_ctrl, | |
561 | .ctrlbit = (1 << 0), | |
562 | }, { | |
563 | .name = "vp", | |
564 | .id = -1, | |
565 | .parent = &clk_div_d1_bus.clk, | |
566 | .enable = s5pc100_d1_2_ctrl, | |
567 | .ctrlbit = (1 << 1), | |
568 | }, { | |
569 | .name = "mixer", | |
570 | .id = -1, | |
571 | .parent = &clk_div_d1_bus.clk, | |
572 | .enable = s5pc100_d1_2_ctrl, | |
573 | .ctrlbit = (1 << 2), | |
574 | }, { | |
575 | .name = "hdmi", | |
576 | .id = -1, | |
577 | .parent = &clk_div_d1_bus.clk, | |
578 | .enable = s5pc100_d1_2_ctrl, | |
579 | .ctrlbit = (1 << 3), | |
580 | }, { | |
581 | .name = "mfc", | |
582 | .id = -1, | |
583 | .parent = &clk_div_d1_bus.clk, | |
584 | .enable = s5pc100_d1_2_ctrl, | |
585 | .ctrlbit = (1 << 4), | |
586 | }, { | |
587 | .name = "apc", | |
588 | .id = -1, | |
589 | .parent = &clk_div_d1_bus.clk, | |
590 | .enable = s5pc100_d1_3_ctrl, | |
591 | .ctrlbit = (1 << 2), | |
592 | }, { | |
593 | .name = "iec", | |
594 | .id = -1, | |
595 | .parent = &clk_div_d1_bus.clk, | |
596 | .enable = s5pc100_d1_3_ctrl, | |
597 | .ctrlbit = (1 << 3), | |
598 | }, { | |
599 | .name = "systimer", | |
600 | .id = -1, | |
601 | .parent = &clk_div_d1_bus.clk, | |
602 | .enable = s5pc100_d1_3_ctrl, | |
603 | .ctrlbit = (1 << 7), | |
604 | }, { | |
605 | .name = "watchdog", | |
606 | .id = -1, | |
607 | .parent = &clk_div_d1_bus.clk, | |
608 | .enable = s5pc100_d1_3_ctrl, | |
609 | .ctrlbit = (1 << 8), | |
610 | }, { | |
611 | .name = "rtc", | |
612 | .id = -1, | |
613 | .parent = &clk_div_d1_bus.clk, | |
614 | .enable = s5pc100_d1_3_ctrl, | |
615 | .ctrlbit = (1 << 9), | |
616 | }, { | |
617 | .name = "i2c", | |
618 | .id = 0, | |
619 | .parent = &clk_div_d1_bus.clk, | |
620 | .enable = s5pc100_d1_4_ctrl, | |
621 | .ctrlbit = (1 << 4), | |
622 | }, { | |
623 | .name = "i2c", | |
624 | .id = 1, | |
625 | .parent = &clk_div_d1_bus.clk, | |
626 | .enable = s5pc100_d1_4_ctrl, | |
627 | .ctrlbit = (1 << 5), | |
628 | }, { | |
629 | .name = "spi", | |
630 | .id = 0, | |
631 | .parent = &clk_div_d1_bus.clk, | |
632 | .enable = s5pc100_d1_4_ctrl, | |
633 | .ctrlbit = (1 << 6), | |
634 | }, { | |
635 | .name = "spi", | |
636 | .id = 1, | |
637 | .parent = &clk_div_d1_bus.clk, | |
638 | .enable = s5pc100_d1_4_ctrl, | |
639 | .ctrlbit = (1 << 7), | |
640 | }, { | |
641 | .name = "spi", | |
642 | .id = 2, | |
643 | .parent = &clk_div_d1_bus.clk, | |
644 | .enable = s5pc100_d1_4_ctrl, | |
645 | .ctrlbit = (1 << 8), | |
646 | }, { | |
647 | .name = "irda", | |
648 | .id = -1, | |
649 | .parent = &clk_div_d1_bus.clk, | |
650 | .enable = s5pc100_d1_4_ctrl, | |
651 | .ctrlbit = (1 << 9), | |
652 | }, { | |
653 | .name = "ccan", | |
654 | .id = 0, | |
655 | .parent = &clk_div_d1_bus.clk, | |
656 | .enable = s5pc100_d1_4_ctrl, | |
657 | .ctrlbit = (1 << 10), | |
658 | }, { | |
659 | .name = "ccan", | |
660 | .id = 1, | |
661 | .parent = &clk_div_d1_bus.clk, | |
662 | .enable = s5pc100_d1_4_ctrl, | |
663 | .ctrlbit = (1 << 11), | |
664 | }, { | |
665 | .name = "hsitx", | |
666 | .id = -1, | |
667 | .parent = &clk_div_d1_bus.clk, | |
668 | .enable = s5pc100_d1_4_ctrl, | |
669 | .ctrlbit = (1 << 12), | |
670 | }, { | |
671 | .name = "hsirx", | |
672 | .id = -1, | |
673 | .parent = &clk_div_d1_bus.clk, | |
674 | .enable = s5pc100_d1_4_ctrl, | |
675 | .ctrlbit = (1 << 13), | |
676 | }, { | |
677 | .name = "iis", | |
678 | .id = 0, | |
05daf079 | 679 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
680 | .enable = s5pc100_d1_5_ctrl, |
681 | .ctrlbit = (1 << 0), | |
682 | }, { | |
683 | .name = "iis", | |
684 | .id = 1, | |
05daf079 | 685 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
686 | .enable = s5pc100_d1_5_ctrl, |
687 | .ctrlbit = (1 << 1), | |
688 | }, { | |
689 | .name = "iis", | |
690 | .id = 2, | |
05daf079 | 691 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
692 | .enable = s5pc100_d1_5_ctrl, |
693 | .ctrlbit = (1 << 2), | |
694 | }, { | |
695 | .name = "ac97", | |
696 | .id = -1, | |
05daf079 | 697 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
698 | .enable = s5pc100_d1_5_ctrl, |
699 | .ctrlbit = (1 << 3), | |
700 | }, { | |
701 | .name = "pcm", | |
702 | .id = 0, | |
05daf079 | 703 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
704 | .enable = s5pc100_d1_5_ctrl, |
705 | .ctrlbit = (1 << 4), | |
706 | }, { | |
707 | .name = "pcm", | |
708 | .id = 1, | |
05daf079 | 709 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
710 | .enable = s5pc100_d1_5_ctrl, |
711 | .ctrlbit = (1 << 5), | |
712 | }, { | |
713 | .name = "spdif", | |
714 | .id = -1, | |
05daf079 | 715 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
716 | .enable = s5pc100_d1_5_ctrl, |
717 | .ctrlbit = (1 << 6), | |
718 | }, { | |
719 | .name = "adc", | |
720 | .id = -1, | |
05daf079 | 721 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
722 | .enable = s5pc100_d1_5_ctrl, |
723 | .ctrlbit = (1 << 7), | |
724 | }, { | |
32018a8c | 725 | .name = "keypad", |
a443a637 | 726 | .id = -1, |
05daf079 | 727 | .parent = &clk_div_pclkd1.clk, |
a443a637 TA |
728 | .enable = s5pc100_d1_5_ctrl, |
729 | .ctrlbit = (1 << 8), | |
730 | }, { | |
731 | .name = "spi_48m", | |
732 | .id = 0, | |
733 | .parent = &clk_mout_48m.clk, | |
734 | .enable = s5pc100_sclk0_ctrl, | |
735 | .ctrlbit = (1 << 7), | |
736 | }, { | |
737 | .name = "spi_48m", | |
738 | .id = 1, | |
739 | .parent = &clk_mout_48m.clk, | |
740 | .enable = s5pc100_sclk0_ctrl, | |
741 | .ctrlbit = (1 << 8), | |
742 | }, { | |
743 | .name = "spi_48m", | |
744 | .id = 2, | |
745 | .parent = &clk_mout_48m.clk, | |
746 | .enable = s5pc100_sclk0_ctrl, | |
747 | .ctrlbit = (1 << 9), | |
748 | }, { | |
749 | .name = "mmc_48m", | |
750 | .id = 0, | |
751 | .parent = &clk_mout_48m.clk, | |
752 | .enable = s5pc100_sclk0_ctrl, | |
753 | .ctrlbit = (1 << 15), | |
754 | }, { | |
755 | .name = "mmc_48m", | |
756 | .id = 1, | |
757 | .parent = &clk_mout_48m.clk, | |
758 | .enable = s5pc100_sclk0_ctrl, | |
759 | .ctrlbit = (1 << 16), | |
760 | }, { | |
761 | .name = "mmc_48m", | |
762 | .id = 2, | |
763 | .parent = &clk_mout_48m.clk, | |
764 | .enable = s5pc100_sclk0_ctrl, | |
765 | .ctrlbit = (1 << 17), | |
766 | }, | |
767 | }; | |
768 | ||
769 | static struct clk clk_vclk54m = { | |
770 | .name = "vclk_54m", | |
771 | .id = -1, | |
772 | .rate = 54000000, | |
773 | }; | |
774 | ||
775 | static struct clk clk_i2scdclk0 = { | |
776 | .name = "i2s_cdclk0", | |
777 | .id = -1, | |
778 | }; | |
779 | ||
780 | static struct clk clk_i2scdclk1 = { | |
781 | .name = "i2s_cdclk1", | |
782 | .id = -1, | |
783 | }; | |
784 | ||
785 | static struct clk clk_i2scdclk2 = { | |
786 | .name = "i2s_cdclk2", | |
787 | .id = -1, | |
788 | }; | |
789 | ||
790 | static struct clk clk_pcmcdclk0 = { | |
791 | .name = "pcm_cdclk0", | |
792 | .id = -1, | |
793 | }; | |
794 | ||
795 | static struct clk clk_pcmcdclk1 = { | |
796 | .name = "pcm_cdclk1", | |
797 | .id = -1, | |
798 | }; | |
799 | ||
800 | static struct clk *clk_src_group1_list[] = { | |
801 | [0] = &clk_mout_epll.clk, | |
802 | [1] = &clk_div_mpll2.clk, | |
803 | [2] = &clk_fin_epll, | |
804 | [3] = &clk_mout_hpll.clk, | |
805 | }; | |
806 | ||
807 | struct clksrc_sources clk_src_group1 = { | |
808 | .sources = clk_src_group1_list, | |
809 | .nr_sources = ARRAY_SIZE(clk_src_group1_list), | |
810 | }; | |
811 | ||
812 | static struct clk *clk_src_group2_list[] = { | |
813 | [0] = &clk_mout_epll.clk, | |
814 | [1] = &clk_div_mpll.clk, | |
815 | }; | |
816 | ||
817 | struct clksrc_sources clk_src_group2 = { | |
818 | .sources = clk_src_group2_list, | |
819 | .nr_sources = ARRAY_SIZE(clk_src_group2_list), | |
820 | }; | |
821 | ||
822 | static struct clk *clk_src_group3_list[] = { | |
823 | [0] = &clk_mout_epll.clk, | |
824 | [1] = &clk_div_mpll.clk, | |
825 | [2] = &clk_fin_epll, | |
826 | [3] = &clk_i2scdclk0, | |
827 | [4] = &clk_pcmcdclk0, | |
828 | [5] = &clk_mout_hpll.clk, | |
829 | }; | |
830 | ||
831 | struct clksrc_sources clk_src_group3 = { | |
832 | .sources = clk_src_group3_list, | |
833 | .nr_sources = ARRAY_SIZE(clk_src_group3_list), | |
834 | }; | |
835 | ||
4cfd9c25 SY |
836 | static struct clksrc_clk clk_sclk_audio0 = { |
837 | .clk = { | |
838 | .name = "sclk_audio", | |
839 | .id = 0, | |
840 | .ctrlbit = (1 << 8), | |
841 | .enable = s5pc100_sclk1_ctrl, | |
842 | }, | |
843 | .sources = &clk_src_group3, | |
844 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 }, | |
845 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, | |
846 | }; | |
847 | ||
a443a637 TA |
848 | static struct clk *clk_src_group4_list[] = { |
849 | [0] = &clk_mout_epll.clk, | |
850 | [1] = &clk_div_mpll.clk, | |
851 | [2] = &clk_fin_epll, | |
852 | [3] = &clk_i2scdclk1, | |
853 | [4] = &clk_pcmcdclk1, | |
854 | [5] = &clk_mout_hpll.clk, | |
855 | }; | |
856 | ||
857 | struct clksrc_sources clk_src_group4 = { | |
858 | .sources = clk_src_group4_list, | |
859 | .nr_sources = ARRAY_SIZE(clk_src_group4_list), | |
860 | }; | |
861 | ||
4cfd9c25 SY |
862 | static struct clksrc_clk clk_sclk_audio1 = { |
863 | .clk = { | |
864 | .name = "sclk_audio", | |
865 | .id = 1, | |
866 | .ctrlbit = (1 << 9), | |
867 | .enable = s5pc100_sclk1_ctrl, | |
868 | }, | |
869 | .sources = &clk_src_group4, | |
870 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 }, | |
871 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, | |
872 | }; | |
873 | ||
a443a637 TA |
874 | static struct clk *clk_src_group5_list[] = { |
875 | [0] = &clk_mout_epll.clk, | |
876 | [1] = &clk_div_mpll.clk, | |
877 | [2] = &clk_fin_epll, | |
878 | [3] = &clk_i2scdclk2, | |
879 | [4] = &clk_mout_hpll.clk, | |
880 | }; | |
881 | ||
882 | struct clksrc_sources clk_src_group5 = { | |
883 | .sources = clk_src_group5_list, | |
884 | .nr_sources = ARRAY_SIZE(clk_src_group5_list), | |
885 | }; | |
886 | ||
4cfd9c25 SY |
887 | static struct clksrc_clk clk_sclk_audio2 = { |
888 | .clk = { | |
889 | .name = "sclk_audio", | |
890 | .id = 2, | |
891 | .ctrlbit = (1 << 10), | |
892 | .enable = s5pc100_sclk1_ctrl, | |
893 | }, | |
894 | .sources = &clk_src_group5, | |
895 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 }, | |
896 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, | |
897 | }; | |
898 | ||
a443a637 TA |
899 | static struct clk *clk_src_group6_list[] = { |
900 | [0] = &s5p_clk_27m, | |
901 | [1] = &clk_vclk54m, | |
902 | [2] = &clk_div_hdmi.clk, | |
903 | }; | |
904 | ||
905 | struct clksrc_sources clk_src_group6 = { | |
906 | .sources = clk_src_group6_list, | |
907 | .nr_sources = ARRAY_SIZE(clk_src_group6_list), | |
908 | }; | |
909 | ||
910 | static struct clk *clk_src_group7_list[] = { | |
911 | [0] = &clk_mout_epll.clk, | |
912 | [1] = &clk_div_mpll.clk, | |
913 | [2] = &clk_mout_hpll.clk, | |
914 | [3] = &clk_vclk54m, | |
915 | }; | |
916 | ||
917 | struct clksrc_sources clk_src_group7 = { | |
918 | .sources = clk_src_group7_list, | |
919 | .nr_sources = ARRAY_SIZE(clk_src_group7_list), | |
920 | }; | |
921 | ||
922 | static struct clk *clk_src_mmc0_list[] = { | |
923 | [0] = &clk_mout_epll.clk, | |
924 | [1] = &clk_div_mpll.clk, | |
925 | [2] = &clk_fin_epll, | |
926 | }; | |
927 | ||
928 | struct clksrc_sources clk_src_mmc0 = { | |
929 | .sources = clk_src_mmc0_list, | |
930 | .nr_sources = ARRAY_SIZE(clk_src_mmc0_list), | |
931 | }; | |
932 | ||
933 | static struct clk *clk_src_mmc12_list[] = { | |
934 | [0] = &clk_mout_epll.clk, | |
935 | [1] = &clk_div_mpll.clk, | |
936 | [2] = &clk_fin_epll, | |
937 | [3] = &clk_mout_hpll.clk, | |
938 | }; | |
939 | ||
940 | struct clksrc_sources clk_src_mmc12 = { | |
941 | .sources = clk_src_mmc12_list, | |
942 | .nr_sources = ARRAY_SIZE(clk_src_mmc12_list), | |
943 | }; | |
944 | ||
945 | static struct clk *clk_src_irda_usb_list[] = { | |
946 | [0] = &clk_mout_epll.clk, | |
947 | [1] = &clk_div_mpll.clk, | |
948 | [2] = &clk_fin_epll, | |
949 | [3] = &clk_mout_hpll.clk, | |
950 | }; | |
951 | ||
952 | struct clksrc_sources clk_src_irda_usb = { | |
953 | .sources = clk_src_irda_usb_list, | |
954 | .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list), | |
955 | }; | |
956 | ||
957 | static struct clk *clk_src_pwi_list[] = { | |
958 | [0] = &clk_fin_epll, | |
959 | [1] = &clk_mout_epll.clk, | |
960 | [2] = &clk_div_mpll.clk, | |
961 | }; | |
962 | ||
963 | struct clksrc_sources clk_src_pwi = { | |
964 | .sources = clk_src_pwi_list, | |
965 | .nr_sources = ARRAY_SIZE(clk_src_pwi_list), | |
966 | }; | |
967 | ||
04a4fd0a SY |
968 | static struct clk *clk_sclk_spdif_list[] = { |
969 | [0] = &clk_sclk_audio0.clk, | |
970 | [1] = &clk_sclk_audio1.clk, | |
971 | [2] = &clk_sclk_audio2.clk, | |
972 | }; | |
973 | ||
974 | struct clksrc_sources clk_src_sclk_spdif = { | |
975 | .sources = clk_sclk_spdif_list, | |
976 | .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list), | |
977 | }; | |
978 | ||
979 | static int s5pc100_spdif_set_rate(struct clk *clk, unsigned long rate) | |
980 | { | |
981 | struct clk *pclk; | |
982 | int ret; | |
983 | ||
984 | pclk = clk_get_parent(clk); | |
985 | if (IS_ERR(pclk)) | |
986 | return -EINVAL; | |
987 | ||
988 | ret = pclk->ops->set_rate(pclk, rate); | |
989 | clk_put(pclk); | |
990 | ||
991 | return ret; | |
992 | } | |
993 | ||
994 | static unsigned long s5pc100_spdif_get_rate(struct clk *clk) | |
995 | { | |
996 | struct clk *pclk; | |
997 | int rate; | |
998 | ||
999 | pclk = clk_get_parent(clk); | |
1000 | if (IS_ERR(pclk)) | |
1001 | return -EINVAL; | |
1002 | ||
1003 | rate = pclk->ops->get_rate(clk); | |
1004 | clk_put(pclk); | |
1005 | ||
1006 | return rate; | |
1007 | } | |
1008 | ||
1009 | static struct clk_ops s5pc100_sclk_spdif_ops = { | |
1010 | .set_rate = s5pc100_spdif_set_rate, | |
1011 | .get_rate = s5pc100_spdif_get_rate, | |
1012 | }; | |
1013 | ||
1014 | static struct clksrc_clk clk_sclk_spdif = { | |
1015 | .clk = { | |
1016 | .name = "sclk_spdif", | |
1017 | .id = -1, | |
1018 | .ctrlbit = (1 << 11), | |
1019 | .enable = s5pc100_sclk1_ctrl, | |
1020 | .ops = &s5pc100_sclk_spdif_ops, | |
1021 | }, | |
1022 | .sources = &clk_src_sclk_spdif, | |
1023 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 }, | |
1024 | }; | |
1025 | ||
a443a637 TA |
1026 | static struct clksrc_clk clksrcs[] = { |
1027 | { | |
1028 | .clk = { | |
1029 | .name = "sclk_spi", | |
1030 | .id = 0, | |
1031 | .ctrlbit = (1 << 4), | |
1032 | .enable = s5pc100_sclk0_ctrl, | |
1033 | ||
1034 | }, | |
1035 | .sources = &clk_src_group1, | |
1036 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, | |
1037 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | |
1038 | }, { | |
1039 | .clk = { | |
1040 | .name = "sclk_spi", | |
1041 | .id = 1, | |
1042 | .ctrlbit = (1 << 5), | |
1043 | .enable = s5pc100_sclk0_ctrl, | |
1044 | ||
1045 | }, | |
1046 | .sources = &clk_src_group1, | |
1047 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, | |
1048 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, | |
1049 | }, { | |
1050 | .clk = { | |
1051 | .name = "sclk_spi", | |
1052 | .id = 2, | |
1053 | .ctrlbit = (1 << 6), | |
1054 | .enable = s5pc100_sclk0_ctrl, | |
1055 | ||
1056 | }, | |
1057 | .sources = &clk_src_group1, | |
1058 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 }, | |
1059 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 }, | |
1060 | }, { | |
1061 | .clk = { | |
1062 | .name = "uclk1", | |
1063 | .id = -1, | |
1064 | .ctrlbit = (1 << 3), | |
1065 | .enable = s5pc100_sclk0_ctrl, | |
1066 | ||
1067 | }, | |
1068 | .sources = &clk_src_group2, | |
1069 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, | |
1070 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | |
1071 | }, { | |
1072 | .clk = { | |
1073 | .name = "sclk_mixer", | |
1074 | .id = -1, | |
1075 | .ctrlbit = (1 << 6), | |
1076 | .enable = s5pc100_sclk0_ctrl, | |
1077 | ||
1078 | }, | |
1079 | .sources = &clk_src_group6, | |
1080 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 }, | |
a443a637 TA |
1081 | }, { |
1082 | .clk = { | |
1083 | .name = "sclk_lcd", | |
1084 | .id = -1, | |
1085 | .ctrlbit = (1 << 0), | |
1086 | .enable = s5pc100_sclk1_ctrl, | |
1087 | ||
1088 | }, | |
1089 | .sources = &clk_src_group7, | |
1090 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 }, | |
1091 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, | |
1092 | }, { | |
1093 | .clk = { | |
1094 | .name = "sclk_fimc", | |
1095 | .id = 0, | |
1096 | .ctrlbit = (1 << 1), | |
1097 | .enable = s5pc100_sclk1_ctrl, | |
1098 | ||
1099 | }, | |
1100 | .sources = &clk_src_group7, | |
1101 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 }, | |
1102 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, | |
1103 | }, { | |
1104 | .clk = { | |
1105 | .name = "sclk_fimc", | |
1106 | .id = 1, | |
1107 | .ctrlbit = (1 << 2), | |
1108 | .enable = s5pc100_sclk1_ctrl, | |
1109 | ||
1110 | }, | |
1111 | .sources = &clk_src_group7, | |
1112 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 }, | |
1113 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, | |
1114 | }, { | |
1115 | .clk = { | |
1116 | .name = "sclk_fimc", | |
1117 | .id = 2, | |
1118 | .ctrlbit = (1 << 3), | |
1119 | .enable = s5pc100_sclk1_ctrl, | |
1120 | ||
1121 | }, | |
1122 | .sources = &clk_src_group7, | |
1123 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 }, | |
1124 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, | |
1125 | }, { | |
1126 | .clk = { | |
aaeedff6 | 1127 | .name = "sclk_mmc", |
a443a637 TA |
1128 | .id = 0, |
1129 | .ctrlbit = (1 << 12), | |
1130 | .enable = s5pc100_sclk1_ctrl, | |
1131 | ||
1132 | }, | |
1133 | .sources = &clk_src_mmc0, | |
1134 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, | |
1135 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, | |
1136 | }, { | |
1137 | .clk = { | |
aaeedff6 | 1138 | .name = "sclk_mmc", |
a443a637 TA |
1139 | .id = 1, |
1140 | .ctrlbit = (1 << 13), | |
1141 | .enable = s5pc100_sclk1_ctrl, | |
1142 | ||
1143 | }, | |
1144 | .sources = &clk_src_mmc12, | |
1145 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, | |
1146 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, | |
1147 | }, { | |
1148 | .clk = { | |
aaeedff6 | 1149 | .name = "sclk_mmc", |
a443a637 TA |
1150 | .id = 2, |
1151 | .ctrlbit = (1 << 14), | |
1152 | .enable = s5pc100_sclk1_ctrl, | |
1153 | ||
1154 | }, | |
1155 | .sources = &clk_src_mmc12, | |
1156 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | |
1157 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, | |
1158 | }, { | |
1159 | .clk = { | |
1160 | .name = "sclk_irda", | |
1161 | .id = 2, | |
1162 | .ctrlbit = (1 << 10), | |
1163 | .enable = s5pc100_sclk0_ctrl, | |
1164 | ||
1165 | }, | |
1166 | .sources = &clk_src_irda_usb, | |
1167 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | |
1168 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, | |
1169 | }, { | |
1170 | .clk = { | |
1171 | .name = "sclk_irda", | |
1172 | .id = -1, | |
1173 | .ctrlbit = (1 << 10), | |
1174 | .enable = s5pc100_sclk0_ctrl, | |
1175 | ||
1176 | }, | |
1177 | .sources = &clk_src_mmc12, | |
1178 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 }, | |
1179 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 }, | |
1180 | }, { | |
1181 | .clk = { | |
1182 | .name = "sclk_pwi", | |
1183 | .id = -1, | |
1184 | .ctrlbit = (1 << 1), | |
1185 | .enable = s5pc100_sclk0_ctrl, | |
1186 | ||
1187 | }, | |
1188 | .sources = &clk_src_pwi, | |
1189 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 }, | |
1190 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 }, | |
1191 | }, { | |
1192 | .clk = { | |
1193 | .name = "sclk_uhost", | |
1194 | .id = -1, | |
1195 | .ctrlbit = (1 << 11), | |
1196 | .enable = s5pc100_sclk0_ctrl, | |
1197 | ||
1198 | }, | |
1199 | .sources = &clk_src_irda_usb, | |
1200 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 }, | |
1201 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 }, | |
1202 | }, | |
1203 | }; | |
1204 | ||
1205 | /* Clock initialisation code */ | |
1206 | static struct clksrc_clk *sysclks[] = { | |
1207 | &clk_mout_apll, | |
1208 | &clk_mout_epll, | |
1209 | &clk_mout_mpll, | |
1210 | &clk_mout_hpll, | |
1211 | &clk_mout_href, | |
1212 | &clk_mout_48m, | |
1213 | &clk_div_apll, | |
1214 | &clk_div_arm, | |
1215 | &clk_div_d0_bus, | |
1216 | &clk_div_pclkd0, | |
1217 | &clk_div_secss, | |
1218 | &clk_div_apll2, | |
1219 | &clk_mout_am, | |
1220 | &clk_div_d1_bus, | |
1221 | &clk_div_mpll2, | |
1222 | &clk_div_mpll, | |
1223 | &clk_mout_onenand, | |
1224 | &clk_div_onenand, | |
1225 | &clk_div_pclkd1, | |
1226 | &clk_div_cam, | |
1227 | &clk_div_hdmi, | |
4cfd9c25 SY |
1228 | &clk_sclk_audio0, |
1229 | &clk_sclk_audio1, | |
1230 | &clk_sclk_audio2, | |
04a4fd0a | 1231 | &clk_sclk_spdif, |
a443a637 TA |
1232 | }; |
1233 | ||
1234 | void __init_or_cpufreq s5pc100_setup_clocks(void) | |
1235 | { | |
1236 | unsigned long xtal; | |
1237 | unsigned long arm; | |
1238 | unsigned long hclkd0; | |
1239 | unsigned long hclkd1; | |
1240 | unsigned long pclkd0; | |
1241 | unsigned long pclkd1; | |
1242 | unsigned long apll; | |
1243 | unsigned long mpll; | |
1244 | unsigned long epll; | |
1245 | unsigned long hpll; | |
1246 | unsigned int ptr; | |
1247 | ||
1248 | /* Set S5PC100 functions for clk_fout_epll */ | |
d4b34c6c | 1249 | clk_fout_epll.enable = s5p_epll_enable; |
a443a637 TA |
1250 | clk_fout_epll.ops = &s5pc100_epll_ops; |
1251 | ||
1252 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | |
1253 | ||
1254 | xtal = clk_get_rate(&clk_xtal); | |
1255 | ||
1256 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1257 | ||
1258 | apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON)); | |
1259 | mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON)); | |
1260 | epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON)); | |
1261 | hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON)); | |
1262 | ||
1263 | printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n", | |
1264 | print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll)); | |
1265 | ||
1266 | clk_fout_apll.rate = apll; | |
1267 | clk_fout_mpll.rate = mpll; | |
1268 | clk_fout_epll.rate = epll; | |
1269 | clk_mout_hpll.clk.rate = hpll; | |
1270 | ||
1271 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | |
1272 | s3c_set_clksrc(&clksrcs[ptr], true); | |
1273 | ||
1274 | arm = clk_get_rate(&clk_div_arm.clk); | |
1275 | hclkd0 = clk_get_rate(&clk_div_d0_bus.clk); | |
1276 | pclkd0 = clk_get_rate(&clk_div_pclkd0.clk); | |
1277 | hclkd1 = clk_get_rate(&clk_div_d1_bus.clk); | |
1278 | pclkd1 = clk_get_rate(&clk_div_pclkd1.clk); | |
1279 | ||
1280 | printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n", | |
1281 | print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1)); | |
1282 | ||
1283 | clk_f.rate = arm; | |
1284 | clk_h.rate = hclkd1; | |
1285 | clk_p.rate = pclkd1; | |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * The following clocks will be enabled during clock initialization. | |
1290 | */ | |
1291 | static struct clk init_clocks[] = { | |
1292 | { | |
1293 | .name = "tzic", | |
1294 | .id = -1, | |
1295 | .parent = &clk_div_d0_bus.clk, | |
1296 | .enable = s5pc100_d0_0_ctrl, | |
1297 | .ctrlbit = (1 << 1), | |
1298 | }, { | |
1299 | .name = "intc", | |
1300 | .id = -1, | |
1301 | .parent = &clk_div_d0_bus.clk, | |
1302 | .enable = s5pc100_d0_0_ctrl, | |
1303 | .ctrlbit = (1 << 0), | |
1304 | }, { | |
1305 | .name = "ebi", | |
1306 | .id = -1, | |
1307 | .parent = &clk_div_d0_bus.clk, | |
1308 | .enable = s5pc100_d0_1_ctrl, | |
1309 | .ctrlbit = (1 << 5), | |
1310 | }, { | |
1311 | .name = "intmem", | |
1312 | .id = -1, | |
1313 | .parent = &clk_div_d0_bus.clk, | |
1314 | .enable = s5pc100_d0_1_ctrl, | |
1315 | .ctrlbit = (1 << 4), | |
1316 | }, { | |
1317 | .name = "sromc", | |
1318 | .id = -1, | |
1319 | .parent = &clk_div_d0_bus.clk, | |
1320 | .enable = s5pc100_d0_1_ctrl, | |
1321 | .ctrlbit = (1 << 1), | |
1322 | }, { | |
1323 | .name = "dmc", | |
1324 | .id = -1, | |
1325 | .parent = &clk_div_d0_bus.clk, | |
1326 | .enable = s5pc100_d0_1_ctrl, | |
1327 | .ctrlbit = (1 << 0), | |
1328 | }, { | |
1329 | .name = "chipid", | |
1330 | .id = -1, | |
1331 | .parent = &clk_div_d0_bus.clk, | |
1332 | .enable = s5pc100_d0_1_ctrl, | |
1333 | .ctrlbit = (1 << 0), | |
1334 | }, { | |
1335 | .name = "gpio", | |
1336 | .id = -1, | |
1337 | .parent = &clk_div_d1_bus.clk, | |
1338 | .enable = s5pc100_d1_3_ctrl, | |
1339 | .ctrlbit = (1 << 1), | |
1340 | }, { | |
1341 | .name = "uart", | |
1342 | .id = 0, | |
1343 | .parent = &clk_div_d1_bus.clk, | |
1344 | .enable = s5pc100_d1_4_ctrl, | |
1345 | .ctrlbit = (1 << 0), | |
1346 | }, { | |
1347 | .name = "uart", | |
1348 | .id = 1, | |
1349 | .parent = &clk_div_d1_bus.clk, | |
1350 | .enable = s5pc100_d1_4_ctrl, | |
1351 | .ctrlbit = (1 << 1), | |
1352 | }, { | |
1353 | .name = "uart", | |
1354 | .id = 2, | |
1355 | .parent = &clk_div_d1_bus.clk, | |
1356 | .enable = s5pc100_d1_4_ctrl, | |
1357 | .ctrlbit = (1 << 2), | |
1358 | }, { | |
1359 | .name = "uart", | |
1360 | .id = 3, | |
1361 | .parent = &clk_div_d1_bus.clk, | |
1362 | .enable = s5pc100_d1_4_ctrl, | |
1363 | .ctrlbit = (1 << 3), | |
1364 | }, { | |
1365 | .name = "timers", | |
1366 | .id = -1, | |
1367 | .parent = &clk_div_d1_bus.clk, | |
1368 | .enable = s5pc100_d1_3_ctrl, | |
1369 | .ctrlbit = (1 << 6), | |
1370 | }, | |
1371 | }; | |
1372 | ||
1373 | static struct clk *clks[] __initdata = { | |
1374 | &clk_ext, | |
1375 | &clk_i2scdclk0, | |
1376 | &clk_i2scdclk1, | |
1377 | &clk_i2scdclk2, | |
1378 | &clk_pcmcdclk0, | |
1379 | &clk_pcmcdclk1, | |
1380 | }; | |
1381 | ||
1382 | void __init s5pc100_register_clocks(void) | |
1383 | { | |
1384 | struct clk *clkp; | |
1385 | int ret; | |
1386 | int ptr; | |
1387 | ||
1388 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | |
1389 | ||
1390 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | |
1391 | s3c_register_clksrc(sysclks[ptr], 1); | |
1392 | ||
1393 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | |
1394 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
1395 | ||
1396 | clkp = init_clocks_disable; | |
1397 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | |
1398 | ||
1399 | ret = s3c24xx_register_clock(clkp); | |
1400 | if (ret < 0) { | |
1401 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | |
1402 | clkp->name, ret); | |
1403 | } | |
1404 | (clkp->enable)(clkp, 0); | |
1405 | } | |
1406 | ||
1407 | s3c_pwmclk_init(); | |
1408 | } |