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1 | /* linux/arch/arm/mach-s5pc100/dev-spi.c |
2 | * | |
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
4 | * Jaswinder Singh <jassi.brar@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
12 | #include <linux/dma-mapping.h> | |
1c739c7f | 13 | #include <linux/gpio.h> |
7c3943f6 JB |
14 | |
15 | #include <mach/dma.h> | |
16 | #include <mach/map.h> | |
7c3943f6 | 17 | #include <mach/spi-clocks.h> |
8fa9dd04 | 18 | #include <mach/irqs.h> |
7c3943f6 JB |
19 | |
20 | #include <plat/s3c64xx-spi.h> | |
21 | #include <plat/gpio-cfg.h> | |
22 | #include <plat/irqs.h> | |
23 | ||
24 | static char *spi_src_clks[] = { | |
25 | [S5PC100_SPI_SRCCLK_PCLK] = "pclk", | |
26 | [S5PC100_SPI_SRCCLK_48M] = "spi_48m", | |
27 | [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus", | |
28 | }; | |
29 | ||
30 | /* SPI Controller platform_devices */ | |
31 | ||
32 | /* Since we emulate multi-cs capability, we do not touch the CS. | |
33 | * The emulated CS is toggled by board specific mechanism, as it can | |
34 | * be either some immediate GPIO or some signal out of some other | |
35 | * chip in between ... or some yet another way. | |
36 | * We simply do not assume anything about CS. | |
37 | */ | |
38 | static int s5pc100_spi_cfg_gpio(struct platform_device *pdev) | |
39 | { | |
40 | switch (pdev->id) { | |
41 | case 0: | |
e27ecd73 KK |
42 | s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, |
43 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | |
7c3943f6 JB |
44 | break; |
45 | ||
46 | case 1: | |
e27ecd73 KK |
47 | s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, |
48 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | |
7c3943f6 JB |
49 | break; |
50 | ||
51 | case 2: | |
52 | s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); | |
7c3943f6 | 53 | s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); |
e27ecd73 KK |
54 | s3c_gpio_cfgall_range(S5PC100_GPB(2), 2, |
55 | S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); | |
7c3943f6 JB |
56 | break; |
57 | ||
58 | default: | |
59 | dev_err(&pdev->dev, "Invalid SPI Controller number!"); | |
60 | return -EINVAL; | |
61 | } | |
62 | ||
63 | return 0; | |
64 | } | |
65 | ||
66 | static struct resource s5pc100_spi0_resource[] = { | |
67 | [0] = { | |
68 | .start = S5PC100_PA_SPI0, | |
69 | .end = S5PC100_PA_SPI0 + 0x100 - 1, | |
70 | .flags = IORESOURCE_MEM, | |
71 | }, | |
72 | [1] = { | |
73 | .start = DMACH_SPI0_TX, | |
74 | .end = DMACH_SPI0_TX, | |
75 | .flags = IORESOURCE_DMA, | |
76 | }, | |
77 | [2] = { | |
78 | .start = DMACH_SPI0_RX, | |
79 | .end = DMACH_SPI0_RX, | |
80 | .flags = IORESOURCE_DMA, | |
81 | }, | |
82 | [3] = { | |
83 | .start = IRQ_SPI0, | |
84 | .end = IRQ_SPI0, | |
85 | .flags = IORESOURCE_IRQ, | |
86 | }, | |
87 | }; | |
88 | ||
89 | static struct s3c64xx_spi_info s5pc100_spi0_pdata = { | |
90 | .cfg_gpio = s5pc100_spi_cfg_gpio, | |
91 | .fifo_lvl_mask = 0x7f, | |
92 | .rx_lvl_offset = 13, | |
93 | .high_speed = 1, | |
94 | }; | |
95 | ||
96 | static u64 spi_dmamask = DMA_BIT_MASK(32); | |
97 | ||
98 | struct platform_device s5pc100_device_spi0 = { | |
99 | .name = "s3c64xx-spi", | |
100 | .id = 0, | |
101 | .num_resources = ARRAY_SIZE(s5pc100_spi0_resource), | |
102 | .resource = s5pc100_spi0_resource, | |
103 | .dev = { | |
104 | .dma_mask = &spi_dmamask, | |
105 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
106 | .platform_data = &s5pc100_spi0_pdata, | |
107 | }, | |
108 | }; | |
109 | ||
110 | static struct resource s5pc100_spi1_resource[] = { | |
111 | [0] = { | |
112 | .start = S5PC100_PA_SPI1, | |
113 | .end = S5PC100_PA_SPI1 + 0x100 - 1, | |
114 | .flags = IORESOURCE_MEM, | |
115 | }, | |
116 | [1] = { | |
117 | .start = DMACH_SPI1_TX, | |
118 | .end = DMACH_SPI1_TX, | |
119 | .flags = IORESOURCE_DMA, | |
120 | }, | |
121 | [2] = { | |
122 | .start = DMACH_SPI1_RX, | |
123 | .end = DMACH_SPI1_RX, | |
124 | .flags = IORESOURCE_DMA, | |
125 | }, | |
126 | [3] = { | |
127 | .start = IRQ_SPI1, | |
128 | .end = IRQ_SPI1, | |
129 | .flags = IORESOURCE_IRQ, | |
130 | }, | |
131 | }; | |
132 | ||
133 | static struct s3c64xx_spi_info s5pc100_spi1_pdata = { | |
134 | .cfg_gpio = s5pc100_spi_cfg_gpio, | |
135 | .fifo_lvl_mask = 0x7f, | |
136 | .rx_lvl_offset = 13, | |
137 | .high_speed = 1, | |
138 | }; | |
139 | ||
140 | struct platform_device s5pc100_device_spi1 = { | |
141 | .name = "s3c64xx-spi", | |
142 | .id = 1, | |
143 | .num_resources = ARRAY_SIZE(s5pc100_spi1_resource), | |
144 | .resource = s5pc100_spi1_resource, | |
145 | .dev = { | |
146 | .dma_mask = &spi_dmamask, | |
147 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
148 | .platform_data = &s5pc100_spi1_pdata, | |
149 | }, | |
150 | }; | |
151 | ||
152 | static struct resource s5pc100_spi2_resource[] = { | |
153 | [0] = { | |
154 | .start = S5PC100_PA_SPI2, | |
155 | .end = S5PC100_PA_SPI2 + 0x100 - 1, | |
156 | .flags = IORESOURCE_MEM, | |
157 | }, | |
158 | [1] = { | |
159 | .start = DMACH_SPI2_TX, | |
160 | .end = DMACH_SPI2_TX, | |
161 | .flags = IORESOURCE_DMA, | |
162 | }, | |
163 | [2] = { | |
164 | .start = DMACH_SPI2_RX, | |
165 | .end = DMACH_SPI2_RX, | |
166 | .flags = IORESOURCE_DMA, | |
167 | }, | |
168 | [3] = { | |
169 | .start = IRQ_SPI2, | |
170 | .end = IRQ_SPI2, | |
171 | .flags = IORESOURCE_IRQ, | |
172 | }, | |
173 | }; | |
174 | ||
175 | static struct s3c64xx_spi_info s5pc100_spi2_pdata = { | |
176 | .cfg_gpio = s5pc100_spi_cfg_gpio, | |
177 | .fifo_lvl_mask = 0x7f, | |
178 | .rx_lvl_offset = 13, | |
179 | .high_speed = 1, | |
180 | }; | |
181 | ||
182 | struct platform_device s5pc100_device_spi2 = { | |
183 | .name = "s3c64xx-spi", | |
184 | .id = 2, | |
185 | .num_resources = ARRAY_SIZE(s5pc100_spi2_resource), | |
186 | .resource = s5pc100_spi2_resource, | |
187 | .dev = { | |
188 | .dma_mask = &spi_dmamask, | |
189 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
190 | .platform_data = &s5pc100_spi2_pdata, | |
191 | }, | |
192 | }; | |
193 | ||
194 | void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) | |
195 | { | |
196 | struct s3c64xx_spi_info *pd; | |
197 | ||
198 | /* Reject invalid configuration */ | |
199 | if (!num_cs || src_clk_nr < 0 | |
200 | || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) { | |
201 | printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); | |
202 | return; | |
203 | } | |
204 | ||
205 | switch (cntrlr) { | |
206 | case 0: | |
207 | pd = &s5pc100_spi0_pdata; | |
208 | break; | |
209 | case 1: | |
210 | pd = &s5pc100_spi1_pdata; | |
211 | break; | |
212 | case 2: | |
213 | pd = &s5pc100_spi2_pdata; | |
214 | break; | |
215 | default: | |
216 | printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", | |
217 | __func__, cntrlr); | |
218 | return; | |
219 | } | |
220 | ||
221 | pd->num_cs = num_cs; | |
222 | pd->src_clk_nr = src_clk_nr; | |
223 | pd->src_clk_name = spi_src_clks[src_clk_nr]; | |
224 | } |