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0c1945d3 KK |
1 | /* linux/arch/arm/mach-s5pv210/clock.c |
2 | * | |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
5 | * | |
6 | * S5PV210 - Clock support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/sysdev.h> | |
21 | #include <linux/io.h> | |
22 | ||
23 | #include <mach/map.h> | |
24 | ||
25 | #include <plat/cpu-freq.h> | |
26 | #include <mach/regs-clock.h> | |
27 | #include <plat/clock.h> | |
28 | #include <plat/cpu.h> | |
29 | #include <plat/pll.h> | |
30 | #include <plat/s5p-clock.h> | |
31 | #include <plat/clock-clksrc.h> | |
32 | #include <plat/s5pv210.h> | |
33 | ||
88695843 JL |
34 | static unsigned long xtal; |
35 | ||
59cda520 TA |
36 | static struct clksrc_clk clk_mout_apll = { |
37 | .clk = { | |
38 | .name = "mout_apll", | |
59cda520 TA |
39 | }, |
40 | .sources = &clk_src_apll, | |
41 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | |
42 | }; | |
43 | ||
44 | static struct clksrc_clk clk_mout_epll = { | |
45 | .clk = { | |
46 | .name = "mout_epll", | |
59cda520 TA |
47 | }, |
48 | .sources = &clk_src_epll, | |
49 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | |
50 | }; | |
51 | ||
52 | static struct clksrc_clk clk_mout_mpll = { | |
53 | .clk = { | |
54 | .name = "mout_mpll", | |
59cda520 TA |
55 | }, |
56 | .sources = &clk_src_mpll, | |
57 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | |
58 | }; | |
59 | ||
374e0bf5 TA |
60 | static struct clk *clkset_armclk_list[] = { |
61 | [0] = &clk_mout_apll.clk, | |
62 | [1] = &clk_mout_mpll.clk, | |
63 | }; | |
64 | ||
65 | static struct clksrc_sources clkset_armclk = { | |
66 | .sources = clkset_armclk_list, | |
67 | .nr_sources = ARRAY_SIZE(clkset_armclk_list), | |
68 | }; | |
69 | ||
70 | static struct clksrc_clk clk_armclk = { | |
71 | .clk = { | |
72 | .name = "armclk", | |
374e0bf5 TA |
73 | }, |
74 | .sources = &clkset_armclk, | |
75 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | |
76 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, | |
77 | }; | |
78 | ||
af76a201 TA |
79 | static struct clksrc_clk clk_hclk_msys = { |
80 | .clk = { | |
81 | .name = "hclk_msys", | |
af76a201 TA |
82 | .parent = &clk_armclk.clk, |
83 | }, | |
84 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | |
85 | }; | |
86 | ||
6ed91a20 TA |
87 | static struct clksrc_clk clk_pclk_msys = { |
88 | .clk = { | |
89 | .name = "pclk_msys", | |
6ed91a20 TA |
90 | .parent = &clk_hclk_msys.clk, |
91 | }, | |
92 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | |
93 | }; | |
94 | ||
0fe967a1 TA |
95 | static struct clksrc_clk clk_sclk_a2m = { |
96 | .clk = { | |
97 | .name = "sclk_a2m", | |
0fe967a1 TA |
98 | .parent = &clk_mout_apll.clk, |
99 | }, | |
100 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | |
101 | }; | |
102 | ||
103 | static struct clk *clkset_hclk_sys_list[] = { | |
104 | [0] = &clk_mout_mpll.clk, | |
105 | [1] = &clk_sclk_a2m.clk, | |
106 | }; | |
107 | ||
108 | static struct clksrc_sources clkset_hclk_sys = { | |
109 | .sources = clkset_hclk_sys_list, | |
110 | .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list), | |
111 | }; | |
112 | ||
113 | static struct clksrc_clk clk_hclk_dsys = { | |
114 | .clk = { | |
115 | .name = "hclk_dsys", | |
0fe967a1 TA |
116 | }, |
117 | .sources = &clkset_hclk_sys, | |
118 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | |
119 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, | |
120 | }; | |
121 | ||
58772cd3 TA |
122 | static struct clksrc_clk clk_pclk_dsys = { |
123 | .clk = { | |
124 | .name = "pclk_dsys", | |
58772cd3 TA |
125 | .parent = &clk_hclk_dsys.clk, |
126 | }, | |
127 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, | |
128 | }; | |
129 | ||
acfa245f TA |
130 | static struct clksrc_clk clk_hclk_psys = { |
131 | .clk = { | |
132 | .name = "hclk_psys", | |
acfa245f TA |
133 | }, |
134 | .sources = &clkset_hclk_sys, | |
135 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | |
136 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, | |
137 | }; | |
138 | ||
f44cf78b TA |
139 | static struct clksrc_clk clk_pclk_psys = { |
140 | .clk = { | |
141 | .name = "pclk_psys", | |
f44cf78b TA |
142 | .parent = &clk_hclk_psys.clk, |
143 | }, | |
144 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, | |
145 | }; | |
146 | ||
0c1945d3 KK |
147 | static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) |
148 | { | |
149 | return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); | |
150 | } | |
151 | ||
152 | static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable) | |
153 | { | |
154 | return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable); | |
155 | } | |
156 | ||
157 | static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable) | |
158 | { | |
159 | return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable); | |
160 | } | |
161 | ||
162 | static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) | |
163 | { | |
164 | return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); | |
165 | } | |
166 | ||
f445dbd5 TA |
167 | static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) |
168 | { | |
169 | return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); | |
170 | } | |
171 | ||
154d62e4 MH |
172 | static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) |
173 | { | |
174 | return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); | |
175 | } | |
176 | ||
f445dbd5 TA |
177 | static struct clk clk_sclk_hdmi27m = { |
178 | .name = "sclk_hdmi27m", | |
f445dbd5 TA |
179 | .rate = 27000000, |
180 | }; | |
181 | ||
2cf4c2e6 TA |
182 | static struct clk clk_sclk_hdmiphy = { |
183 | .name = "sclk_hdmiphy", | |
2cf4c2e6 TA |
184 | }; |
185 | ||
186 | static struct clk clk_sclk_usbphy0 = { | |
187 | .name = "sclk_usbphy0", | |
2cf4c2e6 TA |
188 | }; |
189 | ||
190 | static struct clk clk_sclk_usbphy1 = { | |
191 | .name = "sclk_usbphy1", | |
2cf4c2e6 TA |
192 | }; |
193 | ||
4583487c TA |
194 | static struct clk clk_pcmcdclk0 = { |
195 | .name = "pcmcdclk", | |
4583487c TA |
196 | }; |
197 | ||
198 | static struct clk clk_pcmcdclk1 = { | |
199 | .name = "pcmcdclk", | |
4583487c TA |
200 | }; |
201 | ||
202 | static struct clk clk_pcmcdclk2 = { | |
203 | .name = "pcmcdclk", | |
4583487c TA |
204 | }; |
205 | ||
f445dbd5 TA |
206 | static struct clk *clkset_vpllsrc_list[] = { |
207 | [0] = &clk_fin_vpll, | |
208 | [1] = &clk_sclk_hdmi27m, | |
209 | }; | |
210 | ||
211 | static struct clksrc_sources clkset_vpllsrc = { | |
212 | .sources = clkset_vpllsrc_list, | |
213 | .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), | |
214 | }; | |
215 | ||
216 | static struct clksrc_clk clk_vpllsrc = { | |
217 | .clk = { | |
218 | .name = "vpll_src", | |
f445dbd5 TA |
219 | .enable = s5pv210_clk_mask0_ctrl, |
220 | .ctrlbit = (1 << 7), | |
221 | }, | |
222 | .sources = &clkset_vpllsrc, | |
223 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 }, | |
224 | }; | |
225 | ||
226 | static struct clk *clkset_sclk_vpll_list[] = { | |
227 | [0] = &clk_vpllsrc.clk, | |
228 | [1] = &clk_fout_vpll, | |
229 | }; | |
230 | ||
231 | static struct clksrc_sources clkset_sclk_vpll = { | |
232 | .sources = clkset_sclk_vpll_list, | |
233 | .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), | |
234 | }; | |
235 | ||
236 | static struct clksrc_clk clk_sclk_vpll = { | |
237 | .clk = { | |
238 | .name = "sclk_vpll", | |
f445dbd5 TA |
239 | }, |
240 | .sources = &clkset_sclk_vpll, | |
241 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | |
242 | }; | |
243 | ||
08f49d11 JL |
244 | static struct clk *clkset_moutdmc0src_list[] = { |
245 | [0] = &clk_sclk_a2m.clk, | |
246 | [1] = &clk_mout_mpll.clk, | |
247 | [2] = NULL, | |
248 | [3] = NULL, | |
249 | }; | |
250 | ||
251 | static struct clksrc_sources clkset_moutdmc0src = { | |
252 | .sources = clkset_moutdmc0src_list, | |
253 | .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list), | |
254 | }; | |
255 | ||
256 | static struct clksrc_clk clk_mout_dmc0 = { | |
257 | .clk = { | |
258 | .name = "mout_dmc0", | |
08f49d11 JL |
259 | }, |
260 | .sources = &clkset_moutdmc0src, | |
261 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, | |
262 | }; | |
263 | ||
264 | static struct clksrc_clk clk_sclk_dmc0 = { | |
265 | .clk = { | |
266 | .name = "sclk_dmc0", | |
08f49d11 JL |
267 | .parent = &clk_mout_dmc0.clk, |
268 | }, | |
269 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, | |
270 | }; | |
271 | ||
664f5b20 TA |
272 | static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) |
273 | { | |
274 | return clk_get_rate(clk->parent) / 2; | |
275 | } | |
276 | ||
277 | static struct clk_ops clk_hclk_imem_ops = { | |
278 | .get_rate = s5pv210_clk_imem_get_rate, | |
279 | }; | |
280 | ||
88695843 JL |
281 | static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk) |
282 | { | |
283 | return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); | |
284 | } | |
285 | ||
286 | static struct clk_ops clk_fout_apll_ops = { | |
287 | .get_rate = s5pv210_clk_fout_apll_get_rate, | |
288 | }; | |
289 | ||
3c0fa647 | 290 | static struct clk init_clocks_off[] = { |
0c1945d3 | 291 | { |
313068fd | 292 | .name = "pdma", |
1ce3ea61 | 293 | .devname = "dma-pl330.0", |
313068fd SY |
294 | .parent = &clk_hclk_psys.clk, |
295 | .enable = s5pv210_clk_ip0_ctrl, | |
296 | .ctrlbit = (1 << 3), | |
297 | }, { | |
298 | .name = "pdma", | |
1ce3ea61 | 299 | .devname = "dma-pl330.1", |
313068fd SY |
300 | .parent = &clk_hclk_psys.clk, |
301 | .enable = s5pv210_clk_ip0_ctrl, | |
302 | .ctrlbit = (1 << 4), | |
303 | }, { | |
0c1945d3 | 304 | .name = "rot", |
0fe967a1 | 305 | .parent = &clk_hclk_dsys.clk, |
0c1945d3 KK |
306 | .enable = s5pv210_clk_ip0_ctrl, |
307 | .ctrlbit = (1<<29), | |
da01c2f7 MS |
308 | }, { |
309 | .name = "fimc", | |
b2a9dd46 | 310 | .devname = "s5pv210-fimc.0", |
da01c2f7 MS |
311 | .parent = &clk_hclk_dsys.clk, |
312 | .enable = s5pv210_clk_ip0_ctrl, | |
313 | .ctrlbit = (1 << 24), | |
314 | }, { | |
315 | .name = "fimc", | |
b2a9dd46 | 316 | .devname = "s5pv210-fimc.1", |
da01c2f7 MS |
317 | .parent = &clk_hclk_dsys.clk, |
318 | .enable = s5pv210_clk_ip0_ctrl, | |
319 | .ctrlbit = (1 << 25), | |
320 | }, { | |
321 | .name = "fimc", | |
b2a9dd46 | 322 | .devname = "s5pv210-fimc.2", |
da01c2f7 MS |
323 | .parent = &clk_hclk_dsys.clk, |
324 | .enable = s5pv210_clk_ip0_ctrl, | |
325 | .ctrlbit = (1 << 26), | |
0f75a96b KD |
326 | }, { |
327 | .name = "mfc", | |
328 | .devname = "s5p-mfc", | |
329 | .parent = &clk_pclk_psys.clk, | |
330 | .enable = s5pv210_clk_ip0_ctrl, | |
331 | .ctrlbit = (1 << 16), | |
0c1945d3 KK |
332 | }, { |
333 | .name = "otg", | |
acfa245f | 334 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
335 | .enable = s5pv210_clk_ip1_ctrl, |
336 | .ctrlbit = (1<<16), | |
337 | }, { | |
338 | .name = "usb-host", | |
acfa245f | 339 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
340 | .enable = s5pv210_clk_ip1_ctrl, |
341 | .ctrlbit = (1<<17), | |
342 | }, { | |
343 | .name = "lcd", | |
0fe967a1 | 344 | .parent = &clk_hclk_dsys.clk, |
0c1945d3 KK |
345 | .enable = s5pv210_clk_ip1_ctrl, |
346 | .ctrlbit = (1<<0), | |
347 | }, { | |
348 | .name = "cfcon", | |
acfa245f | 349 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
350 | .enable = s5pv210_clk_ip1_ctrl, |
351 | .ctrlbit = (1<<25), | |
352 | }, { | |
353 | .name = "hsmmc", | |
b2a9dd46 | 354 | .devname = "s3c-sdhci.0", |
acfa245f | 355 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
356 | .enable = s5pv210_clk_ip2_ctrl, |
357 | .ctrlbit = (1<<16), | |
358 | }, { | |
359 | .name = "hsmmc", | |
b2a9dd46 | 360 | .devname = "s3c-sdhci.1", |
acfa245f | 361 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
362 | .enable = s5pv210_clk_ip2_ctrl, |
363 | .ctrlbit = (1<<17), | |
364 | }, { | |
365 | .name = "hsmmc", | |
b2a9dd46 | 366 | .devname = "s3c-sdhci.2", |
acfa245f | 367 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
368 | .enable = s5pv210_clk_ip2_ctrl, |
369 | .ctrlbit = (1<<18), | |
370 | }, { | |
371 | .name = "hsmmc", | |
b2a9dd46 | 372 | .devname = "s3c-sdhci.3", |
acfa245f | 373 | .parent = &clk_hclk_psys.clk, |
0c1945d3 KK |
374 | .enable = s5pv210_clk_ip2_ctrl, |
375 | .ctrlbit = (1<<19), | |
376 | }, { | |
377 | .name = "systimer", | |
f44cf78b | 378 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
379 | .enable = s5pv210_clk_ip3_ctrl, |
380 | .ctrlbit = (1<<16), | |
381 | }, { | |
382 | .name = "watchdog", | |
f44cf78b | 383 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
384 | .enable = s5pv210_clk_ip3_ctrl, |
385 | .ctrlbit = (1<<22), | |
386 | }, { | |
387 | .name = "rtc", | |
f44cf78b | 388 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
389 | .enable = s5pv210_clk_ip3_ctrl, |
390 | .ctrlbit = (1<<15), | |
391 | }, { | |
392 | .name = "i2c", | |
b2a9dd46 | 393 | .devname = "s3c2440-i2c.0", |
f44cf78b | 394 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
395 | .enable = s5pv210_clk_ip3_ctrl, |
396 | .ctrlbit = (1<<7), | |
397 | }, { | |
398 | .name = "i2c", | |
b2a9dd46 | 399 | .devname = "s3c2440-i2c.1", |
f44cf78b | 400 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 401 | .enable = s5pv210_clk_ip3_ctrl, |
f1c894de | 402 | .ctrlbit = (1 << 10), |
0c1945d3 KK |
403 | }, { |
404 | .name = "i2c", | |
b2a9dd46 | 405 | .devname = "s3c2440-i2c.2", |
f44cf78b | 406 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
407 | .enable = s5pv210_clk_ip3_ctrl, |
408 | .ctrlbit = (1<<9), | |
409 | }, { | |
410 | .name = "spi", | |
b2a9dd46 | 411 | .devname = "s3c64xx-spi.0", |
f44cf78b | 412 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
413 | .enable = s5pv210_clk_ip3_ctrl, |
414 | .ctrlbit = (1<<12), | |
415 | }, { | |
416 | .name = "spi", | |
b2a9dd46 | 417 | .devname = "s3c64xx-spi.1", |
f44cf78b | 418 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
419 | .enable = s5pv210_clk_ip3_ctrl, |
420 | .ctrlbit = (1<<13), | |
421 | }, { | |
422 | .name = "spi", | |
b2a9dd46 | 423 | .devname = "s3c64xx-spi.2", |
f44cf78b | 424 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
425 | .enable = s5pv210_clk_ip3_ctrl, |
426 | .ctrlbit = (1<<14), | |
427 | }, { | |
428 | .name = "timers", | |
f44cf78b | 429 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
430 | .enable = s5pv210_clk_ip3_ctrl, |
431 | .ctrlbit = (1<<23), | |
432 | }, { | |
433 | .name = "adc", | |
f44cf78b | 434 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
435 | .enable = s5pv210_clk_ip3_ctrl, |
436 | .ctrlbit = (1<<24), | |
437 | }, { | |
438 | .name = "keypad", | |
f44cf78b | 439 | .parent = &clk_pclk_psys.clk, |
0c1945d3 KK |
440 | .enable = s5pv210_clk_ip3_ctrl, |
441 | .ctrlbit = (1<<21), | |
442 | }, { | |
9aa2570e | 443 | .name = "iis", |
b2a9dd46 | 444 | .devname = "samsung-i2s.0", |
0c1945d3 KK |
445 | .parent = &clk_p, |
446 | .enable = s5pv210_clk_ip3_ctrl, | |
447 | .ctrlbit = (1<<4), | |
448 | }, { | |
9aa2570e | 449 | .name = "iis", |
b2a9dd46 | 450 | .devname = "samsung-i2s.1", |
0c1945d3 KK |
451 | .parent = &clk_p, |
452 | .enable = s5pv210_clk_ip3_ctrl, | |
154d62e4 | 453 | .ctrlbit = (1 << 5), |
0c1945d3 | 454 | }, { |
9aa2570e | 455 | .name = "iis", |
b2a9dd46 | 456 | .devname = "samsung-i2s.2", |
0c1945d3 KK |
457 | .parent = &clk_p, |
458 | .enable = s5pv210_clk_ip3_ctrl, | |
154d62e4 | 459 | .ctrlbit = (1 << 6), |
aa21ae3d SY |
460 | }, { |
461 | .name = "spdif", | |
aa21ae3d SY |
462 | .parent = &clk_p, |
463 | .enable = s5pv210_clk_ip3_ctrl, | |
464 | .ctrlbit = (1 << 0), | |
154d62e4 | 465 | }, |
0c1945d3 KK |
466 | }; |
467 | ||
468 | static struct clk init_clocks[] = { | |
469 | { | |
664f5b20 | 470 | .name = "hclk_imem", |
664f5b20 TA |
471 | .parent = &clk_hclk_msys.clk, |
472 | .ctrlbit = (1 << 5), | |
473 | .enable = s5pv210_clk_ip0_ctrl, | |
474 | .ops = &clk_hclk_imem_ops, | |
475 | }, { | |
0c1945d3 | 476 | .name = "uart", |
b2a9dd46 | 477 | .devname = "s5pv210-uart.0", |
f44cf78b | 478 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 479 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 480 | .ctrlbit = (1 << 17), |
0c1945d3 KK |
481 | }, { |
482 | .name = "uart", | |
b2a9dd46 | 483 | .devname = "s5pv210-uart.1", |
f44cf78b | 484 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 485 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 486 | .ctrlbit = (1 << 18), |
0c1945d3 KK |
487 | }, { |
488 | .name = "uart", | |
b2a9dd46 | 489 | .devname = "s5pv210-uart.2", |
f44cf78b | 490 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 491 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 492 | .ctrlbit = (1 << 19), |
0c1945d3 KK |
493 | }, { |
494 | .name = "uart", | |
b2a9dd46 | 495 | .devname = "s5pv210-uart.3", |
f44cf78b | 496 | .parent = &clk_pclk_psys.clk, |
0c1945d3 | 497 | .enable = s5pv210_clk_ip3_ctrl, |
154d62e4 | 498 | .ctrlbit = (1 << 20), |
81f9becd TA |
499 | }, { |
500 | .name = "sromc", | |
81f9becd TA |
501 | .parent = &clk_hclk_psys.clk, |
502 | .enable = s5pv210_clk_ip1_ctrl, | |
503 | .ctrlbit = (1 << 26), | |
0c1945d3 KK |
504 | }, |
505 | }; | |
506 | ||
0c1945d3 KK |
507 | static struct clk *clkset_uart_list[] = { |
508 | [6] = &clk_mout_mpll.clk, | |
509 | [7] = &clk_mout_epll.clk, | |
510 | }; | |
511 | ||
512 | static struct clksrc_sources clkset_uart = { | |
513 | .sources = clkset_uart_list, | |
514 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | |
515 | }; | |
516 | ||
2cf4c2e6 TA |
517 | static struct clk *clkset_group1_list[] = { |
518 | [0] = &clk_sclk_a2m.clk, | |
519 | [1] = &clk_mout_mpll.clk, | |
520 | [2] = &clk_mout_epll.clk, | |
521 | [3] = &clk_sclk_vpll.clk, | |
522 | }; | |
523 | ||
524 | static struct clksrc_sources clkset_group1 = { | |
525 | .sources = clkset_group1_list, | |
526 | .nr_sources = ARRAY_SIZE(clkset_group1_list), | |
527 | }; | |
528 | ||
529 | static struct clk *clkset_sclk_onenand_list[] = { | |
530 | [0] = &clk_hclk_psys.clk, | |
531 | [1] = &clk_hclk_dsys.clk, | |
532 | }; | |
533 | ||
534 | static struct clksrc_sources clkset_sclk_onenand = { | |
535 | .sources = clkset_sclk_onenand_list, | |
536 | .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list), | |
537 | }; | |
538 | ||
9e20614b TA |
539 | static struct clk *clkset_sclk_dac_list[] = { |
540 | [0] = &clk_sclk_vpll.clk, | |
541 | [1] = &clk_sclk_hdmiphy, | |
542 | }; | |
543 | ||
544 | static struct clksrc_sources clkset_sclk_dac = { | |
545 | .sources = clkset_sclk_dac_list, | |
546 | .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), | |
547 | }; | |
548 | ||
549 | static struct clksrc_clk clk_sclk_dac = { | |
550 | .clk = { | |
551 | .name = "sclk_dac", | |
154d62e4 MH |
552 | .enable = s5pv210_clk_mask0_ctrl, |
553 | .ctrlbit = (1 << 2), | |
9e20614b TA |
554 | }, |
555 | .sources = &clkset_sclk_dac, | |
556 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, | |
557 | }; | |
558 | ||
559 | static struct clksrc_clk clk_sclk_pixel = { | |
560 | .clk = { | |
561 | .name = "sclk_pixel", | |
9e20614b TA |
562 | .parent = &clk_sclk_vpll.clk, |
563 | }, | |
564 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, | |
565 | }; | |
566 | ||
567 | static struct clk *clkset_sclk_hdmi_list[] = { | |
568 | [0] = &clk_sclk_pixel.clk, | |
569 | [1] = &clk_sclk_hdmiphy, | |
570 | }; | |
571 | ||
572 | static struct clksrc_sources clkset_sclk_hdmi = { | |
573 | .sources = clkset_sclk_hdmi_list, | |
574 | .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), | |
575 | }; | |
576 | ||
577 | static struct clksrc_clk clk_sclk_hdmi = { | |
578 | .clk = { | |
579 | .name = "sclk_hdmi", | |
154d62e4 MH |
580 | .enable = s5pv210_clk_mask0_ctrl, |
581 | .ctrlbit = (1 << 0), | |
9e20614b TA |
582 | }, |
583 | .sources = &clkset_sclk_hdmi, | |
584 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, | |
585 | }; | |
586 | ||
587 | static struct clk *clkset_sclk_mixer_list[] = { | |
588 | [0] = &clk_sclk_dac.clk, | |
589 | [1] = &clk_sclk_hdmi.clk, | |
590 | }; | |
591 | ||
592 | static struct clksrc_sources clkset_sclk_mixer = { | |
593 | .sources = clkset_sclk_mixer_list, | |
594 | .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), | |
595 | }; | |
596 | ||
4583487c TA |
597 | static struct clk *clkset_sclk_audio0_list[] = { |
598 | [0] = &clk_ext_xtal_mux, | |
599 | [1] = &clk_pcmcdclk0, | |
600 | [2] = &clk_sclk_hdmi27m, | |
601 | [3] = &clk_sclk_usbphy0, | |
602 | [4] = &clk_sclk_usbphy1, | |
603 | [5] = &clk_sclk_hdmiphy, | |
604 | [6] = &clk_mout_mpll.clk, | |
605 | [7] = &clk_mout_epll.clk, | |
606 | [8] = &clk_sclk_vpll.clk, | |
607 | }; | |
608 | ||
609 | static struct clksrc_sources clkset_sclk_audio0 = { | |
610 | .sources = clkset_sclk_audio0_list, | |
611 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), | |
612 | }; | |
613 | ||
614 | static struct clksrc_clk clk_sclk_audio0 = { | |
615 | .clk = { | |
616 | .name = "sclk_audio", | |
b2a9dd46 | 617 | .devname = "soc-audio.0", |
154d62e4 MH |
618 | .enable = s5pv210_clk_mask0_ctrl, |
619 | .ctrlbit = (1 << 24), | |
4583487c TA |
620 | }, |
621 | .sources = &clkset_sclk_audio0, | |
622 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, | |
623 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 }, | |
624 | }; | |
625 | ||
626 | static struct clk *clkset_sclk_audio1_list[] = { | |
627 | [0] = &clk_ext_xtal_mux, | |
628 | [1] = &clk_pcmcdclk1, | |
629 | [2] = &clk_sclk_hdmi27m, | |
630 | [3] = &clk_sclk_usbphy0, | |
631 | [4] = &clk_sclk_usbphy1, | |
632 | [5] = &clk_sclk_hdmiphy, | |
633 | [6] = &clk_mout_mpll.clk, | |
634 | [7] = &clk_mout_epll.clk, | |
635 | [8] = &clk_sclk_vpll.clk, | |
636 | }; | |
637 | ||
638 | static struct clksrc_sources clkset_sclk_audio1 = { | |
639 | .sources = clkset_sclk_audio1_list, | |
640 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list), | |
641 | }; | |
642 | ||
643 | static struct clksrc_clk clk_sclk_audio1 = { | |
644 | .clk = { | |
645 | .name = "sclk_audio", | |
b2a9dd46 | 646 | .devname = "soc-audio.1", |
154d62e4 MH |
647 | .enable = s5pv210_clk_mask0_ctrl, |
648 | .ctrlbit = (1 << 25), | |
4583487c TA |
649 | }, |
650 | .sources = &clkset_sclk_audio1, | |
651 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, | |
652 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 }, | |
653 | }; | |
654 | ||
655 | static struct clk *clkset_sclk_audio2_list[] = { | |
656 | [0] = &clk_ext_xtal_mux, | |
657 | [1] = &clk_pcmcdclk0, | |
658 | [2] = &clk_sclk_hdmi27m, | |
659 | [3] = &clk_sclk_usbphy0, | |
660 | [4] = &clk_sclk_usbphy1, | |
661 | [5] = &clk_sclk_hdmiphy, | |
662 | [6] = &clk_mout_mpll.clk, | |
663 | [7] = &clk_mout_epll.clk, | |
664 | [8] = &clk_sclk_vpll.clk, | |
665 | }; | |
666 | ||
667 | static struct clksrc_sources clkset_sclk_audio2 = { | |
668 | .sources = clkset_sclk_audio2_list, | |
669 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list), | |
670 | }; | |
671 | ||
672 | static struct clksrc_clk clk_sclk_audio2 = { | |
673 | .clk = { | |
674 | .name = "sclk_audio", | |
b2a9dd46 | 675 | .devname = "soc-audio.2", |
154d62e4 MH |
676 | .enable = s5pv210_clk_mask0_ctrl, |
677 | .ctrlbit = (1 << 26), | |
4583487c TA |
678 | }, |
679 | .sources = &clkset_sclk_audio2, | |
680 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, | |
681 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 }, | |
682 | }; | |
683 | ||
684 | static struct clk *clkset_sclk_spdif_list[] = { | |
685 | [0] = &clk_sclk_audio0.clk, | |
686 | [1] = &clk_sclk_audio1.clk, | |
687 | [2] = &clk_sclk_audio2.clk, | |
688 | }; | |
689 | ||
690 | static struct clksrc_sources clkset_sclk_spdif = { | |
691 | .sources = clkset_sclk_spdif_list, | |
692 | .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), | |
693 | }; | |
694 | ||
aa21ae3d SY |
695 | static struct clksrc_clk clk_sclk_spdif = { |
696 | .clk = { | |
697 | .name = "sclk_spdif", | |
aa21ae3d SY |
698 | .enable = s5pv210_clk_mask0_ctrl, |
699 | .ctrlbit = (1 << 27), | |
65f5eaa2 | 700 | .ops = &s5p_sclk_spdif_ops, |
aa21ae3d SY |
701 | }, |
702 | .sources = &clkset_sclk_spdif, | |
703 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, | |
704 | }; | |
705 | ||
f64cacc3 TA |
706 | static struct clk *clkset_group2_list[] = { |
707 | [0] = &clk_ext_xtal_mux, | |
708 | [1] = &clk_xusbxti, | |
709 | [2] = &clk_sclk_hdmi27m, | |
710 | [3] = &clk_sclk_usbphy0, | |
711 | [4] = &clk_sclk_usbphy1, | |
712 | [5] = &clk_sclk_hdmiphy, | |
713 | [6] = &clk_mout_mpll.clk, | |
714 | [7] = &clk_mout_epll.clk, | |
715 | [8] = &clk_sclk_vpll.clk, | |
716 | }; | |
717 | ||
718 | static struct clksrc_sources clkset_group2 = { | |
719 | .sources = clkset_group2_list, | |
720 | .nr_sources = ARRAY_SIZE(clkset_group2_list), | |
721 | }; | |
722 | ||
0c1945d3 KK |
723 | static struct clksrc_clk clksrcs[] = { |
724 | { | |
2cf4c2e6 TA |
725 | .clk = { |
726 | .name = "sclk_dmc", | |
2cf4c2e6 TA |
727 | }, |
728 | .sources = &clkset_group1, | |
729 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, | |
730 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, | |
731 | }, { | |
732 | .clk = { | |
733 | .name = "sclk_onenand", | |
2cf4c2e6 TA |
734 | }, |
735 | .sources = &clkset_sclk_onenand, | |
736 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, | |
737 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, | |
738 | }, { | |
0c1945d3 KK |
739 | .clk = { |
740 | .name = "uclk1", | |
b2a9dd46 | 741 | .devname = "s5pv210-uart.0", |
154d62e4 MH |
742 | .enable = s5pv210_clk_mask0_ctrl, |
743 | .ctrlbit = (1 << 12), | |
0c1945d3 KK |
744 | }, |
745 | .sources = &clkset_uart, | |
746 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, | |
747 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, | |
f64cacc3 TA |
748 | }, { |
749 | .clk = { | |
750 | .name = "uclk1", | |
b2a9dd46 | 751 | .devname = "s5pv210-uart.1", |
154d62e4 MH |
752 | .enable = s5pv210_clk_mask0_ctrl, |
753 | .ctrlbit = (1 << 13), | |
f64cacc3 TA |
754 | }, |
755 | .sources = &clkset_uart, | |
756 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, | |
757 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, | |
758 | }, { | |
759 | .clk = { | |
760 | .name = "uclk1", | |
b2a9dd46 | 761 | .devname = "s5pv210-uart.2", |
154d62e4 MH |
762 | .enable = s5pv210_clk_mask0_ctrl, |
763 | .ctrlbit = (1 << 14), | |
f64cacc3 TA |
764 | }, |
765 | .sources = &clkset_uart, | |
766 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, | |
767 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, | |
768 | }, { | |
769 | .clk = { | |
770 | .name = "uclk1", | |
b2a9dd46 | 771 | .devname = "s5pv210-uart.3", |
154d62e4 MH |
772 | .enable = s5pv210_clk_mask0_ctrl, |
773 | .ctrlbit = (1 << 15), | |
f64cacc3 TA |
774 | }, |
775 | .sources = &clkset_uart, | |
776 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, | |
777 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, | |
9e20614b TA |
778 | }, { |
779 | .clk = { | |
780 | .name = "sclk_mixer", | |
154d62e4 MH |
781 | .enable = s5pv210_clk_mask0_ctrl, |
782 | .ctrlbit = (1 << 1), | |
9e20614b TA |
783 | }, |
784 | .sources = &clkset_sclk_mixer, | |
785 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, | |
f64cacc3 TA |
786 | }, { |
787 | .clk = { | |
788 | .name = "sclk_fimc", | |
b2a9dd46 | 789 | .devname = "s5pv210-fimc.0", |
154d62e4 MH |
790 | .enable = s5pv210_clk_mask1_ctrl, |
791 | .ctrlbit = (1 << 2), | |
f64cacc3 TA |
792 | }, |
793 | .sources = &clkset_group2, | |
794 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, | |
795 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, | |
796 | }, { | |
797 | .clk = { | |
798 | .name = "sclk_fimc", | |
b2a9dd46 | 799 | .devname = "s5pv210-fimc.1", |
154d62e4 MH |
800 | .enable = s5pv210_clk_mask1_ctrl, |
801 | .ctrlbit = (1 << 3), | |
f64cacc3 TA |
802 | }, |
803 | .sources = &clkset_group2, | |
804 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, | |
805 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, | |
806 | }, { | |
807 | .clk = { | |
808 | .name = "sclk_fimc", | |
b2a9dd46 | 809 | .devname = "s5pv210-fimc.2", |
154d62e4 MH |
810 | .enable = s5pv210_clk_mask1_ctrl, |
811 | .ctrlbit = (1 << 4), | |
f64cacc3 TA |
812 | }, |
813 | .sources = &clkset_group2, | |
814 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, | |
815 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, | |
816 | }, { | |
817 | .clk = { | |
818 | .name = "sclk_cam", | |
b2a9dd46 | 819 | .devname = "s5pv210-fimc.0", |
154d62e4 MH |
820 | .enable = s5pv210_clk_mask0_ctrl, |
821 | .ctrlbit = (1 << 3), | |
f64cacc3 TA |
822 | }, |
823 | .sources = &clkset_group2, | |
824 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, | |
825 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, | |
826 | }, { | |
827 | .clk = { | |
828 | .name = "sclk_cam", | |
b2a9dd46 | 829 | .devname = "s5pv210-fimc.1", |
154d62e4 MH |
830 | .enable = s5pv210_clk_mask0_ctrl, |
831 | .ctrlbit = (1 << 4), | |
f64cacc3 TA |
832 | }, |
833 | .sources = &clkset_group2, | |
834 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, | |
835 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 }, | |
836 | }, { | |
837 | .clk = { | |
838 | .name = "sclk_fimd", | |
154d62e4 MH |
839 | .enable = s5pv210_clk_mask0_ctrl, |
840 | .ctrlbit = (1 << 5), | |
f64cacc3 TA |
841 | }, |
842 | .sources = &clkset_group2, | |
843 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, | |
844 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, | |
845 | }, { | |
846 | .clk = { | |
847 | .name = "sclk_mmc", | |
b2a9dd46 | 848 | .devname = "s3c-sdhci.0", |
154d62e4 MH |
849 | .enable = s5pv210_clk_mask0_ctrl, |
850 | .ctrlbit = (1 << 8), | |
f64cacc3 TA |
851 | }, |
852 | .sources = &clkset_group2, | |
853 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, | |
854 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, | |
855 | }, { | |
856 | .clk = { | |
857 | .name = "sclk_mmc", | |
b2a9dd46 | 858 | .devname = "s3c-sdhci.1", |
154d62e4 MH |
859 | .enable = s5pv210_clk_mask0_ctrl, |
860 | .ctrlbit = (1 << 9), | |
f64cacc3 TA |
861 | }, |
862 | .sources = &clkset_group2, | |
863 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, | |
864 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, | |
865 | }, { | |
866 | .clk = { | |
867 | .name = "sclk_mmc", | |
b2a9dd46 | 868 | .devname = "s3c-sdhci.2", |
154d62e4 MH |
869 | .enable = s5pv210_clk_mask0_ctrl, |
870 | .ctrlbit = (1 << 10), | |
f64cacc3 TA |
871 | }, |
872 | .sources = &clkset_group2, | |
873 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, | |
874 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, | |
875 | }, { | |
876 | .clk = { | |
877 | .name = "sclk_mmc", | |
b2a9dd46 | 878 | .devname = "s3c-sdhci.3", |
154d62e4 MH |
879 | .enable = s5pv210_clk_mask0_ctrl, |
880 | .ctrlbit = (1 << 11), | |
f64cacc3 TA |
881 | }, |
882 | .sources = &clkset_group2, | |
883 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, | |
884 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, | |
885 | }, { | |
886 | .clk = { | |
887 | .name = "sclk_mfc", | |
0f75a96b | 888 | .devname = "s5p-mfc", |
f64cacc3 TA |
889 | .enable = s5pv210_clk_ip0_ctrl, |
890 | .ctrlbit = (1 << 16), | |
891 | }, | |
892 | .sources = &clkset_group1, | |
893 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, | |
894 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | |
895 | }, { | |
896 | .clk = { | |
897 | .name = "sclk_g2d", | |
f64cacc3 TA |
898 | .enable = s5pv210_clk_ip0_ctrl, |
899 | .ctrlbit = (1 << 12), | |
900 | }, | |
901 | .sources = &clkset_group1, | |
902 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | |
903 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, | |
904 | }, { | |
905 | .clk = { | |
906 | .name = "sclk_g3d", | |
f64cacc3 TA |
907 | .enable = s5pv210_clk_ip0_ctrl, |
908 | .ctrlbit = (1 << 8), | |
909 | }, | |
910 | .sources = &clkset_group1, | |
911 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, | |
912 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | |
913 | }, { | |
914 | .clk = { | |
915 | .name = "sclk_csis", | |
154d62e4 MH |
916 | .enable = s5pv210_clk_mask0_ctrl, |
917 | .ctrlbit = (1 << 6), | |
f64cacc3 TA |
918 | }, |
919 | .sources = &clkset_group2, | |
920 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, | |
921 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, | |
922 | }, { | |
923 | .clk = { | |
924 | .name = "sclk_spi", | |
b2a9dd46 | 925 | .devname = "s3c64xx-spi.0", |
154d62e4 MH |
926 | .enable = s5pv210_clk_mask0_ctrl, |
927 | .ctrlbit = (1 << 16), | |
f64cacc3 TA |
928 | }, |
929 | .sources = &clkset_group2, | |
930 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, | |
931 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, | |
932 | }, { | |
933 | .clk = { | |
934 | .name = "sclk_spi", | |
b2a9dd46 | 935 | .devname = "s3c64xx-spi.1", |
154d62e4 MH |
936 | .enable = s5pv210_clk_mask0_ctrl, |
937 | .ctrlbit = (1 << 17), | |
f64cacc3 TA |
938 | }, |
939 | .sources = &clkset_group2, | |
940 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, | |
941 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, | |
942 | }, { | |
943 | .clk = { | |
944 | .name = "sclk_pwi", | |
154d62e4 MH |
945 | .enable = s5pv210_clk_mask0_ctrl, |
946 | .ctrlbit = (1 << 29), | |
f64cacc3 TA |
947 | }, |
948 | .sources = &clkset_group2, | |
949 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, | |
950 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 }, | |
951 | }, { | |
952 | .clk = { | |
953 | .name = "sclk_pwm", | |
154d62e4 MH |
954 | .enable = s5pv210_clk_mask0_ctrl, |
955 | .ctrlbit = (1 << 19), | |
f64cacc3 TA |
956 | }, |
957 | .sources = &clkset_group2, | |
958 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, | |
959 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 }, | |
9e20614b | 960 | }, |
0c1945d3 KK |
961 | }; |
962 | ||
963 | /* Clock initialisation code */ | |
eb1ef1ed | 964 | static struct clksrc_clk *sysclks[] = { |
0c1945d3 KK |
965 | &clk_mout_apll, |
966 | &clk_mout_epll, | |
967 | &clk_mout_mpll, | |
374e0bf5 | 968 | &clk_armclk, |
af76a201 | 969 | &clk_hclk_msys, |
0fe967a1 TA |
970 | &clk_sclk_a2m, |
971 | &clk_hclk_dsys, | |
acfa245f | 972 | &clk_hclk_psys, |
6ed91a20 | 973 | &clk_pclk_msys, |
58772cd3 | 974 | &clk_pclk_dsys, |
f44cf78b | 975 | &clk_pclk_psys, |
f445dbd5 TA |
976 | &clk_vpllsrc, |
977 | &clk_sclk_vpll, | |
9e20614b TA |
978 | &clk_sclk_dac, |
979 | &clk_sclk_pixel, | |
980 | &clk_sclk_hdmi, | |
08f49d11 JL |
981 | &clk_mout_dmc0, |
982 | &clk_sclk_dmc0, | |
900fa019 SY |
983 | &clk_sclk_audio0, |
984 | &clk_sclk_audio1, | |
985 | &clk_sclk_audio2, | |
986 | &clk_sclk_spdif, | |
0c1945d3 KK |
987 | }; |
988 | ||
c9fa7a08 SY |
989 | static u32 epll_div[][6] = { |
990 | { 48000000, 0, 48, 3, 3, 0 }, | |
991 | { 96000000, 0, 48, 3, 2, 0 }, | |
992 | { 144000000, 1, 72, 3, 2, 0 }, | |
993 | { 192000000, 0, 48, 3, 1, 0 }, | |
994 | { 288000000, 1, 72, 3, 1, 0 }, | |
995 | { 32750000, 1, 65, 3, 4, 35127 }, | |
996 | { 32768000, 1, 65, 3, 4, 35127 }, | |
997 | { 45158400, 0, 45, 3, 3, 10355 }, | |
998 | { 45000000, 0, 45, 3, 3, 10355 }, | |
999 | { 45158000, 0, 45, 3, 3, 10355 }, | |
1000 | { 49125000, 0, 49, 3, 3, 9961 }, | |
1001 | { 49152000, 0, 49, 3, 3, 9961 }, | |
1002 | { 67737600, 1, 67, 3, 3, 48366 }, | |
1003 | { 67738000, 1, 67, 3, 3, 48366 }, | |
1004 | { 73800000, 1, 73, 3, 3, 47710 }, | |
1005 | { 73728000, 1, 73, 3, 3, 47710 }, | |
1006 | { 36000000, 1, 32, 3, 4, 0 }, | |
1007 | { 60000000, 1, 60, 3, 3, 0 }, | |
1008 | { 72000000, 1, 72, 3, 3, 0 }, | |
1009 | { 80000000, 1, 80, 3, 3, 0 }, | |
1010 | { 84000000, 0, 42, 3, 2, 0 }, | |
1011 | { 50000000, 0, 50, 3, 3, 0 }, | |
1012 | }; | |
1013 | ||
1014 | static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate) | |
1015 | { | |
1016 | unsigned int epll_con, epll_con_k; | |
1017 | unsigned int i; | |
1018 | ||
1019 | /* Return if nothing changed */ | |
1020 | if (clk->rate == rate) | |
1021 | return 0; | |
1022 | ||
1023 | epll_con = __raw_readl(S5P_EPLL_CON); | |
1024 | epll_con_k = __raw_readl(S5P_EPLL_CON1); | |
1025 | ||
1026 | epll_con_k &= ~PLL46XX_KDIV_MASK; | |
1027 | epll_con &= ~(1 << 27 | | |
1028 | PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | | |
1029 | PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | | |
1030 | PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); | |
1031 | ||
1032 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | |
1033 | if (epll_div[i][0] == rate) { | |
1034 | epll_con_k |= epll_div[i][5] << 0; | |
1035 | epll_con |= (epll_div[i][1] << 27 | | |
1036 | epll_div[i][2] << PLL46XX_MDIV_SHIFT | | |
1037 | epll_div[i][3] << PLL46XX_PDIV_SHIFT | | |
1038 | epll_div[i][4] << PLL46XX_SDIV_SHIFT); | |
1039 | break; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | if (i == ARRAY_SIZE(epll_div)) { | |
1044 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", | |
1045 | __func__); | |
1046 | return -EINVAL; | |
1047 | } | |
1048 | ||
1049 | __raw_writel(epll_con, S5P_EPLL_CON); | |
1050 | __raw_writel(epll_con_k, S5P_EPLL_CON1); | |
1051 | ||
9616674a SY |
1052 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", |
1053 | clk->rate, rate); | |
1054 | ||
c9fa7a08 SY |
1055 | clk->rate = rate; |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static struct clk_ops s5pv210_epll_ops = { | |
1061 | .set_rate = s5pv210_epll_set_rate, | |
1062 | .get_rate = s5p_epll_get_rate, | |
1063 | }; | |
1064 | ||
0c1945d3 KK |
1065 | void __init_or_cpufreq s5pv210_setup_clocks(void) |
1066 | { | |
1067 | struct clk *xtal_clk; | |
f445dbd5 | 1068 | unsigned long vpllsrc; |
0c1945d3 | 1069 | unsigned long armclk; |
af76a201 | 1070 | unsigned long hclk_msys; |
0fe967a1 | 1071 | unsigned long hclk_dsys; |
acfa245f | 1072 | unsigned long hclk_psys; |
6ed91a20 | 1073 | unsigned long pclk_msys; |
58772cd3 | 1074 | unsigned long pclk_dsys; |
f44cf78b | 1075 | unsigned long pclk_psys; |
0c1945d3 KK |
1076 | unsigned long apll; |
1077 | unsigned long mpll; | |
1078 | unsigned long epll; | |
f445dbd5 | 1079 | unsigned long vpll; |
0c1945d3 KK |
1080 | unsigned int ptr; |
1081 | u32 clkdiv0, clkdiv1; | |
1082 | ||
c9fa7a08 SY |
1083 | /* Set functions for clk_fout_epll */ |
1084 | clk_fout_epll.enable = s5p_epll_enable; | |
1085 | clk_fout_epll.ops = &s5pv210_epll_ops; | |
1086 | ||
0c1945d3 KK |
1087 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); |
1088 | ||
1089 | clkdiv0 = __raw_readl(S5P_CLK_DIV0); | |
1090 | clkdiv1 = __raw_readl(S5P_CLK_DIV1); | |
1091 | ||
1092 | printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", | |
1093 | __func__, clkdiv0, clkdiv1); | |
1094 | ||
1095 | xtal_clk = clk_get(NULL, "xtal"); | |
1096 | BUG_ON(IS_ERR(xtal_clk)); | |
1097 | ||
1098 | xtal = clk_get_rate(xtal_clk); | |
1099 | clk_put(xtal_clk); | |
1100 | ||
1101 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1102 | ||
1103 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); | |
1104 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); | |
42a6e20e SY |
1105 | epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON), |
1106 | __raw_readl(S5P_EPLL_CON1), pll_4600); | |
f445dbd5 TA |
1107 | vpllsrc = clk_get_rate(&clk_vpllsrc.clk); |
1108 | vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); | |
0c1945d3 | 1109 | |
88695843 | 1110 | clk_fout_apll.ops = &clk_fout_apll_ops; |
c62ec6a9 TA |
1111 | clk_fout_mpll.rate = mpll; |
1112 | clk_fout_epll.rate = epll; | |
f445dbd5 | 1113 | clk_fout_vpll.rate = vpll; |
c62ec6a9 | 1114 | |
f445dbd5 TA |
1115 | printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", |
1116 | apll, mpll, epll, vpll); | |
0c1945d3 | 1117 | |
374e0bf5 | 1118 | armclk = clk_get_rate(&clk_armclk.clk); |
af76a201 | 1119 | hclk_msys = clk_get_rate(&clk_hclk_msys.clk); |
0fe967a1 | 1120 | hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); |
acfa245f | 1121 | hclk_psys = clk_get_rate(&clk_hclk_psys.clk); |
6ed91a20 | 1122 | pclk_msys = clk_get_rate(&clk_pclk_msys.clk); |
58772cd3 | 1123 | pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk); |
f44cf78b | 1124 | pclk_psys = clk_get_rate(&clk_pclk_psys.clk); |
0c1945d3 | 1125 | |
acfa245f TA |
1126 | printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n" |
1127 | "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", | |
1128 | armclk, hclk_msys, hclk_dsys, hclk_psys, | |
f44cf78b | 1129 | pclk_msys, pclk_dsys, pclk_psys); |
0c1945d3 | 1130 | |
0c1945d3 | 1131 | clk_f.rate = armclk; |
acfa245f | 1132 | clk_h.rate = hclk_psys; |
f44cf78b | 1133 | clk_p.rate = pclk_psys; |
0c1945d3 | 1134 | |
0c1945d3 KK |
1135 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) |
1136 | s3c_set_clksrc(&clksrcs[ptr], true); | |
1137 | } | |
1138 | ||
1139 | static struct clk *clks[] __initdata = { | |
f445dbd5 | 1140 | &clk_sclk_hdmi27m, |
2cf4c2e6 TA |
1141 | &clk_sclk_hdmiphy, |
1142 | &clk_sclk_usbphy0, | |
1143 | &clk_sclk_usbphy1, | |
4583487c TA |
1144 | &clk_pcmcdclk0, |
1145 | &clk_pcmcdclk1, | |
1146 | &clk_pcmcdclk2, | |
0c1945d3 KK |
1147 | }; |
1148 | ||
1149 | void __init s5pv210_register_clocks(void) | |
1150 | { | |
0c1945d3 KK |
1151 | int ptr; |
1152 | ||
3c0fa647 | 1153 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
0c1945d3 | 1154 | |
eb1ef1ed TA |
1155 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) |
1156 | s3c_register_clksrc(sysclks[ptr], 1); | |
1157 | ||
0c1945d3 KK |
1158 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
1159 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | |
1160 | ||
3c0fa647 KK |
1161 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
1162 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
0c1945d3 KK |
1163 | |
1164 | s3c_pwmclk_init(); | |
1165 | } |