Commit | Line | Data |
---|---|---|
7f471ee8 JS |
1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics Co.Ltd | |
3 | * Author: Joonyoung Shim <jy0922.shim@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundationr | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <mach/map.h> | |
16 | #include <mach/regs-sys.h> | |
17 | #include <plat/cpu.h> | |
18 | #include <plat/regs-usb-hsotg-phy.h> | |
19 | #include <plat/usb-phy.h> | |
20 | ||
21 | static int s5pv210_usb_otgphy_init(struct platform_device *pdev) | |
22 | { | |
23 | struct clk *xusbxti; | |
24 | u32 phyclk; | |
25 | ||
26 | writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN, | |
27 | S5PV210_USB_PHY_CON); | |
28 | ||
29 | /* set clock frequency for PLL */ | |
30 | phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; | |
31 | ||
32 | xusbxti = clk_get(&pdev->dev, "xusbxti"); | |
33 | if (xusbxti && !IS_ERR(xusbxti)) { | |
34 | switch (clk_get_rate(xusbxti)) { | |
35 | case 12 * MHZ: | |
36 | phyclk |= S3C_PHYCLK_CLKSEL_12M; | |
37 | break; | |
38 | case 24 * MHZ: | |
39 | phyclk |= S3C_PHYCLK_CLKSEL_24M; | |
40 | break; | |
41 | default: | |
42 | case 48 * MHZ: | |
43 | /* default reference clock */ | |
44 | break; | |
45 | } | |
46 | clk_put(xusbxti); | |
47 | } | |
48 | ||
49 | /* TODO: select external clock/oscillator */ | |
50 | writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); | |
51 | ||
52 | /* set to normal OTG PHY */ | |
53 | writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); | |
54 | mdelay(1); | |
55 | ||
56 | /* reset OTG PHY and Link */ | |
57 | writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, | |
58 | S3C_RSTCON); | |
59 | udelay(20); /* at-least 10uS */ | |
60 | writel(0, S3C_RSTCON); | |
61 | ||
62 | return 0; | |
63 | } | |
64 | ||
65 | static int s5pv210_usb_otgphy_exit(struct platform_device *pdev) | |
66 | { | |
67 | writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | | |
68 | S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR); | |
69 | ||
70 | writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN, | |
71 | S5PV210_USB_PHY_CON); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
76 | int s5p_usb_phy_init(struct platform_device *pdev, int type) | |
77 | { | |
78 | if (type == S5P_USB_PHY_DEVICE) | |
79 | return s5pv210_usb_otgphy_init(pdev); | |
80 | ||
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | int s5p_usb_phy_exit(struct platform_device *pdev, int type) | |
85 | { | |
86 | if (type == S5P_USB_PHY_DEVICE) | |
87 | return s5pv210_usb_otgphy_exit(pdev); | |
88 | ||
89 | return -EINVAL; | |
90 | } |