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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-sa1100/irq.c | |
3 | * | |
4 | * Copyright (C) 1999-2001 Nicolas Pitre | |
5 | * | |
6 | * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
119c641c TG |
14 | #include <linux/interrupt.h> |
15 | #include <linux/irq.h> | |
1da177e4 | 16 | #include <linux/ioport.h> |
90533980 | 17 | #include <linux/syscore_ops.h> |
1da177e4 | 18 | |
a09e64fb | 19 | #include <mach/hardware.h> |
1da177e4 LT |
20 | #include <asm/mach/irq.h> |
21 | ||
22 | #include "generic.h" | |
23 | ||
24 | ||
25 | /* | |
26 | * SA1100 GPIO edge detection for IRQs: | |
27 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | |
28 | * Use this instead of directly setting GRER/GFER. | |
29 | */ | |
30 | static int GPIO_IRQ_rising_edge; | |
31 | static int GPIO_IRQ_falling_edge; | |
32 | static int GPIO_IRQ_mask = (1 << 11) - 1; | |
33 | ||
34 | /* | |
35 | * To get the GPIO number from an IRQ number | |
36 | */ | |
37 | #define GPIO_11_27_IRQ(i) ((i) - 21) | |
38 | #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq)) | |
39 | ||
c4e8964e | 40 | static int sa1100_gpio_type(struct irq_data *d, unsigned int type) |
1da177e4 LT |
41 | { |
42 | unsigned int mask; | |
43 | ||
c4e8964e LB |
44 | if (d->irq <= 10) |
45 | mask = 1 << d->irq; | |
1da177e4 | 46 | else |
c4e8964e | 47 | mask = GPIO11_27_MASK(d->irq); |
1da177e4 | 48 | |
6cab4860 | 49 | if (type == IRQ_TYPE_PROBE) { |
1da177e4 LT |
50 | if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) |
51 | return 0; | |
6cab4860 | 52 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
1da177e4 LT |
53 | } |
54 | ||
6cab4860 | 55 | if (type & IRQ_TYPE_EDGE_RISING) { |
1da177e4 LT |
56 | GPIO_IRQ_rising_edge |= mask; |
57 | } else | |
58 | GPIO_IRQ_rising_edge &= ~mask; | |
6cab4860 | 59 | if (type & IRQ_TYPE_EDGE_FALLING) { |
1da177e4 LT |
60 | GPIO_IRQ_falling_edge |= mask; |
61 | } else | |
62 | GPIO_IRQ_falling_edge &= ~mask; | |
63 | ||
64 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
65 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | /* | |
71 | * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10. | |
72 | */ | |
c4e8964e | 73 | static void sa1100_low_gpio_ack(struct irq_data *d) |
1da177e4 | 74 | { |
c4e8964e | 75 | GEDR = (1 << d->irq); |
1da177e4 LT |
76 | } |
77 | ||
c4e8964e | 78 | static void sa1100_low_gpio_mask(struct irq_data *d) |
1da177e4 | 79 | { |
c4e8964e | 80 | ICMR &= ~(1 << d->irq); |
1da177e4 LT |
81 | } |
82 | ||
c4e8964e | 83 | static void sa1100_low_gpio_unmask(struct irq_data *d) |
1da177e4 | 84 | { |
c4e8964e | 85 | ICMR |= 1 << d->irq; |
1da177e4 LT |
86 | } |
87 | ||
c4e8964e | 88 | static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on) |
1da177e4 LT |
89 | { |
90 | if (on) | |
c4e8964e | 91 | PWER |= 1 << d->irq; |
1da177e4 | 92 | else |
c4e8964e | 93 | PWER &= ~(1 << d->irq); |
1da177e4 LT |
94 | return 0; |
95 | } | |
96 | ||
38c677cb DB |
97 | static struct irq_chip sa1100_low_gpio_chip = { |
98 | .name = "GPIO-l", | |
c4e8964e LB |
99 | .irq_ack = sa1100_low_gpio_ack, |
100 | .irq_mask = sa1100_low_gpio_mask, | |
101 | .irq_unmask = sa1100_low_gpio_unmask, | |
102 | .irq_set_type = sa1100_gpio_type, | |
103 | .irq_set_wake = sa1100_low_gpio_wake, | |
1da177e4 LT |
104 | }; |
105 | ||
106 | /* | |
107 | * IRQ11 (GPIO11 through 27) handler. We enter here with the | |
108 | * irq_controller_lock held, and IRQs disabled. Decode the IRQ | |
109 | * and call the handler. | |
110 | */ | |
111 | static void | |
10dd5ce2 | 112 | sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
113 | { |
114 | unsigned int mask; | |
115 | ||
116 | mask = GEDR & 0xfffff800; | |
117 | do { | |
118 | /* | |
119 | * clear down all currently active IRQ sources. | |
120 | * We will be processing them all. | |
121 | */ | |
122 | GEDR = mask; | |
123 | ||
124 | irq = IRQ_GPIO11; | |
1da177e4 LT |
125 | mask >>= 11; |
126 | do { | |
127 | if (mask & 1) | |
d8aa0251 | 128 | generic_handle_irq(irq); |
1da177e4 LT |
129 | mask >>= 1; |
130 | irq++; | |
1da177e4 LT |
131 | } while (mask); |
132 | ||
133 | mask = GEDR & 0xfffff800; | |
134 | } while (mask); | |
135 | } | |
136 | ||
137 | /* | |
138 | * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially. | |
139 | * In addition, the IRQs are all collected up into one bit in the | |
140 | * interrupt controller registers. | |
141 | */ | |
c4e8964e | 142 | static void sa1100_high_gpio_ack(struct irq_data *d) |
1da177e4 | 143 | { |
c4e8964e | 144 | unsigned int mask = GPIO11_27_MASK(d->irq); |
1da177e4 LT |
145 | |
146 | GEDR = mask; | |
147 | } | |
148 | ||
c4e8964e | 149 | static void sa1100_high_gpio_mask(struct irq_data *d) |
1da177e4 | 150 | { |
c4e8964e | 151 | unsigned int mask = GPIO11_27_MASK(d->irq); |
1da177e4 LT |
152 | |
153 | GPIO_IRQ_mask &= ~mask; | |
154 | ||
155 | GRER &= ~mask; | |
156 | GFER &= ~mask; | |
157 | } | |
158 | ||
c4e8964e | 159 | static void sa1100_high_gpio_unmask(struct irq_data *d) |
1da177e4 | 160 | { |
c4e8964e | 161 | unsigned int mask = GPIO11_27_MASK(d->irq); |
1da177e4 LT |
162 | |
163 | GPIO_IRQ_mask |= mask; | |
164 | ||
165 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
166 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
167 | } | |
168 | ||
c4e8964e | 169 | static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on) |
1da177e4 LT |
170 | { |
171 | if (on) | |
c4e8964e | 172 | PWER |= GPIO11_27_MASK(d->irq); |
1da177e4 | 173 | else |
c4e8964e | 174 | PWER &= ~GPIO11_27_MASK(d->irq); |
1da177e4 LT |
175 | return 0; |
176 | } | |
177 | ||
38c677cb DB |
178 | static struct irq_chip sa1100_high_gpio_chip = { |
179 | .name = "GPIO-h", | |
c4e8964e LB |
180 | .irq_ack = sa1100_high_gpio_ack, |
181 | .irq_mask = sa1100_high_gpio_mask, | |
182 | .irq_unmask = sa1100_high_gpio_unmask, | |
183 | .irq_set_type = sa1100_gpio_type, | |
184 | .irq_set_wake = sa1100_high_gpio_wake, | |
1da177e4 LT |
185 | }; |
186 | ||
187 | /* | |
188 | * We don't need to ACK IRQs on the SA1100 unless they're GPIOs | |
189 | * this is for internal IRQs i.e. from 11 to 31. | |
190 | */ | |
c4e8964e | 191 | static void sa1100_mask_irq(struct irq_data *d) |
1da177e4 | 192 | { |
c4e8964e | 193 | ICMR &= ~(1 << d->irq); |
1da177e4 LT |
194 | } |
195 | ||
c4e8964e | 196 | static void sa1100_unmask_irq(struct irq_data *d) |
1da177e4 | 197 | { |
c4e8964e | 198 | ICMR |= (1 << d->irq); |
1da177e4 LT |
199 | } |
200 | ||
19ca5d27 RK |
201 | /* |
202 | * Apart form GPIOs, only the RTC alarm can be a wakeup event. | |
203 | */ | |
c4e8964e | 204 | static int sa1100_set_wake(struct irq_data *d, unsigned int on) |
19ca5d27 | 205 | { |
c4e8964e | 206 | if (d->irq == IRQ_RTCAlrm) { |
19ca5d27 RK |
207 | if (on) |
208 | PWER |= PWER_RTC; | |
209 | else | |
210 | PWER &= ~PWER_RTC; | |
211 | return 0; | |
212 | } | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
38c677cb DB |
216 | static struct irq_chip sa1100_normal_chip = { |
217 | .name = "SC", | |
c4e8964e LB |
218 | .irq_ack = sa1100_mask_irq, |
219 | .irq_mask = sa1100_mask_irq, | |
220 | .irq_unmask = sa1100_unmask_irq, | |
221 | .irq_set_wake = sa1100_set_wake, | |
1da177e4 LT |
222 | }; |
223 | ||
a181099e RK |
224 | static struct resource irq_resource = |
225 | DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); | |
1da177e4 LT |
226 | |
227 | static struct sa1100irq_state { | |
228 | unsigned int saved; | |
229 | unsigned int icmr; | |
230 | unsigned int iclr; | |
231 | unsigned int iccr; | |
232 | } sa1100irq_state; | |
233 | ||
90533980 | 234 | static int sa1100irq_suspend(void) |
1da177e4 LT |
235 | { |
236 | struct sa1100irq_state *st = &sa1100irq_state; | |
237 | ||
238 | st->saved = 1; | |
239 | st->icmr = ICMR; | |
240 | st->iclr = ICLR; | |
241 | st->iccr = ICCR; | |
242 | ||
243 | /* | |
244 | * Disable all GPIO-based interrupts. | |
245 | */ | |
246 | ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7| | |
247 | IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2| | |
248 | IC_GPIO1|IC_GPIO0); | |
249 | ||
250 | /* | |
251 | * Set the appropriate edges for wakeup. | |
252 | */ | |
253 | GRER = PWER & GPIO_IRQ_rising_edge; | |
254 | GFER = PWER & GPIO_IRQ_falling_edge; | |
255 | ||
256 | /* | |
257 | * Clear any pending GPIO interrupts. | |
258 | */ | |
259 | GEDR = GEDR; | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
90533980 | 264 | static void sa1100irq_resume(void) |
1da177e4 LT |
265 | { |
266 | struct sa1100irq_state *st = &sa1100irq_state; | |
267 | ||
268 | if (st->saved) { | |
269 | ICCR = st->iccr; | |
270 | ICLR = st->iclr; | |
271 | ||
272 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
273 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
274 | ||
275 | ICMR = st->icmr; | |
276 | } | |
1da177e4 LT |
277 | } |
278 | ||
90533980 | 279 | static struct syscore_ops sa1100irq_syscore_ops = { |
1da177e4 LT |
280 | .suspend = sa1100irq_suspend, |
281 | .resume = sa1100irq_resume, | |
282 | }; | |
283 | ||
1da177e4 LT |
284 | static int __init sa1100irq_init_devicefs(void) |
285 | { | |
90533980 RW |
286 | register_syscore_ops(&sa1100irq_syscore_ops); |
287 | return 0; | |
1da177e4 LT |
288 | } |
289 | ||
290 | device_initcall(sa1100irq_init_devicefs); | |
291 | ||
292 | void __init sa1100_init_irq(void) | |
293 | { | |
294 | unsigned int irq; | |
295 | ||
296 | request_resource(&iomem_resource, &irq_resource); | |
297 | ||
298 | /* disable all IRQs */ | |
299 | ICMR = 0; | |
300 | ||
301 | /* all IRQs are IRQ, not FIQ */ | |
302 | ICLR = 0; | |
303 | ||
304 | /* clear all GPIO edge detects */ | |
305 | GFER = 0; | |
306 | GRER = 0; | |
307 | GEDR = -1; | |
308 | ||
309 | /* | |
310 | * Whatever the doc says, this has to be set for the wait-on-irq | |
311 | * instruction to work... on a SA1100 rev 9 at least. | |
312 | */ | |
313 | ICCR = 1; | |
314 | ||
315 | for (irq = 0; irq <= 10; irq++) { | |
f38c02f3 TG |
316 | irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip, |
317 | handle_edge_irq); | |
1da177e4 LT |
318 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
319 | } | |
320 | ||
321 | for (irq = 12; irq <= 31; irq++) { | |
f38c02f3 TG |
322 | irq_set_chip_and_handler(irq, &sa1100_normal_chip, |
323 | handle_level_irq); | |
1da177e4 LT |
324 | set_irq_flags(irq, IRQF_VALID); |
325 | } | |
326 | ||
327 | for (irq = 32; irq <= 48; irq++) { | |
f38c02f3 TG |
328 | irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip, |
329 | handle_edge_irq); | |
1da177e4 LT |
330 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
331 | } | |
332 | ||
333 | /* | |
334 | * Install handler for GPIO 11-27 edge detect interrupts | |
335 | */ | |
6845664a TG |
336 | irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip); |
337 | irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); | |
45528e38 DB |
338 | |
339 | sa1100_init_gpio(); | |
1da177e4 | 340 | } |