Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-sa1100/irq.c | |
3 | * | |
4 | * Copyright (C) 1999-2001 Nicolas Pitre | |
5 | * | |
6 | * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
119c641c | 14 | #include <linux/interrupt.h> |
3169663a | 15 | #include <linux/io.h> |
119c641c | 16 | #include <linux/irq.h> |
1eca42b4 | 17 | #include <linux/irqdomain.h> |
1da177e4 | 18 | #include <linux/ioport.h> |
90533980 | 19 | #include <linux/syscore_ops.h> |
1da177e4 | 20 | |
a09e64fb | 21 | #include <mach/hardware.h> |
f314f33b | 22 | #include <mach/irqs.h> |
1da177e4 | 23 | #include <asm/mach/irq.h> |
affcab32 | 24 | #include <asm/exception.h> |
1da177e4 LT |
25 | |
26 | #include "generic.h" | |
27 | ||
28 | ||
ab71f99f DES |
29 | /* |
30 | * We don't need to ACK IRQs on the SA1100 unless they're GPIOs | |
31 | * this is for internal IRQs i.e. from IRQ LCD to RTCAlrm. | |
32 | */ | |
33 | static void sa1100_mask_irq(struct irq_data *d) | |
34 | { | |
35 | ICMR &= ~BIT(d->hwirq); | |
36 | } | |
37 | ||
38 | static void sa1100_unmask_irq(struct irq_data *d) | |
39 | { | |
40 | ICMR |= BIT(d->hwirq); | |
41 | } | |
42 | ||
43 | /* | |
44 | * Apart form GPIOs, only the RTC alarm can be a wakeup event. | |
45 | */ | |
46 | static int sa1100_set_wake(struct irq_data *d, unsigned int on) | |
47 | { | |
48 | if (BIT(d->hwirq) == IC_RTCAlrm) { | |
49 | if (on) | |
50 | PWER |= PWER_RTC; | |
51 | else | |
52 | PWER &= ~PWER_RTC; | |
53 | return 0; | |
54 | } | |
55 | return -EINVAL; | |
56 | } | |
57 | ||
58 | static struct irq_chip sa1100_normal_chip = { | |
59 | .name = "SC", | |
60 | .irq_ack = sa1100_mask_irq, | |
61 | .irq_mask = sa1100_mask_irq, | |
62 | .irq_unmask = sa1100_unmask_irq, | |
63 | .irq_set_wake = sa1100_set_wake, | |
64 | }; | |
65 | ||
66 | static int sa1100_normal_irqdomain_map(struct irq_domain *d, | |
67 | unsigned int irq, irq_hw_number_t hwirq) | |
68 | { | |
69 | irq_set_chip_and_handler(irq, &sa1100_normal_chip, | |
70 | handle_level_irq); | |
71 | set_irq_flags(irq, IRQF_VALID); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
76 | static struct irq_domain_ops sa1100_normal_irqdomain_ops = { | |
77 | .map = sa1100_normal_irqdomain_map, | |
78 | .xlate = irq_domain_xlate_onetwocell, | |
79 | }; | |
80 | ||
81 | static struct irq_domain *sa1100_normal_irqdomain; | |
82 | ||
1da177e4 LT |
83 | /* |
84 | * SA1100 GPIO edge detection for IRQs: | |
85 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | |
86 | * Use this instead of directly setting GRER/GFER. | |
87 | */ | |
88 | static int GPIO_IRQ_rising_edge; | |
89 | static int GPIO_IRQ_falling_edge; | |
83508093 | 90 | static int GPIO_IRQ_mask; |
1da177e4 | 91 | |
c4e8964e | 92 | static int sa1100_gpio_type(struct irq_data *d, unsigned int type) |
1da177e4 LT |
93 | { |
94 | unsigned int mask; | |
95 | ||
1eeec6af | 96 | mask = BIT(d->hwirq); |
1da177e4 | 97 | |
6cab4860 | 98 | if (type == IRQ_TYPE_PROBE) { |
1da177e4 LT |
99 | if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) |
100 | return 0; | |
6cab4860 | 101 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
1da177e4 LT |
102 | } |
103 | ||
6cab4860 | 104 | if (type & IRQ_TYPE_EDGE_RISING) { |
1da177e4 LT |
105 | GPIO_IRQ_rising_edge |= mask; |
106 | } else | |
107 | GPIO_IRQ_rising_edge &= ~mask; | |
6cab4860 | 108 | if (type & IRQ_TYPE_EDGE_FALLING) { |
1da177e4 LT |
109 | GPIO_IRQ_falling_edge |= mask; |
110 | } else | |
111 | GPIO_IRQ_falling_edge &= ~mask; | |
112 | ||
113 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
114 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | /* | |
ab71f99f | 120 | * GPIO IRQs must be acknowledged. |
1da177e4 | 121 | */ |
ab71f99f | 122 | static void sa1100_gpio_ack(struct irq_data *d) |
1da177e4 | 123 | { |
1eeec6af | 124 | GEDR = BIT(d->hwirq); |
1da177e4 LT |
125 | } |
126 | ||
83508093 DES |
127 | static void sa1100_gpio_mask(struct irq_data *d) |
128 | { | |
129 | unsigned int mask = BIT(d->hwirq); | |
130 | ||
131 | GPIO_IRQ_mask &= ~mask; | |
132 | ||
133 | GRER &= ~mask; | |
134 | GFER &= ~mask; | |
135 | } | |
136 | ||
137 | static void sa1100_gpio_unmask(struct irq_data *d) | |
138 | { | |
139 | unsigned int mask = BIT(d->hwirq); | |
140 | ||
141 | GPIO_IRQ_mask |= mask; | |
142 | ||
143 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
144 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
145 | } | |
146 | ||
ab71f99f | 147 | static int sa1100_gpio_wake(struct irq_data *d, unsigned int on) |
1da177e4 LT |
148 | { |
149 | if (on) | |
1eeec6af | 150 | PWER |= BIT(d->hwirq); |
1da177e4 | 151 | else |
1eeec6af | 152 | PWER &= ~BIT(d->hwirq); |
1da177e4 LT |
153 | return 0; |
154 | } | |
155 | ||
ab71f99f | 156 | /* |
590f2661 | 157 | * This is for GPIO IRQs |
ab71f99f | 158 | */ |
590f2661 DES |
159 | static struct irq_chip sa1100_gpio_chip = { |
160 | .name = "GPIO", | |
ab71f99f | 161 | .irq_ack = sa1100_gpio_ack, |
83508093 DES |
162 | .irq_mask = sa1100_gpio_mask, |
163 | .irq_unmask = sa1100_gpio_unmask, | |
c4e8964e | 164 | .irq_set_type = sa1100_gpio_type, |
ab71f99f | 165 | .irq_set_wake = sa1100_gpio_wake, |
1da177e4 LT |
166 | }; |
167 | ||
590f2661 | 168 | static int sa1100_gpio_irqdomain_map(struct irq_domain *d, |
1eca42b4 DES |
169 | unsigned int irq, irq_hw_number_t hwirq) |
170 | { | |
590f2661 | 171 | irq_set_chip_and_handler(irq, &sa1100_gpio_chip, |
1eca42b4 DES |
172 | handle_edge_irq); |
173 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
590f2661 DES |
178 | static struct irq_domain_ops sa1100_gpio_irqdomain_ops = { |
179 | .map = sa1100_gpio_irqdomain_map, | |
1eca42b4 DES |
180 | .xlate = irq_domain_xlate_onetwocell, |
181 | }; | |
182 | ||
590f2661 | 183 | static struct irq_domain *sa1100_gpio_irqdomain; |
1eca42b4 | 184 | |
1da177e4 | 185 | /* |
83508093 | 186 | * IRQ 0-11 (GPIO) handler. We enter here with the |
1da177e4 LT |
187 | * irq_controller_lock held, and IRQs disabled. Decode the IRQ |
188 | * and call the handler. | |
189 | */ | |
190 | static void | |
83508093 | 191 | sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
192 | { |
193 | unsigned int mask; | |
194 | ||
83508093 | 195 | mask = GEDR; |
1da177e4 LT |
196 | do { |
197 | /* | |
198 | * clear down all currently active IRQ sources. | |
199 | * We will be processing them all. | |
200 | */ | |
201 | GEDR = mask; | |
202 | ||
83508093 | 203 | irq = IRQ_GPIO0; |
1da177e4 LT |
204 | do { |
205 | if (mask & 1) | |
d8aa0251 | 206 | generic_handle_irq(irq); |
1da177e4 LT |
207 | mask >>= 1; |
208 | irq++; | |
1da177e4 LT |
209 | } while (mask); |
210 | ||
83508093 | 211 | mask = GEDR; |
1da177e4 LT |
212 | } while (mask); |
213 | } | |
214 | ||
a181099e RK |
215 | static struct resource irq_resource = |
216 | DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); | |
1da177e4 LT |
217 | |
218 | static struct sa1100irq_state { | |
219 | unsigned int saved; | |
220 | unsigned int icmr; | |
221 | unsigned int iclr; | |
222 | unsigned int iccr; | |
223 | } sa1100irq_state; | |
224 | ||
90533980 | 225 | static int sa1100irq_suspend(void) |
1da177e4 LT |
226 | { |
227 | struct sa1100irq_state *st = &sa1100irq_state; | |
228 | ||
229 | st->saved = 1; | |
230 | st->icmr = ICMR; | |
231 | st->iclr = ICLR; | |
232 | st->iccr = ICCR; | |
233 | ||
234 | /* | |
235 | * Disable all GPIO-based interrupts. | |
236 | */ | |
237 | ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7| | |
238 | IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2| | |
239 | IC_GPIO1|IC_GPIO0); | |
240 | ||
241 | /* | |
242 | * Set the appropriate edges for wakeup. | |
243 | */ | |
244 | GRER = PWER & GPIO_IRQ_rising_edge; | |
245 | GFER = PWER & GPIO_IRQ_falling_edge; | |
246 | ||
247 | /* | |
248 | * Clear any pending GPIO interrupts. | |
249 | */ | |
250 | GEDR = GEDR; | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
90533980 | 255 | static void sa1100irq_resume(void) |
1da177e4 LT |
256 | { |
257 | struct sa1100irq_state *st = &sa1100irq_state; | |
258 | ||
259 | if (st->saved) { | |
260 | ICCR = st->iccr; | |
261 | ICLR = st->iclr; | |
262 | ||
263 | GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; | |
264 | GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; | |
265 | ||
266 | ICMR = st->icmr; | |
267 | } | |
1da177e4 LT |
268 | } |
269 | ||
90533980 | 270 | static struct syscore_ops sa1100irq_syscore_ops = { |
1da177e4 LT |
271 | .suspend = sa1100irq_suspend, |
272 | .resume = sa1100irq_resume, | |
273 | }; | |
274 | ||
1da177e4 LT |
275 | static int __init sa1100irq_init_devicefs(void) |
276 | { | |
90533980 RW |
277 | register_syscore_ops(&sa1100irq_syscore_ops); |
278 | return 0; | |
1da177e4 LT |
279 | } |
280 | ||
281 | device_initcall(sa1100irq_init_devicefs); | |
282 | ||
affcab32 DES |
283 | static asmlinkage void __exception_irq_entry |
284 | sa1100_handle_irq(struct pt_regs *regs) | |
285 | { | |
286 | uint32_t icip, icmr, mask; | |
287 | ||
288 | do { | |
289 | icip = (ICIP); | |
290 | icmr = (ICMR); | |
291 | mask = icip & icmr; | |
292 | ||
293 | if (mask == 0) | |
294 | break; | |
295 | ||
83508093 | 296 | handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0_SC, regs); |
affcab32 DES |
297 | } while (1); |
298 | } | |
299 | ||
1da177e4 LT |
300 | void __init sa1100_init_irq(void) |
301 | { | |
1da177e4 LT |
302 | request_resource(&iomem_resource, &irq_resource); |
303 | ||
304 | /* disable all IRQs */ | |
305 | ICMR = 0; | |
306 | ||
307 | /* all IRQs are IRQ, not FIQ */ | |
308 | ICLR = 0; | |
309 | ||
310 | /* clear all GPIO edge detects */ | |
311 | GFER = 0; | |
312 | GRER = 0; | |
313 | GEDR = -1; | |
314 | ||
315 | /* | |
316 | * Whatever the doc says, this has to be set for the wait-on-irq | |
317 | * instruction to work... on a SA1100 rev 9 at least. | |
318 | */ | |
319 | ICCR = 1; | |
320 | ||
83508093 DES |
321 | sa1100_normal_irqdomain = irq_domain_add_legacy(NULL, |
322 | 32, IRQ_GPIO0_SC, 0, | |
323 | &sa1100_normal_irqdomain_ops, NULL); | |
324 | ||
590f2661 DES |
325 | sa1100_gpio_irqdomain = irq_domain_add_legacy(NULL, |
326 | 28, IRQ_GPIO0, 0, | |
327 | &sa1100_gpio_irqdomain_ops, NULL); | |
1da177e4 | 328 | |
83508093 DES |
329 | /* |
330 | * Install handlers for GPIO 0-10 edge detect interrupts | |
331 | */ | |
332 | irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler); | |
333 | irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler); | |
334 | irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler); | |
335 | irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler); | |
336 | irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler); | |
337 | irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler); | |
338 | irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler); | |
339 | irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler); | |
340 | irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler); | |
341 | irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler); | |
342 | irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler); | |
1da177e4 LT |
343 | /* |
344 | * Install handler for GPIO 11-27 edge detect interrupts | |
345 | */ | |
83508093 | 346 | irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler); |
45528e38 | 347 | |
affcab32 DES |
348 | set_handle_irq(sa1100_handle_irq); |
349 | ||
45528e38 | 350 | sa1100_init_gpio(); |
1da177e4 | 351 | } |