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9f15d2ca MRJ |
1 | /* |
2 | * linux/arch/arm/mach-sa1100/nanoengine.c | |
3 | * | |
4 | * Bright Star Engineering's nanoEngine board init code. | |
5 | * | |
fa87672a | 6 | * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> |
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7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/kernel.h> | |
6920b5a7 | 16 | #include <linux/platform_data/sa11x0-serial.h> |
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17 | #include <linux/mtd/mtd.h> |
18 | #include <linux/mtd/partitions.h> | |
19 | #include <linux/root_dev.h> | |
20 | ||
21 | #include <asm/mach-types.h> | |
22 | #include <asm/setup.h> | |
2b974795 | 23 | #include <asm/page.h> |
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24 | |
25 | #include <asm/mach/arch.h> | |
26 | #include <asm/mach/flash.h> | |
27 | #include <asm/mach/map.h> | |
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28 | |
29 | #include <mach/hardware.h> | |
b080ac8a | 30 | #include <mach/nanoengine.h> |
f314f33b | 31 | #include <mach/irqs.h> |
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32 | |
33 | #include "generic.h" | |
34 | ||
35 | /* Flash bank 0 */ | |
36 | static struct mtd_partition nanoengine_partitions[] = { | |
37 | { | |
38 | .name = "nanoEngine boot firmware and parameter table", | |
39 | .size = 0x00010000, /* 32K */ | |
40 | .offset = 0, | |
41 | .mask_flags = MTD_WRITEABLE, | |
42 | }, { | |
43 | .name = "kernel/initrd reserved", | |
44 | .size = 0x002f0000, | |
45 | .offset = 0x00010000, | |
46 | .mask_flags = MTD_WRITEABLE, | |
47 | }, { | |
48 | .name = "experimental filesystem allocation", | |
49 | .size = 0x00100000, | |
50 | .offset = 0x00300000, | |
51 | .mask_flags = MTD_WRITEABLE, | |
52 | } | |
53 | }; | |
54 | ||
55 | static struct flash_platform_data nanoengine_flash_data = { | |
56 | .map_name = "jedec_probe", | |
57 | .parts = nanoengine_partitions, | |
58 | .nr_parts = ARRAY_SIZE(nanoengine_partitions), | |
59 | }; | |
60 | ||
61 | static struct resource nanoengine_flash_resources[] = { | |
a181099e RK |
62 | DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), |
63 | DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), | |
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64 | }; |
65 | ||
66 | static struct map_desc nanoengine_io_desc[] __initdata = { | |
67 | { | |
68 | /* System Registers */ | |
69 | .virtual = 0xf0000000, | |
70 | .pfn = __phys_to_pfn(0x10000000), | |
71 | .length = 0x00100000, | |
72 | .type = MT_DEVICE | |
b080ac8a MRJ |
73 | }, { |
74 | /* Internal PCI Memory Read/Write */ | |
75 | .virtual = NANO_PCI_MEM_RW_VIRT, | |
76 | .pfn = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS), | |
77 | .length = NANO_PCI_MEM_RW_SIZE, | |
78 | .type = MT_DEVICE | |
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79 | }, { |
80 | /* Internal PCI Config Space */ | |
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81 | .virtual = NANO_PCI_CONFIG_SPACE_VIRT, |
82 | .pfn = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS), | |
83 | .length = NANO_PCI_CONFIG_SPACE_SIZE, | |
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84 | .type = MT_DEVICE |
85 | } | |
86 | }; | |
87 | ||
88 | static void __init nanoengine_map_io(void) | |
89 | { | |
90 | sa1100_map_io(); | |
91 | iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc)); | |
92 | ||
93 | sa1100_register_uart(0, 1); | |
94 | sa1100_register_uart(1, 2); | |
95 | sa1100_register_uart(2, 3); | |
96 | Ser1SDCR0 |= SDCR0_UART; | |
97 | /* disable IRDA -- UART2 is used as a normal serial port */ | |
98 | Ser2UTCR4 = 0; | |
99 | Ser2HSCR0 = 0; | |
100 | } | |
101 | ||
102 | static void __init nanoengine_init(void) | |
103 | { | |
104 | sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources, | |
105 | ARRAY_SIZE(nanoengine_flash_resources)); | |
106 | } | |
107 | ||
108 | MACHINE_START(NANOENGINE, "BSE nanoEngine") | |
17f4425d | 109 | .atag_offset = 0x100, |
9f15d2ca | 110 | .map_io = nanoengine_map_io, |
f314f33b | 111 | .nr_irqs = SA1100_NR_IRQS, |
9f15d2ca | 112 | .init_irq = sa1100_init_irq, |
6bb27d73 | 113 | .init_time = sa1100_timer_init, |
9f15d2ca | 114 | .init_machine = nanoengine_init, |
7fea1ba5 | 115 | .init_late = sa11x0_init_late, |
d9ca5839 | 116 | .restart = sa11x0_restart, |
9f15d2ca | 117 | MACHINE_END |