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1da177e4 LT |
1 | /* |
2 | * SA1100 Power Management Routines | |
3 | * | |
4 | * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License. | |
8 | * | |
9 | * History: | |
10 | * | |
11 | * 2001-02-06: Cliff Brake Initial code | |
12 | * | |
13 | * 2001-02-25: Sukjae Cho <sjcho@east.isi.edu> & | |
14 | * Chester Kuo <chester@linux.org.tw> | |
15 | * Save more value for the resume function! Support | |
16 | * Bitsy/Assabet/Freebird board | |
17 | * | |
18 | * 2001-08-29: Nicolas Pitre <nico@cam.org> | |
19 | * Cleaned up, pushed platform dependent stuff | |
20 | * in the platform specific files. | |
21 | * | |
22 | * 2002-05-27: Nicolas Pitre Killed sleep.h and the kmalloced save array. | |
23 | * Storage is local on the stack now. | |
24 | */ | |
25 | #include <linux/init.h> | |
26 | #include <linux/suspend.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/time.h> | |
29 | ||
30 | #include <asm/hardware.h> | |
31 | #include <asm/memory.h> | |
32 | #include <asm/system.h> | |
33 | #include <asm/mach/time.h> | |
34 | ||
35 | extern void sa1100_cpu_suspend(void); | |
36 | extern void sa1100_cpu_resume(void); | |
37 | ||
38 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x | |
39 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | |
40 | ||
41 | /* | |
42 | * List of global SA11x0 peripheral registers to preserve. | |
43 | * More ones like CP and general purpose register values are preserved | |
44 | * on the stack and then the stack pointer is stored last in sleep.S. | |
45 | */ | |
46 | enum { SLEEP_SAVE_SP = 0, | |
47 | ||
48 | SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR, | |
49 | SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR, | |
50 | ||
51 | SLEEP_SAVE_Ser1SDCR0, | |
52 | ||
53 | SLEEP_SAVE_SIZE | |
54 | }; | |
55 | ||
56 | ||
57 | static int sa11x0_pm_enter(suspend_state_t state) | |
58 | { | |
59 | unsigned long gpio, sleep_save[SLEEP_SAVE_SIZE]; | |
1da177e4 | 60 | |
1da177e4 LT |
61 | gpio = GPLR; |
62 | ||
63 | /* save vital registers */ | |
64 | SAVE(GPDR); | |
65 | SAVE(GAFR); | |
66 | ||
67 | SAVE(PPDR); | |
68 | SAVE(PPSR); | |
69 | SAVE(PPAR); | |
70 | SAVE(PSDR); | |
71 | ||
72 | SAVE(Ser1SDCR0); | |
73 | ||
74 | /* Clear previous reset status */ | |
75 | RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR; | |
76 | ||
77 | /* set resume return address */ | |
78 | PSPR = virt_to_phys(sa1100_cpu_resume); | |
79 | ||
80 | /* go zzz */ | |
81 | sa1100_cpu_suspend(); | |
82 | ||
36c5ed23 RK |
83 | cpu_init(); |
84 | ||
1da177e4 LT |
85 | /* |
86 | * Ensure not to come back here if it wasn't intended | |
87 | */ | |
88 | PSPR = 0; | |
89 | ||
90 | /* | |
91 | * Ensure interrupt sources are disabled; we will re-init | |
92 | * the interrupt subsystem via the device manager. | |
93 | */ | |
94 | ICLR = 0; | |
95 | ICCR = 1; | |
96 | ICMR = 0; | |
97 | ||
98 | /* restore registers */ | |
99 | RESTORE(GPDR); | |
100 | RESTORE(GAFR); | |
101 | ||
102 | RESTORE(PPDR); | |
103 | RESTORE(PPSR); | |
104 | RESTORE(PPAR); | |
105 | RESTORE(PSDR); | |
106 | ||
107 | RESTORE(Ser1SDCR0); | |
108 | ||
109 | GPSR = gpio; | |
110 | GPCR = ~gpio; | |
111 | ||
112 | /* | |
113 | * Clear the peripheral sleep-hold bit. | |
114 | */ | |
115 | PSSR = PSSR_PH; | |
116 | ||
1da177e4 LT |
117 | return 0; |
118 | } | |
119 | ||
120 | unsigned long sleep_phys_sp(void *sp) | |
121 | { | |
122 | return virt_to_phys(sp); | |
123 | } | |
124 | ||
26398a70 | 125 | static struct platform_suspend_ops sa11x0_pm_ops = { |
1da177e4 | 126 | .enter = sa11x0_pm_enter, |
26398a70 | 127 | .valid = suspend_valid_only_mem, |
1da177e4 LT |
128 | }; |
129 | ||
130 | static int __init sa11x0_pm_init(void) | |
131 | { | |
26398a70 | 132 | suspend_set_ops(&sa11x0_pm_ops); |
1da177e4 LT |
133 | return 0; |
134 | } | |
135 | ||
136 | late_initcall(sa11x0_pm_init); |