projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| cfa66a81 KM |
1 | /* |
| 2 | * Bock-W board support | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
| 5 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License as published by | |
| 9 | * the Free Software Foundation; version 2 of the License. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU General Public License | |
| 17 | * along with this program; if not, write to the Free Software | |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
| 19 | */ | |
| 20 | ||
| 21 | #include <linux/of_platform.h> | |
| cfa66a81 KM |
22 | #include <mach/common.h> |
| 23 | #include <mach/r8a7778.h> | |
| 24 | #include <asm/mach/arch.h> | |
| 25 | ||
| 26 | /* | |
| 27 | * see board-bock.c for checking detail of dip-switch | |
| 28 | */ | |
| 29 | ||
| 90357fcb KM |
30 | #define FPGA 0x18200000 |
| 31 | #define IRQ0MR 0x30 | |
| 32 | #define COMCTLR 0x101c | |
| 79990c16 KM |
33 | |
| 34 | #define PFC 0xfffc0000 | |
| 35 | #define PUPR4 0x110 | |
| cfa66a81 KM |
36 | static void __init bockw_init(void) |
| 37 | { | |
| b6d3eba3 | 38 | void __iomem *fpga; |
| 79990c16 | 39 | void __iomem *pfc; |
| 90357fcb | 40 | |
| cfa66a81 | 41 | r8a7778_clock_init(); |
| 90357fcb | 42 | r8a7778_init_irq_extpin_dt(1); |
| cfa66a81 KM |
43 | r8a7778_add_dt_devices(); |
| 44 | ||
| 90357fcb KM |
45 | fpga = ioremap_nocache(FPGA, SZ_1M); |
| 46 | if (fpga) { | |
| 47 | /* | |
| 48 | * CAUTION | |
| 49 | * | |
| 50 | * IRQ0/1 is cascaded interrupt from FPGA. | |
| 51 | * it should be cared in the future | |
| 52 | * Now, it is assuming IRQ0 was used only from SMSC. | |
| 53 | */ | |
| 54 | u16 val = ioread16(fpga + IRQ0MR); | |
| 55 | val &= ~(1 << 4); /* enable SMSC911x */ | |
| 56 | iowrite16(val, fpga + IRQ0MR); | |
| b6d3eba3 KM |
57 | |
| 58 | iounmap(fpga); | |
| 90357fcb KM |
59 | } |
| 60 | ||
| 79990c16 KM |
61 | pfc = ioremap_nocache(PFC, 0x200); |
| 62 | if (pfc) { | |
| 63 | /* | |
| 64 | * FIXME | |
| 65 | * | |
| 66 | * SDHI CD/WP pin needs pull-up | |
| 67 | */ | |
| 68 | iowrite32(ioread32(pfc + PUPR4) | (3 << 26), pfc + PUPR4); | |
| 69 | iounmap(pfc); | |
| 90357fcb KM |
70 | } |
| 71 | ||
| cfa66a81 KM |
72 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 73 | } | |
| 74 | ||
| 75 | static const char *bockw_boards_compat_dt[] __initdata = { | |
| 76 | "renesas,bockw-reference", | |
| 77 | NULL, | |
| 78 | }; | |
| 79 | ||
| 80 | DT_MACHINE_START(BOCKW_DT, "bockw") | |
| 81 | .init_early = r8a7778_init_delay, | |
| 82 | .init_irq = r8a7778_init_irq_dt, | |
| 83 | .init_machine = bockw_init, | |
| cfa66a81 KM |
84 | .dt_compat = bockw_boards_compat_dt, |
| 85 | MACHINE_END |