[deliverable/linux.git] / arch / arm / mach-shmobile / board-lager.c

/*
 * Lager board support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/leds.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/camera-rcar.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/rcar-du.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/gpio-regulator.h>
#include <linux/regulator/machine.h>
#include <linux/sh_eth.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7790.h>
#include <media/soc_camera.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/mtd.h>
#include <linux/spi/flash.h>
#include <linux/spi/rspi.h>
#include <linux/spi/spi.h>

/* DU */
static struct rcar_du_encoder_data lager_du_encoders[] = {
	{
		.type = RCAR_DU_ENCODER_VGA,
		.output = RCAR_DU_OUTPUT_DPAD0,
	}, {
		.type = RCAR_DU_ENCODER_NONE,
		.output = RCAR_DU_OUTPUT_LVDS1,
		.connector.lvds.panel = {
			.width_mm = 210,
			.height_mm = 158,
			.mode = {
				.clock = 65000,
				.hdisplay = 1024,
				.hsync_start = 1048,
				.hsync_end = 1184,
				.htotal = 1344,
				.vdisplay = 768,
				.vsync_start = 771,
				.vsync_end = 777,
				.vtotal = 806,
				.flags = 0,
			},
		},
	},
};

static const struct rcar_du_platform_data lager_du_pdata __initconst = {
	.encoders = lager_du_encoders,
	.num_encoders = ARRAY_SIZE(lager_du_encoders),
};

static const struct resource du_resources[] __initconst = {
	DEFINE_RES_MEM(0xfeb00000, 0x70000),
	DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
	DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"),
	DEFINE_RES_IRQ(gic_spi(256)),
	DEFINE_RES_IRQ(gic_spi(268)),
	DEFINE_RES_IRQ(gic_spi(269)),
};

static void __init lager_add_du_device(void)
{
	struct platform_device_info info = {
		.name = "rcar-du-r8a7790",
		.id = -1,
		.res = du_resources,
		.num_res = ARRAY_SIZE(du_resources),
		.data = &lager_du_pdata,
		.size_data = sizeof(lager_du_pdata),
		.dma_mask = DMA_BIT_MASK(32),
	};

	platform_device_register_full(&info);
}

/* LEDS */
static struct gpio_led lager_leds[] = {
	{
		.name		= "led8",
		.gpio		= RCAR_GP_PIN(5, 17),
		.default_state	= LEDS_GPIO_DEFSTATE_ON,
	}, {
		.name		= "led7",
		.gpio		= RCAR_GP_PIN(4, 23),
		.default_state	= LEDS_GPIO_DEFSTATE_ON,
	}, {
		.name		= "led6",
		.gpio		= RCAR_GP_PIN(4, 22),
		.default_state	= LEDS_GPIO_DEFSTATE_ON,
	},
};

static const struct gpio_led_platform_data lager_leds_pdata __initconst = {
	.leds		= lager_leds,
	.num_leds	= ARRAY_SIZE(lager_leds),
};

/* GPIO KEY */
#define GPIO_KEY(c, g, d, ...) \
	{ .code = c, .gpio = g, .desc = d, .active_low = 1, \
	  .wakeup = 1, .debounce_interval = 20 }

static struct gpio_keys_button gpio_buttons[] = {
	GPIO_KEY(KEY_4,		RCAR_GP_PIN(1, 28),	"SW2-pin4"),
	GPIO_KEY(KEY_3,		RCAR_GP_PIN(1, 26),	"SW2-pin3"),
	GPIO_KEY(KEY_2,		RCAR_GP_PIN(1, 24),	"SW2-pin2"),
	GPIO_KEY(KEY_1,		RCAR_GP_PIN(1, 14),	"SW2-pin1"),
};

static const struct gpio_keys_platform_data lager_keys_pdata __initconst = {
	.buttons	= gpio_buttons,
	.nbuttons	= ARRAY_SIZE(gpio_buttons),
};

/* Fixed 3.3V regulator to be used by MMCIF */
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
{
	REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"),
};

/*
 * SDHI regulator macro
 *
 ** FIXME**
 * Lager board vqmmc is provided via DA9063 PMIC chip,
 * and we should use ${LINK}/drivers/mfd/da9063-* driver for it.
 * but, it doesn't have regulator support at this point.
 * It uses gpio-regulator for vqmmc as quick-hack.
 */
#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin)				\
static struct regulator_consumer_supply vcc_sdhi##idx##_consumer =	\
	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx);		\
									\
static struct regulator_init_data vcc_sdhi##idx##_init_data = {		\
	.constraints = {						\
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,		\
	},								\
	.consumer_supplies	= &vcc_sdhi##idx##_consumer,		\
	.num_consumer_supplies	= 1,					\
};									\
									\
static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
	.supply_name	= "SDHI" #idx "Vcc",				\
	.microvolts	= 3300000,					\
	.gpio		= vdd_pin,					\
	.enable_high	= 1,						\
	.init_data	= &vcc_sdhi##idx##_init_data,			\
};									\
									\
static struct regulator_consumer_supply vccq_sdhi##idx##_consumer =	\
	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx);		\
									\
static struct regulator_init_data vccq_sdhi##idx##_init_data = {	\
	.constraints = {						\
		.input_uV	= 3300000,				\
		.min_uV		= 1800000,				\
		.max_uV		= 3300000,				\
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |		\
				  REGULATOR_CHANGE_STATUS,		\
	},								\
	.consumer_supplies	= &vccq_sdhi##idx##_consumer,		\
	.num_consumer_supplies	= 1,					\
};									\
									\
static struct gpio vccq_sdhi##idx##_gpio =				\
	{ vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx };		\
									\
static struct gpio_regulator_state vccq_sdhi##idx##_states[] = {	\
	{ .value = 1800000, .gpios = 0 },				\
	{ .value = 3300000, .gpios = 1 },				\
};									\
									\
static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
	.supply_name	= "vqmmc",					\
	.gpios		= &vccq_sdhi##idx##_gpio,			\
	.nr_gpios	= 1,						\
	.states		= vccq_sdhi##idx##_states,			\
	.nr_states	= ARRAY_SIZE(vccq_sdhi##idx##_states),		\
	.type		= REGULATOR_VOLTAGE,				\
	.init_data	= &vccq_sdhi##idx##_init_data,			\
};

SDHI_REGULATOR(0, RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 29));
SDHI_REGULATOR(2, RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 30));

/* MMCIF */
static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = {
	.caps		= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
	.clk_ctrl2_present = true,
	.ccs_unsupported = true,
};

static const struct resource mmcif1_resources[] __initconst = {
	DEFINE_RES_MEM(0xee220000, 0x80),
	DEFINE_RES_IRQ(gic_spi(170)),
};

/* Ether */
static const struct sh_eth_plat_data ether_pdata __initconst = {
	.phy			= 0x1,
	.edmac_endian		= EDMAC_LITTLE_ENDIAN,
	.phy_interface		= PHY_INTERFACE_MODE_RMII,
	.ether_link_active_low	= 1,
};

static const struct resource ether_resources[] __initconst = {
	DEFINE_RES_MEM(0xee700000, 0x400),
	DEFINE_RES_IRQ(gic_spi(162)),
};

/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */
static struct mtd_partition spi_flash_part[] = {
	/* Reserved for user loader program, read-only */
	{
		.name = "loader",
		.offset = 0,
		.size = SZ_256K,
		.mask_flags = MTD_WRITEABLE,
	},
	/* Reserved for user program, read-only */
	{
		.name = "user",
		.offset = MTDPART_OFS_APPEND,
		.size = SZ_4M,
		.mask_flags = MTD_WRITEABLE,
	},
	/* All else is writable (e.g. JFFS2) */
	{
		.name = "flash",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
		.mask_flags = 0,
	},
};

static const struct flash_platform_data spi_flash_data = {
	.name           = "m25p80",
	.parts          = spi_flash_part,
	.nr_parts       = ARRAY_SIZE(spi_flash_part),
	.type           = "s25fl512s",
};

static const struct rspi_plat_data qspi_pdata __initconst = {
	.num_chipselect	= 1,
};

static const struct spi_board_info spi_info[] __initconst = {
	{
		.modalias               = "m25p80",
		.platform_data          = &spi_flash_data,
		.mode                   = SPI_MODE_0,
		.max_speed_hz           = 30000000,
		.bus_num                = 0,
		.chip_select            = 0,
	},
};

/* QSPI resource */
static const struct resource qspi_resources[] __initconst = {
	DEFINE_RES_MEM(0xe6b10000, 0x1000),
	DEFINE_RES_IRQ(gic_spi(184)),
};

/* VIN */
static const struct resource vin_resources[] __initconst = {
	/* VIN0 */
	DEFINE_RES_MEM(0xe6ef0000, 0x1000),
	DEFINE_RES_IRQ(gic_spi(188)),
	/* VIN1 */
	DEFINE_RES_MEM(0xe6ef1000, 0x1000),
	DEFINE_RES_IRQ(gic_spi(189)),
};

static void __init lager_add_vin_device(unsigned idx,
					struct rcar_vin_platform_data *pdata)
{
	struct platform_device_info vin_info = {
		.parent		= &platform_bus,
		.name		= "r8a7790-vin",
		.id		= idx,
		.res		= &vin_resources[idx * 2],
		.num_res	= 2,
		.dma_mask	= DMA_BIT_MASK(32),
		.data		= pdata,
		.size_data	= sizeof(*pdata),
	};

	BUG_ON(idx > 1);

	platform_device_register_full(&vin_info);
}

#define LAGER_CAMERA(idx, name, addr, pdata, flag)			\
static struct i2c_board_info i2c_cam##idx##_device = {			\
	I2C_BOARD_INFO(name, addr),					\
};									\
									\
static struct rcar_vin_platform_data vin##idx##_pdata = {		\
	.flags = flag,							\
};									\
									\
static struct soc_camera_link cam##idx##_link = {			\
	.bus_id = idx,							\
	.board_info = &i2c_cam##idx##_device,				\
	.i2c_adapter_id = 2,						\
	.module_name = name,						\
	.priv = pdata,							\
}

/* Camera 0 is not currently supported due to adv7612 support missing */
LAGER_CAMERA(1, "adv7180", 0x20, NULL, RCAR_VIN_BT656);

static void __init lager_add_camera1_device(void)
{
	platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1,
				      &cam1_link, sizeof(cam1_link));
	lager_add_vin_device(1, &vin1_pdata);
}

static const struct pinctrl_map lager_pinctrl_map[] = {
	/* DU (CN10: ARGB0, CN13: LVDS) */
	PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
				  "du_rgb666", "du"),
	PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
				  "du_sync_1", "du"),
	PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
				  "du_clk_out_0", "du"),
	/* SCIF0 (CN19: DEBUG SERIAL0) */
	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
				  "scif0_data", "scif0"),
	/* SCIF1 (CN20: DEBUG SERIAL1) */
	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
				  "scif1_data", "scif1"),
	/* MMCIF1 */
	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
				  "mmc1_data8", "mmc1"),
	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
				  "mmc1_ctrl", "mmc1"),
	/* Ether */
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
				  "eth_link", "eth"),
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
				  "eth_mdio", "eth"),
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
				  "eth_rmii", "eth"),
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
				  "intc_irq0", "intc"),
	/* VIN0 */
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
				  "vin0_data24", "vin0"),
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
				  "vin0_sync", "vin0"),
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
				  "vin0_field", "vin0"),
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
				  "vin0_clkenb", "vin0"),
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
				  "vin0_clk", "vin0"),
	/* VIN1 */
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
				  "vin1_data8", "vin1"),
	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
				  "vin1_clk", "vin1"),
};

static void __init lager_add_standard_devices(void)
{
	int fixed_regulator_idx = 0;
	int gpio_regulator_idx = 0;

	r8a7790_clock_init();

	pinctrl_register_mappings(lager_pinctrl_map,
				  ARRAY_SIZE(lager_pinctrl_map));
	r8a7790_pinmux_init();

	r8a7790_add_standard_devices();
	platform_device_register_data(&platform_bus, "leds-gpio", -1,
				      &lager_leds_pdata,
				      sizeof(lager_leds_pdata));
	platform_device_register_data(&platform_bus, "gpio-keys", -1,
				      &lager_keys_pdata,
				      sizeof(lager_keys_pdata));
	regulator_register_always_on(fixed_regulator_idx++,
				     "fixed-3.3V", fixed3v3_power_consumers,
				     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
	platform_device_register_resndata(&platform_bus, "sh_mmcif", 1,
					  mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
					  &mmcif1_pdata, sizeof(mmcif1_pdata));

	platform_device_register_resndata(&platform_bus, "r8a7790-ether", -1,
					  ether_resources,
					  ARRAY_SIZE(ether_resources),
					  &ether_pdata, sizeof(ether_pdata));

	lager_add_du_device();

	platform_device_register_resndata(&platform_bus, "qspi", 0,
					  qspi_resources,
					  ARRAY_SIZE(qspi_resources),
					  &qspi_pdata, sizeof(qspi_pdata));
	spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));

	platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++,
				      &vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
	platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++,
				      &vcc_sdhi2_info, sizeof(struct fixed_voltage_config));

	platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
				      &vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
	platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
				      &vccq_sdhi2_info, sizeof(struct gpio_regulator_config));

	lager_add_camera1_device();
}

/*
 * Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
 * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
 * 14-15. We have to set them back to 01 from the default 00 value each time
 * the PHY is reset. It's also important because the PHY's LED0 signal is
 * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
 * bounce on and off after each packet, which we apparently want to avoid.
 */
static int lager_ksz8041_fixup(struct phy_device *phydev)
{
	u16 phyctrl1 = phy_read(phydev, 0x1e);

	phyctrl1 &= ~0xc000;
	phyctrl1 |= 0x4000;
	return phy_write(phydev, 0x1e, phyctrl1);
}

static void __init lager_init(void)
{
	lager_add_standard_devices();

	if (IS_ENABLED(CONFIG_PHYLIB))
		phy_register_fixup_for_id("r8a7790-ether-ff:01",
					  lager_ksz8041_fixup);
}

static const char * const lager_boards_compat_dt[] __initconst = {
	"renesas,lager",
	NULL,
};

DT_MACHINE_START(LAGER_DT, "lager")
	.smp		= smp_ops(r8a7790_smp_ops),
	.init_early	= r8a7790_init_early,
	.init_time	= rcar_gen2_timer_init,
	.init_machine	= lager_init,
	.init_late	= shmobile_init_late,
	.dt_compat	= lager_boards_compat_dt,
MACHINE_END
Commit	Line	Data
3cc828fd MD	1	/*
	2	* Lager board support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20
c3842e4f SH	21	#include <linux/gpio.h>
	22	#include <linux/gpio_keys.h>
	23	#include <linux/input.h>
3cc828fd	24	#include <linux/interrupt.h>
3cc828fd	25	#include <linux/kernel.h>
1034f4ee	26	#include <linux/leds.h>
63d0539e GL	27	#include <linux/mmc/host.h>
63d0539e GL	28	#include <linux/mmc/sh_mmcif.h>
e3a28ac2	29	#include <linux/pinctrl/machine.h>
094a804a	30	#include <linux/platform_data/camera-rcar.h>
1034f4ee	31	#include <linux/platform_data/gpio-rcar.h>
c75a5afa	32	#include <linux/platform_data/rcar-du.h>
3cc828fd	33	#include <linux/platform_device.h>
48c8b96f	34	#include <linux/phy.h>
be0647d5	35	#include <linux/regulator/driver.h>
63d0539e	36	#include <linux/regulator/fixed.h>
be0647d5	37	#include <linux/regulator/gpio-regulator.h>
63d0539e	38	#include <linux/regulator/machine.h>
4901e136	39	#include <linux/sh_eth.h>
3cc828fd	40	#include <mach/common.h>
63d0539e	41	#include <mach/irqs.h>
3cc828fd	42	#include <mach/r8a7790.h>
094a804a	43	#include <media/soc_camera.h>
3cc828fd MD	44	#include <asm/mach-types.h>
3cc828fd MD	45	#include <asm/mach/arch.h>
24cf82f4 HCM	46	#include <linux/mtd/partitions.h>
	47	#include <linux/mtd/mtd.h>
	48	#include <linux/spi/flash.h>
	49	#include <linux/spi/rspi.h>
	50	#include <linux/spi/spi.h>
3cc828fd	51
c75a5afa LP	52	/* DU */
	53	static struct rcar_du_encoder_data lager_du_encoders[] = {
	54	{
	55	.type = RCAR_DU_ENCODER_VGA,
	56	.output = RCAR_DU_OUTPUT_DPAD0,
	57	}, {
	58	.type = RCAR_DU_ENCODER_NONE,
	59	.output = RCAR_DU_OUTPUT_LVDS1,
	60	.connector.lvds.panel = {
	61	.width_mm = 210,
	62	.height_mm = 158,
	63	.mode = {
	64	.clock = 65000,
	65	.hdisplay = 1024,
	66	.hsync_start = 1048,
	67	.hsync_end = 1184,
	68	.htotal = 1344,
	69	.vdisplay = 768,
	70	.vsync_start = 771,
	71	.vsync_end = 777,
	72	.vtotal = 806,
	73	.flags = 0,
	74	},
	75	},
	76	},
	77	};
	78
	79	static const struct rcar_du_platform_data lager_du_pdata __initconst = {
	80	.encoders = lager_du_encoders,
	81	.num_encoders = ARRAY_SIZE(lager_du_encoders),
	82	};
	83
	84	static const struct resource du_resources[] __initconst = {
	85	DEFINE_RES_MEM(0xfeb00000, 0x70000),
	86	DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
	87	DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"),
	88	DEFINE_RES_IRQ(gic_spi(256)),
	89	DEFINE_RES_IRQ(gic_spi(268)),
	90	DEFINE_RES_IRQ(gic_spi(269)),
	91	};
	92
	93	static void __init lager_add_du_device(void)
	94	{
	95	struct platform_device_info info = {
	96	.name = "rcar-du-r8a7790",
	97	.id = -1,
	98	.res = du_resources,
	99	.num_res = ARRAY_SIZE(du_resources),
37bf8103 LP	100	.data = &lager_du_pdata,
37bf8103 LP	101	.size_data = sizeof(lager_du_pdata),
c75a5afa LP	102	.dma_mask = DMA_BIT_MASK(32),
	103	};
	104
	105	platform_device_register_full(&info);
	106	}
	107
1034f4ee SH	108	/* LEDS */
	109	static struct gpio_led lager_leds[] = {
	110	{
	111	.name = "led8",
	112	.gpio = RCAR_GP_PIN(5, 17),
	113	.default_state = LEDS_GPIO_DEFSTATE_ON,
	114	}, {
	115	.name = "led7",
	116	.gpio = RCAR_GP_PIN(4, 23),
	117	.default_state = LEDS_GPIO_DEFSTATE_ON,
	118	}, {
	119	.name = "led6",
	120	.gpio = RCAR_GP_PIN(4, 22),
	121	.default_state = LEDS_GPIO_DEFSTATE_ON,
	122	},
	123	};
	124
27113d63	125	static const struct gpio_led_platform_data lager_leds_pdata __initconst = {
1034f4ee SH	126	.leds = lager_leds,
	127	.num_leds = ARRAY_SIZE(lager_leds),
	128	};
	129
c3842e4f SH	130	/* GPIO KEY */
c3842e4f SH	131	#define GPIO_KEY(c, g, d, ...) \
c9fd77d4	132	{ .code = c, .gpio = g, .desc = d, .active_low = 1, \
e0554d90	133	.wakeup = 1, .debounce_interval = 20 }
c3842e4f	134
a6014693	135	static struct gpio_keys_button gpio_buttons[] = {
c3842e4f SH	136	GPIO_KEY(KEY_4, RCAR_GP_PIN(1, 28), "SW2-pin4"),
	137	GPIO_KEY(KEY_3, RCAR_GP_PIN(1, 26), "SW2-pin3"),
	138	GPIO_KEY(KEY_2, RCAR_GP_PIN(1, 24), "SW2-pin2"),
	139	GPIO_KEY(KEY_1, RCAR_GP_PIN(1, 14), "SW2-pin1"),
	140	};
	141
27113d63	142	static const struct gpio_keys_platform_data lager_keys_pdata __initconst = {
c3842e4f SH	143	.buttons = gpio_buttons,
	144	.nbuttons = ARRAY_SIZE(gpio_buttons),
	145	};
	146
63d0539e GL	147	/* Fixed 3.3V regulator to be used by MMCIF */
	148	static struct regulator_consumer_supply fixed3v3_power_consumers[] =
	149	{
	150	REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"),
	151	};
	152
be0647d5 KM	153	/*
	154	* SDHI regulator macro
	155	*
	156	FIXME
	157	* Lager board vqmmc is provided via DA9063 PMIC chip,
	158	* and we should use ${LINK}/drivers/mfd/da9063-* driver for it.
	159	* but, it doesn't have regulator support at this point.
	160	* It uses gpio-regulator for vqmmc as quick-hack.
	161	*/
	162	#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin) \
	163	static struct regulator_consumer_supply vcc_sdhi##idx##_consumer = \
	164	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx); \
	165	\
	166	static struct regulator_init_data vcc_sdhi##idx##_init_data = { \
	167	.constraints = { \
	168	.valid_ops_mask = REGULATOR_CHANGE_STATUS, \
	169	}, \
	170	.consumer_supplies = &vcc_sdhi##idx##_consumer, \
	171	.num_consumer_supplies = 1, \
	172	}; \
	173	\
	174	static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
	175	.supply_name = "SDHI" #idx "Vcc", \
	176	.microvolts = 3300000, \
	177	.gpio = vdd_pin, \
	178	.enable_high = 1, \
	179	.init_data = &vcc_sdhi##idx##_init_data, \
	180	}; \
	181	\
	182	static struct regulator_consumer_supply vccq_sdhi##idx##_consumer = \
	183	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx); \
	184	\
	185	static struct regulator_init_data vccq_sdhi##idx##_init_data = { \
	186	.constraints = { \
	187	.input_uV = 3300000, \
	188	.min_uV = 1800000, \
	189	.max_uV = 3300000, \
	190	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \| \
	191	REGULATOR_CHANGE_STATUS, \
	192	}, \
	193	.consumer_supplies = &vccq_sdhi##idx##_consumer, \
	194	.num_consumer_supplies = 1, \
	195	}; \
	196	\
	197	static struct gpio vccq_sdhi##idx##_gpio = \
	198	{ vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx }; \
	199	\
	200	static struct gpio_regulator_state vccq_sdhi##idx##_states[] = { \
	201	{ .value = 1800000, .gpios = 0 }, \
	202	{ .value = 3300000, .gpios = 1 }, \
	203	}; \
	204	\
	205	static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
	206	.supply_name = "vqmmc", \
	207	.gpios = &vccq_sdhi##idx##_gpio, \
	208	.nr_gpios = 1, \
	209	.states = vccq_sdhi##idx##_states, \
	210	.nr_states = ARRAY_SIZE(vccq_sdhi##idx##_states), \
	211	.type = REGULATOR_VOLTAGE, \
	212	.init_data = &vccq_sdhi##idx##_init_data, \
	213	};
	214
	215	SDHI_REGULATOR(0, RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 29));
	216	SDHI_REGULATOR(2, RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 30));
217
63d0539e	218	/* MMCIF */
27113d63	219	static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = {
63d0539e	220	.caps = MMC_CAP_8_BIT_DATA \| MMC_CAP_NONREMOVABLE,
b77c6bce GL	221	.clk_ctrl2_present = true,
b77c6bce GL	222	.ccs_unsupported = true,
63d0539e GL	223	};
63d0539e GL	224
27113d63	225	static const struct resource mmcif1_resources[] __initconst = {
b7b42df6	226	DEFINE_RES_MEM(0xee220000, 0x80),
63d0539e GL	227	DEFINE_RES_IRQ(gic_spi(170)),
	228	};
	229
4901e136	230	/* Ether */
27113d63	231	static const struct sh_eth_plat_data ether_pdata __initconst = {
4901e136 SH	232	.phy = 0x1,
4901e136 SH	233	.edmac_endian = EDMAC_LITTLE_ENDIAN,
4901e136 SH	234	.phy_interface = PHY_INTERFACE_MODE_RMII,
	235	.ether_link_active_low = 1,
	236	};
	237
27113d63	238	static const struct resource ether_resources[] __initconst = {
4901e136 SH	239	DEFINE_RES_MEM(0xee700000, 0x400),
	240	DEFINE_RES_IRQ(gic_spi(162)),
	241	};
	242
24cf82f4 HCM	243	/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64Mb) */
	244	static struct mtd_partition spi_flash_part[] = {
	245	/* Reserved for user loader program, read-only */
	246	{
	247	.name = "loader",
	248	.offset = 0,
	249	.size = SZ_256K,
	250	.mask_flags = MTD_WRITEABLE,
	251	},
	252	/* Reserved for user program, read-only */
	253	{
	254	.name = "user",
	255	.offset = MTDPART_OFS_APPEND,
	256	.size = SZ_4M,
	257	.mask_flags = MTD_WRITEABLE,
	258	},
	259	/* All else is writable (e.g. JFFS2) */
	260	{
	261	.name = "flash",
	262	.offset = MTDPART_OFS_APPEND,
	263	.size = MTDPART_SIZ_FULL,
	264	.mask_flags = 0,
	265	},
	266	};
	267
d422c451	268	static const struct flash_platform_data spi_flash_data = {
24cf82f4 HCM	269	.name = "m25p80",
	270	.parts = spi_flash_part,
	271	.nr_parts = ARRAY_SIZE(spi_flash_part),
	272	.type = "s25fl512s",
	273	};
	274
	275	static const struct rspi_plat_data qspi_pdata __initconst = {
	276	.num_chipselect = 1,
	277	};
	278
	279	static const struct spi_board_info spi_info[] __initconst = {
	280	{
	281	.modalias = "m25p80",
	282	.platform_data = &spi_flash_data,
	283	.mode = SPI_MODE_0,
	284	.max_speed_hz = 30000000,
	285	.bus_num = 0,
	286	.chip_select = 0,
	287	},
	288	};
	289
	290	/* QSPI resource */
	291	static const struct resource qspi_resources[] __initconst = {
	292	DEFINE_RES_MEM(0xe6b10000, 0x1000),
	293	DEFINE_RES_IRQ(gic_spi(184)),
	294	};
	295
094a804a VB	296	/* VIN */
	297	static const struct resource vin_resources[] __initconst = {
	298	/* VIN0 */
	299	DEFINE_RES_MEM(0xe6ef0000, 0x1000),
	300	DEFINE_RES_IRQ(gic_spi(188)),
	301	/* VIN1 */
	302	DEFINE_RES_MEM(0xe6ef1000, 0x1000),
	303	DEFINE_RES_IRQ(gic_spi(189)),
	304	};
	305
	306	static void __init lager_add_vin_device(unsigned idx,
	307	struct rcar_vin_platform_data *pdata)
	308	{
	309	struct platform_device_info vin_info = {
	310	.parent = &platform_bus,
	311	.name = "r8a7790-vin",
	312	.id = idx,
	313	.res = &vin_resources[idx * 2],
	314	.num_res = 2,
	315	.dma_mask = DMA_BIT_MASK(32),
	316	.data = pdata,
	317	.size_data = sizeof(*pdata),
	318	};
	319
	320	BUG_ON(idx > 1);
	321
	322	platform_device_register_full(&vin_info);
	323	}
	324
	325	#define LAGER_CAMERA(idx, name, addr, pdata, flag) \
	326	static struct i2c_board_info i2c_cam##idx##_device = { \
	327	I2C_BOARD_INFO(name, addr), \
	328	}; \
	329	\
	330	static struct rcar_vin_platform_data vin##idx##_pdata = { \
	331	.flags = flag, \
	332	}; \
	333	\
	334	static struct soc_camera_link cam##idx##_link = { \
	335	.bus_id = idx, \
	336	.board_info = &i2c_cam##idx##_device, \
	337	.i2c_adapter_id = 2, \
	338	.module_name = name, \
	339	.priv = pdata, \
	340	}
	341
	342	/* Camera 0 is not currently supported due to adv7612 support missing */
	343	LAGER_CAMERA(1, "adv7180", 0x20, NULL, RCAR_VIN_BT656);
	344
	345	static void __init lager_add_camera1_device(void)
	346	{
	347	platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1,
	348	&cam1_link, sizeof(cam1_link));
	349	lager_add_vin_device(1, &vin1_pdata);
	350	}
	351
e3a28ac2	352	static const struct pinctrl_map lager_pinctrl_map[] = {
c75a5afa LP	353	/* DU (CN10: ARGB0, CN13: LVDS) */
	354	PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
	355	"du_rgb666", "du"),
	356	PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
	357	"du_sync_1", "du"),
	358	PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
	359	"du_clk_out_0", "du"),
e3a28ac2 LP	360	/* SCIF0 (CN19: DEBUG SERIAL0) */
	361	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
	362	"scif0_data", "scif0"),
	363	/* SCIF1 (CN20: DEBUG SERIAL1) */
	364	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
	365	"scif1_data", "scif1"),
63d0539e GL	366	/* MMCIF1 */
	367	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
	368	"mmc1_data8", "mmc1"),
	369	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
	370	"mmc1_ctrl", "mmc1"),
4901e136 SH	371	/* Ether */
	372	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
	373	"eth_link", "eth"),
	374	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
	375	"eth_mdio", "eth"),
	376	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
	377	"eth_rmii", "eth"),
	378	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
	379	"intc_irq0", "intc"),
094a804a VB	380	/* VIN0 */
	381	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
	382	"vin0_data24", "vin0"),
	383	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
	384	"vin0_sync", "vin0"),
	385	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
	386	"vin0_field", "vin0"),
	387	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
	388	"vin0_clkenb", "vin0"),
	389	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
	390	"vin0_clk", "vin0"),
	391	/* VIN1 */
	392	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
	393	"vin1_data8", "vin1"),
	394	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
	395	"vin1_clk", "vin1"),
e3a28ac2 LP	396	};
e3a28ac2 LP	397
3cc828fd MD	398	static void __init lager_add_standard_devices(void)
3cc828fd MD	399	{
be0647d5 KM	400	int fixed_regulator_idx = 0;
	401	int gpio_regulator_idx = 0;
	402
3cc828fd	403	r8a7790_clock_init();
e3a28ac2 LP	404
	405	pinctrl_register_mappings(lager_pinctrl_map,
	406	ARRAY_SIZE(lager_pinctrl_map));
	407	r8a7790_pinmux_init();
	408
3cc828fd	409	r8a7790_add_standard_devices();
1034f4ee SH	410	platform_device_register_data(&platform_bus, "leds-gpio", -1,
	411	&lager_leds_pdata,
	412	sizeof(lager_leds_pdata));
c3842e4f SH	413	platform_device_register_data(&platform_bus, "gpio-keys", -1,
	414	&lager_keys_pdata,
	415	sizeof(lager_keys_pdata));
be0647d5 KM	416	regulator_register_always_on(fixed_regulator_idx++,
be0647d5 KM	417	"fixed-3.3V", fixed3v3_power_consumers,
63d0539e GL	418	ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
	419	platform_device_register_resndata(&platform_bus, "sh_mmcif", 1,
	420	mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
	421	&mmcif1_pdata, sizeof(mmcif1_pdata));
4901e136 SH	422
	423	platform_device_register_resndata(&platform_bus, "r8a7790-ether", -1,
	424	ether_resources,
	425	ARRAY_SIZE(ether_resources),
	426	&ether_pdata, sizeof(ether_pdata));
c75a5afa LP	427
c75a5afa LP	428	lager_add_du_device();
24cf82f4 HCM	429
	430	platform_device_register_resndata(&platform_bus, "qspi", 0,
	431	qspi_resources,
	432	ARRAY_SIZE(qspi_resources),
	433	&qspi_pdata, sizeof(qspi_pdata));
	434	spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
be0647d5 KM	435
	436	platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++,
	437	&vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
	438	platform_device_register_data(&platform_bus, "reg-fixed-voltage", fixed_regulator_idx++,
	439	&vcc_sdhi2_info, sizeof(struct fixed_voltage_config));
	440
	441	platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
	442	&vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
	443	platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
	444	&vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
094a804a VB	445
094a804a VB	446	lager_add_camera1_device();
3cc828fd MD	447	}
3cc828fd MD	448
48c8b96f SS	449	/*
	450	* Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
	451	* to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
	452	* 14-15. We have to set them back to 01 from the default 00 value each time
	453	* the PHY is reset. It's also important because the PHY's LED0 signal is
	454	* connected to SoC's ETH_LINK signal and in the PHY's default mode it will
	455	* bounce on and off after each packet, which we apparently want to avoid.
	456	*/
	457	static int lager_ksz8041_fixup(struct phy_device *phydev)
	458	{
	459	u16 phyctrl1 = phy_read(phydev, 0x1e);
	460
	461	phyctrl1 &= ~0xc000;
	462	phyctrl1 \|= 0x4000;
	463	return phy_write(phydev, 0x1e, phyctrl1);
	464	}
	465
	466	static void __init lager_init(void)
	467	{
	468	lager_add_standard_devices();
	469
6802cdc5 SH	470	if (IS_ENABLED(CONFIG_PHYLIB))
	471	phy_register_fixup_for_id("r8a7790-ether-ff:01",
	472	lager_ksz8041_fixup);
48c8b96f SS	473	}
48c8b96f SS	474
27113d63	475	static const char * const lager_boards_compat_dt[] __initconst = {
3cc828fd MD	476	"renesas,lager",
	477	NULL,
	478	};
	479
	480	DT_MACHINE_START(LAGER_DT, "lager")
ad09cb83	481	.smp = smp_ops(r8a7790_smp_ops),
0efd7faa	482	.init_early = r8a7790_init_early,
50c517d9	483	.init_time = rcar_gen2_timer_init,
48c8b96f	484	.init_machine = lager_init,
3fbbcbdf	485	.init_late = shmobile_init_late,
3cc828fd MD	486	.dt_compat = lager_boards_compat_dt,
3cc828fd MD	487	MACHINE_END