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e3da5b36 MD |
1 | /* |
2 | * r7a72100 clock framework support | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2012 Phil Edworthy | |
6 | * Copyright (C) 2011 Magnus Damm | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | #include <linux/init.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/sh_clk.h> | |
21 | #include <linux/clkdev.h> | |
22 | #include <mach/common.h> | |
23 | #include <mach/r7s72100.h> | |
24 | ||
25 | /* registers */ | |
26 | #define FRQCR 0xfcfe0010 | |
27 | #define FRQCR2 0xfcfe0014 | |
28 | #define STBCR3 0xfcfe0420 | |
29 | #define STBCR4 0xfcfe0424 | |
30 | ||
31 | #define PLL_RATE 30 | |
32 | ||
33 | static struct clk_mapping cpg_mapping = { | |
34 | .phys = 0xfcfe0000, | |
35 | .len = 0x1000, | |
36 | }; | |
37 | ||
38 | /* Fixed 32 KHz root clock for RTC */ | |
39 | static struct clk r_clk = { | |
40 | .rate = 32768, | |
41 | }; | |
42 | ||
43 | /* | |
44 | * Default rate for the root input clock, reset this with clk_set_rate() | |
45 | * from the platform code. | |
46 | */ | |
47 | static struct clk extal_clk = { | |
48 | .rate = 13330000, | |
49 | .mapping = &cpg_mapping, | |
50 | }; | |
51 | ||
52 | static unsigned long pll_recalc(struct clk *clk) | |
53 | { | |
54 | return clk->parent->rate * PLL_RATE; | |
55 | } | |
56 | ||
57 | static struct sh_clk_ops pll_clk_ops = { | |
58 | .recalc = pll_recalc, | |
59 | }; | |
60 | ||
61 | static struct clk pll_clk = { | |
62 | .ops = &pll_clk_ops, | |
63 | .parent = &extal_clk, | |
64 | .flags = CLK_ENABLE_ON_INIT, | |
65 | }; | |
66 | ||
67 | static unsigned long bus_recalc(struct clk *clk) | |
68 | { | |
69 | return clk->parent->rate * 2 / 3; | |
70 | } | |
71 | ||
72 | static struct sh_clk_ops bus_clk_ops = { | |
73 | .recalc = bus_recalc, | |
74 | }; | |
75 | ||
76 | static struct clk bus_clk = { | |
77 | .ops = &bus_clk_ops, | |
78 | .parent = &pll_clk, | |
79 | .flags = CLK_ENABLE_ON_INIT, | |
80 | }; | |
81 | ||
82 | static unsigned long peripheral0_recalc(struct clk *clk) | |
83 | { | |
84 | return clk->parent->rate / 12; | |
85 | } | |
86 | ||
87 | static struct sh_clk_ops peripheral0_clk_ops = { | |
88 | .recalc = peripheral0_recalc, | |
89 | }; | |
90 | ||
91 | static struct clk peripheral0_clk = { | |
92 | .ops = &peripheral0_clk_ops, | |
93 | .parent = &pll_clk, | |
94 | .flags = CLK_ENABLE_ON_INIT, | |
95 | }; | |
96 | ||
97 | static unsigned long peripheral1_recalc(struct clk *clk) | |
98 | { | |
99 | return clk->parent->rate / 6; | |
100 | } | |
101 | ||
102 | static struct sh_clk_ops peripheral1_clk_ops = { | |
103 | .recalc = peripheral1_recalc, | |
104 | }; | |
105 | ||
106 | static struct clk peripheral1_clk = { | |
107 | .ops = &peripheral1_clk_ops, | |
108 | .parent = &pll_clk, | |
109 | .flags = CLK_ENABLE_ON_INIT, | |
110 | }; | |
111 | ||
112 | struct clk *main_clks[] = { | |
113 | &r_clk, | |
114 | &extal_clk, | |
115 | &pll_clk, | |
116 | &bus_clk, | |
117 | &peripheral0_clk, | |
118 | &peripheral1_clk, | |
119 | }; | |
120 | ||
121 | static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */ | |
122 | static int multipliers[] = { 1, 2, 1, 1 }; | |
123 | ||
124 | static struct clk_div_mult_table div4_div_mult_table = { | |
125 | .divisors = div2, | |
126 | .nr_divisors = ARRAY_SIZE(div2), | |
127 | .multipliers = multipliers, | |
128 | .nr_multipliers = ARRAY_SIZE(multipliers), | |
129 | }; | |
130 | ||
131 | static struct clk_div4_table div4_table = { | |
132 | .div_mult_table = &div4_div_mult_table, | |
133 | }; | |
134 | ||
135 | enum { DIV4_I, | |
136 | DIV4_NR }; | |
137 | ||
138 | #define DIV4(_reg, _bit, _mask, _flags) \ | |
139 | SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) | |
140 | ||
141 | /* The mask field specifies the div2 entries that are valid */ | |
142 | struct clk div4_clks[DIV4_NR] = { | |
143 | [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT | |
144 | | CLK_ENABLE_ON_INIT), | |
145 | }; | |
146 | ||
147 | enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, | |
148 | MSTP33, MSTP_NR }; | |
149 | ||
150 | static struct clk mstp_clks[MSTP_NR] = { | |
151 | [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ | |
152 | [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ | |
153 | [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ | |
154 | [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */ | |
155 | [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */ | |
156 | [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */ | |
157 | [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */ | |
158 | [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */ | |
159 | [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */ | |
160 | }; | |
161 | ||
162 | static struct clk_lookup lookups[] = { | |
163 | /* main clocks */ | |
164 | CLKDEV_CON_ID("rclk", &r_clk), | |
165 | CLKDEV_CON_ID("extal", &extal_clk), | |
166 | CLKDEV_CON_ID("pll_clk", &pll_clk), | |
167 | CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk), | |
168 | ||
169 | /* DIV4 clocks */ | |
170 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | |
171 | ||
172 | /* MSTP clocks */ | |
f6ca6f11 MD |
173 | CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]), |
174 | CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]), | |
175 | CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]), | |
176 | CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]), | |
177 | CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]), | |
178 | CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]), | |
179 | CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]), | |
180 | CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]), | |
e3da5b36 MD |
181 | }; |
182 | ||
183 | void __init r7s72100_clock_init(void) | |
184 | { | |
185 | int k, ret = 0; | |
186 | ||
187 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) | |
188 | ret = clk_register(main_clks[k]); | |
189 | ||
190 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | |
191 | ||
192 | if (!ret) | |
193 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); | |
194 | ||
195 | if (!ret) | |
196 | ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); | |
197 | ||
198 | if (!ret) | |
199 | shmobile_clk_init(); | |
200 | else | |
201 | panic("failed to setup rza1 clocks\n"); | |
202 | } |