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Merge tag 'iio-fixes-for-3.19a' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / mach-shmobile / clock-r8a73a4.c
CommitLineData
eccf0607
MD		 1/*
2 * r8a73a4 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
eccf0607
MD		 15 */
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/sh_clk.h>
20#include <linux/clkdev.h>
fd44aa5e 21#include "common.h"
ad6ffa0b 22#include "clock.h"
eccf0607
MD		 23
24#define CPG_BASE 0xe6150000
25#define CPG_LEN 0x270
26
e481a528 27#define SMSTPCR2 0xe6150138
111fad56 28#define SMSTPCR3 0xe615013c
1e453df9 29#define SMSTPCR4 0xe6150140
c91cf2fa 30#define SMSTPCR5 0xe6150144
eccf0607 31
b89edf34
KM		 32#define FRQCRA 0xE6150000
33#define FRQCRB 0xE6150004
181135e0 34#define FRQCRC 0xE61500E0
9051e912
KM		 35#define VCLKCR1 0xE6150008
36#define VCLKCR2 0xE615000C
37#define VCLKCR3 0xE615001C
38#define VCLKCR4 0xE6150014
39#define VCLKCR5 0xE6150034
40#define ZBCKCR 0xE6150010
41#define SD0CKCR 0xE6150074
42#define SD1CKCR 0xE6150078
43#define SD2CKCR 0xE615007C
44#define MMC0CKCR 0xE6150240
45#define MMC1CKCR 0xE6150244
46#define FSIACKCR 0xE6150018
47#define FSIBCKCR 0xE6150090
48#define MPCKCR 0xe6150080
49#define SPUVCKCR 0xE6150094
50#define HSICKCR 0xE615026C
51#define M4CKCR 0xE6150098
0c3091ad 52#define PLLECR 0xE61500D0
181135e0 53#define PLL0CR 0xE61500D8
0c3091ad
KM		 54#define PLL1CR 0xE6150028
55#define PLL2CR 0xE615002C
56#define PLL2SCR 0xE61501F4
57#define PLL2HCR 0xE61501E4
9051e912 58#define CKSCR 0xE61500C0
0c3091ad
KM		 59
60#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
5e634d98 61
eccf0607
MD		 62static struct clk_mapping cpg_mapping = {
63 .phys = CPG_BASE,
64 .len = CPG_LEN,
65};
66
67static struct clk extalr_clk = {
68 .rate = 32768,
69 .mapping = &cpg_mapping,
70};
71
72static struct clk extal1_clk = {
73 .rate = 26000000,
74 .mapping = &cpg_mapping,
75};
76
77static struct clk extal2_clk = {
78 .rate = 48000000,
79 .mapping = &cpg_mapping,
80};
81
5e634d98
KM		 82static struct sh_clk_ops followparent_clk_ops = {
83 .recalc = followparent_recalc,
84};
85
86static struct clk main_clk = {
87 /* .parent will be set r8a73a4_clock_init */
88 .ops = &followparent_clk_ops,
89};
90
91SH_CLK_RATIO(div2, 1, 2);
92SH_CLK_RATIO(div4, 1, 4);
93
94SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
95SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
96SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
97SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4);
98
9051e912
KM		 99/* External FSIACK/FSIBCK clock */
100static struct clk fsiack_clk = {
101};
102
103static struct clk fsibck_clk = {
104};
105
0c3091ad
KM		 106/*
107 * PLL clocks
108 */
109static struct clk *pll_parent_main[] = {
110 [0] = &main_clk,
111 [1] = &main_div2_clk
112};
113
114static struct clk *pll_parent_main_extal[8] = {
115 [0] = &main_div2_clk,
116 [1] = &extal2_div2_clk,
117 [3] = &extal2_div4_clk,
118 [4] = &main_clk,
119 [5] = &extal2_clk,
120};
121
122static unsigned long pll_recalc(struct clk *clk)
123{
124 unsigned long mult = 1;
125
126 if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
127 mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
128
129 return clk->parent->rate * mult;
130}
131
132static int pll_set_parent(struct clk *clk, struct clk *parent)
133{
134 u32 val;
135 int i, ret;
136
137 if (!clk->parent_table || !clk->parent_num)
138 return -EINVAL;
139
140 /* Search the parent */
141 for (i = 0; i < clk->parent_num; i++)
142 if (clk->parent_table[i] == parent)
143 break;
144
145 if (i == clk->parent_num)
146 return -ENODEV;
147
148 ret = clk_reparent(clk, parent);
149 if (ret < 0)
150 return ret;
151
152 val = ioread32(clk->mapped_reg) &
153 ~(((1 << clk->src_width) - 1) << clk->src_shift);
154
155 iowrite32(val | i << clk->src_shift, clk->mapped_reg);
156
157 return 0;
158}
159
160static struct sh_clk_ops pll_clk_ops = {
161 .recalc = pll_recalc,
162 .set_parent = pll_set_parent,
163};
164
165#define PLL_CLOCK(name, p, pt, w, s, reg, e) \
166 static struct clk name = { \
167 .ops = &pll_clk_ops, \
168 .flags = CLK_ENABLE_ON_INIT, \
169 .parent = p, \
170 .parent_table = pt, \
171 .parent_num = ARRAY_SIZE(pt), \
172 .src_width = w, \
173 .src_shift = s, \
174 .enable_reg = (void __iomem *)reg, \
175 .enable_bit = e, \
176 .mapping = &cpg_mapping, \
177 }
178
181135e0 179PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0);
0c3091ad
KM		 180PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
181PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2);
182PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
183PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
184
185SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
186
181135e0
GL		 187static atomic_t frqcr_lock;
188
189/* Several clocks need to access FRQCRB, have to lock */
190static bool frqcr_kick_check(struct clk *clk)
191{
192 return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
193}
194
8d276572
GL		 195static int frqcr_kick_do(struct clk *clk)
196{
197 int i;
198
199 /* set KICK bit in FRQCRB to update hardware setting, check success */
200 iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
201 for (i = 1000; i; i--)
202 if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
203 cpu_relax();
204 else
205 return 0;
206
207 return -ETIMEDOUT;
208}
209
181135e0
GL		 210static int zclk_set_rate(struct clk *clk, unsigned long rate)
211{
212 void __iomem *frqcrc;
213 int ret;
214 unsigned long step, p_rate;
215 u32 val;
216
217 if (!clk->parent || !__clk_get(clk->parent))
218 return -ENODEV;
219
220 if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
221 ret = -EBUSY;
222 goto done;
223 }
224
d1c3c959
GL		 225 /*
226 * Users are supposed to first call clk_set_rate() only with
227 * clk_round_rate() results. So, we don't fix wrong rates here, but
228 * guard against them anyway
229 */
181135e0
GL		 230
231 p_rate = clk_get_rate(clk->parent);
232 if (rate == p_rate) {
233 val = 0;
234 } else {
235 step = DIV_ROUND_CLOSEST(p_rate, 32);
d1c3c959
GL		 236
237 if (rate > p_rate || rate < step) {
238 ret = -EINVAL;
239 goto done;
240 }
241
181135e0
GL		 242 val = 32 - rate / step;
243 }
244
d1c3c959
GL		 245 frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
246
181135e0
GL		 247 iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
248 (val << clk->enable_bit), frqcrc);
249
250 ret = frqcr_kick_do(clk);
251
252done:
253 atomic_dec(&frqcr_lock);
254 __clk_put(clk->parent);
255 return ret;
256}
257
258static long zclk_round_rate(struct clk *clk, unsigned long rate)
259{
260 /*
261 * theoretical rate = parent rate * multiplier / 32,
262 * where 1 <= multiplier <= 32. Therefore we should do
263 * multiplier = rate * 32 / parent rate
264 * rounded rate = parent rate * multiplier / 32.
265 * However, multiplication before division won't fit in 32 bits, so
266 * we sacrifice some precision by first dividing and then multiplying.
267 * To find the nearest divisor we calculate both and pick up the best
268 * one. This avoids 64-bit arithmetics.
269 */
270 unsigned long step, mul_min, mul_max, rate_min, rate_max;
271
272 rate_max = clk_get_rate(clk->parent);
273
274 /* output freq <= parent */
275 if (rate >= rate_max)
276 return rate_max;
277
278 step = DIV_ROUND_CLOSEST(rate_max, 32);
279 /* output freq >= parent / 32 */
280 if (step >= rate)
281 return step;
282
283 mul_min = rate / step;
284 mul_max = DIV_ROUND_UP(rate, step);
285 rate_min = step * mul_min;
286 if (mul_max == mul_min)
287 return rate_min;
288
289 rate_max = step * mul_max;
290
291 if (rate_max - rate < rate - rate_min)
292 return rate_max;
293
294 return rate_min;
295}
296
297static unsigned long zclk_recalc(struct clk *clk)
298{
299 void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
300 unsigned int max = clk->div_mask + 1;
301 unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
302 clk->div_mask);
303
304 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
305 (max - val);
306}
307
308static struct sh_clk_ops zclk_ops = {
309 .recalc = zclk_recalc,
310 .set_rate = zclk_set_rate,
311 .round_rate = zclk_round_rate,
312};
313
314static struct clk z_clk = {
315 .parent = &pll0_clk,
316 .div_mask = 0x1f,
317 .enable_bit = 8,
318 /* We'll need to access FRQCRB and FRQCRC */
319 .enable_reg = (void __iomem *)FRQCRB,
320 .ops = &zclk_ops,
321};
322
a040f22d
GL		 323/*
324 * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
325 * switching is only available in auto-DVFS mode
326 */
327SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
328
329static struct clk z2_clk = {
330 .parent = &pll0_div2_clk,
331 .div_mask = 0x1f,
332 .enable_bit = 0,
333 /* We'll need to access FRQCRB and FRQCRC */
334 .enable_reg = (void __iomem *)FRQCRB,
335 .ops = &zclk_ops,
336};
337
eccf0607
MD		 338static struct clk *main_clks[] = {
339 &extalr_clk,
340 &extal1_clk,
5e634d98 341 &extal1_div2_clk,
eccf0607 342 &extal2_clk,
5e634d98
KM		 343 &extal2_div2_clk,
344 &extal2_div4_clk,
345 &main_clk,
346 &main_div2_clk,
9051e912
KM		 347 &fsiack_clk,
348 &fsibck_clk,
181135e0 349 &pll0_clk,
0c3091ad
KM		 350 &pll1_clk,
351 &pll1_div2_clk,
352 &pll2_clk,
353 &pll2s_clk,
354 &pll2h_clk,
181135e0 355 &z_clk,
a040f22d
GL		 356 &pll0_div2_clk,
357 &z2_clk,
eccf0607
MD		 358};
359
b89edf34
KM		 360/* DIV4 */
361static void div4_kick(struct clk *clk)
362{
181135e0
GL		 363 if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
364 frqcr_kick_do(clk);
365 atomic_dec(&frqcr_lock);
b89edf34
KM		 366}
367
368static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
369
370static struct clk_div_mult_table div4_div_mult_table = {
371 .divisors = divisors,
372 .nr_divisors = ARRAY_SIZE(divisors),
373};
374
375static struct clk_div4_table div4_table = {
376 .div_mult_table = &div4_div_mult_table,
377 .kick = div4_kick,
378};
379
380enum {
381 DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
382 DIV4_ZX, DIV4_ZS, DIV4_HP,
383 DIV4_NR };
384
385static struct clk div4_clks[DIV4_NR] = {
386 [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
387 [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
388 [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT),
389 [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0),
390 [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0),
391 [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
392 [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0),
393 [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0),
394};
395
9051e912
KM		 396enum {
397 DIV6_ZB,
398 DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
399 DIV6_MMC0, DIV6_MMC1,
400 DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
401 DIV6_FSIA, DIV6_FSIB,
402 DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
403 DIV6_NR };
404
405static struct clk *div6_parents[8] = {
406 [0] = &pll1_div2_clk,
407 [1] = &pll2s_clk,
408 [3] = &extal2_clk,
409 [4] = &main_div2_clk,
410 [6] = &extalr_clk,
411};
412
413static struct clk *fsia_parents[4] = {
414 [0] = &pll1_div2_clk,
415 [1] = &pll2s_clk,
416 [2] = &fsiack_clk,
417};
418
419static struct clk *fsib_parents[4] = {
420 [0] = &pll1_div2_clk,
421 [1] = &pll2s_clk,
422 [2] = &fsibck_clk,
423};
424
425static struct clk *mp_parents[4] = {
426 [0] = &pll1_div2_clk,
427 [1] = &pll2s_clk,
428 [2] = &extal2_clk,
429 [3] = &extal2_clk,
430};
431
432static struct clk *m4_parents[2] = {
433 [0] = &pll2s_clk,
434};
435
436static struct clk *hsi_parents[4] = {
437 [0] = &pll2h_clk,
438 [1] = &pll1_div2_clk,
439 [3] = &pll2s_clk,
440};
441
442/*** FIXME ***
443 * SH_CLK_DIV6_EXT() macro doesn't care .mapping
444 * but, it is necessary on R-Car (= ioremap() base CPG)
445 * The difference between
446 * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
447 * is only .mapping
448 */
449#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \
450 _num_parents, _src_shift, _src_width) \
451{ \
452 .enable_reg = (void __iomem *)_reg, \
453 .enable_bit = 0, /* unused */ \
454 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
455 .div_mask = SH_CLK_DIV6_MSK, \
456 .parent_table = _parents, \
457 .parent_num = _num_parents, \
458 .src_shift = _src_shift, \
459 .src_width = _src_width, \
460 .mapping = &cpg_mapping, \
461}
462
463static struct clk div6_clks[DIV6_NR] = {
464 [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
465 div6_parents, 2, 7, 1),
466 [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
467 div6_parents, 2, 6, 2),
468 [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
469 div6_parents, 2, 6, 2),
470 [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
471 div6_parents, 2, 6, 2),
472 [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
473 div6_parents, 2, 6, 2),
474 [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
475 div6_parents, 2, 6, 2),
476 [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
477 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
478 [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
479 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
480 [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
481 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
482 [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
483 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
484 [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
485 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
486 [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
487 fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
488 [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
489 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
490 [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
491 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
492 /* pll2s will be selected always for M4 */
493 [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
494 m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
495 [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
496 hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
497 [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
498 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
499};
500
b89edf34 501/* MSTP */
c91cf2fa 502enum {
9f754b4a 503 MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
a7b99f27 504 MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
1e453df9
GL		 505 MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
506 MSTP411, MSTP410, MSTP409,
507 MSTP522, MSTP515,
c91cf2fa
KM		 508 MSTP_NR
509};
510
eccf0607 511static struct clk mstp_clks[MSTP_NR] = {
9051e912
KM		 512 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */
513 [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */
514 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */
515 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
516 [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
517 [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
9f754b4a 518 [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */
1e453df9 519 [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
111fad56
GL		 520 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
521 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
522 [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
523 [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
524 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
1e453df9
GL		 525 [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0), /* IIC6 */
526 [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */
527 [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */
528 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
a7b99f27 529 [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
1e453df9
GL		 530 [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */
531 [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
532 [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
c91cf2fa 533 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
1e453df9 534 [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0), /* IIC8 */
eccf0607
MD		 535};
536
537static struct clk_lookup lookups[] = {
5e634d98
KM		 538 /* main clock */
539 CLKDEV_CON_ID("extal1", &extal1_clk),
540 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
541 CLKDEV_CON_ID("extal2", &extal2_clk),
542 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
543 CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk),
9051e912
KM		 544 CLKDEV_CON_ID("fsiack", &fsiack_clk),
545 CLKDEV_CON_ID("fsibck", &fsibck_clk),
5e634d98 546
0c3091ad
KM		 547 /* pll clock */
548 CLKDEV_CON_ID("pll1", &pll1_clk),
549 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
550 CLKDEV_CON_ID("pll2", &pll2_clk),
551 CLKDEV_CON_ID("pll2s", &pll2s_clk),
552 CLKDEV_CON_ID("pll2h", &pll2h_clk),
553
181135e0 554 /* CPU clock */
e4a6a29d 555 CLKDEV_DEV_ID("cpu0", &z_clk),
181135e0 556
9051e912
KM		 557 /* DIV6 */
558 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
9051e912
KM		 559 CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]),
560 CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]),
561 CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]),
562 CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]),
563 CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]),
564 CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]),
565 CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]),
566 CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]),
567 CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]),
568 CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]),
569 CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]),
570
0c3091ad 571 /* MSTP */
e481a528 572 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
9947efaa 573 CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]),
e481a528 574 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
9947efaa 575 CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]),
e481a528 576 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
9947efaa 577 CLKDEV_DEV_ID("e6c20000.serial", &mstp_clks[MSTP206]),
e481a528 578 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
9947efaa 579 CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP207]),
e481a528 580 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
9947efaa 581 CLKDEV_DEV_ID("e6ce0000.serial", &mstp_clks[MSTP216]),
e481a528 582 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
9947efaa 583 CLKDEV_DEV_ID("e6cf0000.serial", &mstp_clks[MSTP217]),
9f754b4a 584 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
b9b28f52 585 CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
c91cf2fa 586 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
1e453df9 587 CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
111fad56 588 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
43304a5f 589 CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
111fad56 590 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
43304a5f 591 CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
111fad56 592 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
43304a5f 593 CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
111fad56 594 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
43304a5f 595 CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
111fad56 596 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
43304a5f 597 CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
1e453df9
GL		 598 CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
599 CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
600 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
601 CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
52065ef7 602 CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.1", &mstp_clks[MSTP329]),
aad64dc3 603 CLKDEV_ICK_ID("fck", "e6130000.timer", &mstp_clks[MSTP329]),
1e453df9
GL		 604 CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
605 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
606 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
607 CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
c91cf2fa
KM		 608
609 /* for DT */
610 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
eccf0607
MD		 611};
612
613void __init r8a73a4_clock_init(void)
614{
9051e912 615 void __iomem *reg;
eccf0607 616 int k, ret = 0;
5e634d98 617 u32 ckscr;
eccf0607 618
181135e0
GL		 619 atomic_set(&frqcr_lock, -1);
620
5e634d98
KM		 621 reg = ioremap_nocache(CKSCR, PAGE_SIZE);
622 BUG_ON(!reg);
623 ckscr = ioread32(reg);
624 iounmap(reg);
625
626 switch ((ckscr >> 28) & 0x3) {
627 case 0:
628 main_clk.parent = &extal1_clk;
629 break;
630 case 1:
631 main_clk.parent = &extal1_div2_clk;
632 break;
633 case 2:
634 main_clk.parent = &extal2_clk;
635 break;
636 case 3:
637 main_clk.parent = &extal2_div2_clk;
638 break;
639 }
640
eccf0607
MD		 641 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
642 ret = clk_register(main_clks[k]);
643
b89edf34
KM		 644 if (!ret)
645 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
646
9051e912
KM		 647 if (!ret)
648 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
649
eccf0607
MD		 650 if (!ret)
651 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
652
653 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
654
655 if (!ret)
656 shmobile_clk_init();
657 else
658 panic("failed to setup r8a73a4 clocks\n");
659}
Linux kernel - Deliverables
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