[deliverable/linux.git] / arch / arm / mach-shmobile / clock-r8a7790.c

/*
 * r8a7790 clock framework support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <mach/clock.h>
#include <mach/common.h>

/*
 *   MD		EXTAL		PLL0	PLL1	PLL3
 * 14 13 19	(MHz)		*1	*1
 *---------------------------------------------------
 * 0  0  0	15 x 1		x172/2	x208/2	x106
 * 0  0  1	15 x 1		x172/2	x208/2	x88
 * 0  1  0	20 x 1		x130/2	x156/2	x80
 * 0  1  1	20 x 1		x130/2	x156/2	x66
 * 1  0  0	26 / 2		x200/2	x240/2	x122
 * 1  0  1	26 / 2		x200/2	x240/2	x102
 * 1  1  0	30 / 2		x172/2	x208/2	x106
 * 1  1  1	30 / 2		x172/2	x208/2	x88
 *
 * *1 :	Table 7.6 indicates VCO ouput (PLLx = VCO/2)
 *	see "p1 / 2" on R8A7790_CLOCK_ROOT() below
 */

#define MD(nr)	(1 << nr)

#define CPG_BASE 0xe6150000
#define CPG_LEN 0x1000

#define SMSTPCR2 0xe6150138
#define SMSTPCR7 0xe615014c

#define MODEMR		0xE6160060
#define SDCKCR		0xE6150074
#define SD2CKCR		0xE6150078
#define SD3CKCR		0xE615007C
#define MMC0CKCR	0xE6150240
#define MMC1CKCR	0xE6150244
#define SSPCKCR		0xE6150248
#define SSPRSCKCR	0xE615024C

static struct clk_mapping cpg_mapping = {
	.phys   = CPG_BASE,
	.len    = CPG_LEN,
};

static struct clk extal_clk = {
	/* .rate will be updated on r8a7790_clock_init() */
	.mapping	= &cpg_mapping,
};

static struct sh_clk_ops followparent_clk_ops = {
	.recalc	= followparent_recalc,
};

static struct clk main_clk = {
	/* .parent will be set r8a73a4_clock_init */
	.ops	= &followparent_clk_ops,
};

/*
 * clock ratio of these clock will be updated
 * on r8a7790_clock_init()
 */
SH_FIXED_RATIO_CLK_SET(pll1_clk,		main_clk,	1, 1);
SH_FIXED_RATIO_CLK_SET(pll3_clk,		main_clk,	1, 1);
SH_FIXED_RATIO_CLK_SET(lb_clk,			pll1_clk,	1, 1);
SH_FIXED_RATIO_CLK_SET(qspi_clk,		pll1_clk,	1, 1);

/* fixed ratio clock */
SH_FIXED_RATIO_CLK_SET(extal_div2_clk,		extal_clk,	1, 2);
SH_FIXED_RATIO_CLK_SET(cp_clk,			extal_clk,	1, 2);

SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,		pll1_clk,	1, 2);
SH_FIXED_RATIO_CLK_SET(zg_clk,			pll1_clk,	1, 3);
SH_FIXED_RATIO_CLK_SET(zx_clk,			pll1_clk,	1, 3);
SH_FIXED_RATIO_CLK_SET(zs_clk,			pll1_clk,	1, 6);
SH_FIXED_RATIO_CLK_SET(hp_clk,			pll1_clk,	1, 12);
SH_FIXED_RATIO_CLK_SET(i_clk,			pll1_clk,	1, 2);
SH_FIXED_RATIO_CLK_SET(b_clk,			pll1_clk,	1, 12);
SH_FIXED_RATIO_CLK_SET(p_clk,			pll1_clk,	1, 24);
SH_FIXED_RATIO_CLK_SET(cl_clk,			pll1_clk,	1, 48);
SH_FIXED_RATIO_CLK_SET(m2_clk,			pll1_clk,	1, 8);
SH_FIXED_RATIO_CLK_SET(imp_clk,			pll1_clk,	1, 4);
SH_FIXED_RATIO_CLK_SET(rclk_clk,		pll1_clk,	1, (48 * 1024));
SH_FIXED_RATIO_CLK_SET(oscclk_clk,		pll1_clk,	1, (12 * 1024));

SH_FIXED_RATIO_CLK_SET(zb3_clk,			pll3_clk,	1, 4);
SH_FIXED_RATIO_CLK_SET(zb3d2_clk,		pll3_clk,	1, 8);
SH_FIXED_RATIO_CLK_SET(ddr_clk,			pll3_clk,	1, 8);
SH_FIXED_RATIO_CLK_SET(mp_clk,			pll1_div2_clk,	1, 15);

static struct clk *main_clks[] = {
	&extal_clk,
	&extal_div2_clk,
	&main_clk,
	&pll1_clk,
	&pll1_div2_clk,
	&pll3_clk,
	&lb_clk,
	&qspi_clk,
	&zg_clk,
	&zx_clk,
	&zs_clk,
	&hp_clk,
	&i_clk,
	&b_clk,
	&p_clk,
	&cl_clk,
	&m2_clk,
	&imp_clk,
	&rclk_clk,
	&oscclk_clk,
	&zb3_clk,
	&zb3d2_clk,
	&ddr_clk,
	&mp_clk,
	&cp_clk,
};

/* SDHI (DIV4) clock */
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum {
	DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
};

struct clk div4_clks[DIV4_NR] = {
	[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
	[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
};

/* DIV6 clocks */
enum {
	DIV6_SD2, DIV6_SD3,
	DIV6_MMC0, DIV6_MMC1,
	DIV6_SSP, DIV6_SSPRS,
	DIV6_NR
};

static struct clk div6_clks[DIV6_NR] = {
	[DIV6_SD2]	= SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
	[DIV6_SD3]	= SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
	[DIV6_MMC0]	= SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
	[DIV6_MMC1]	= SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
	[DIV6_SSP]	= SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
	[DIV6_SSPRS]	= SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
};

/* MSTP */
enum { MSTP721, MSTP720,
	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
	[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
	[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
	[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
	[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
	[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
	[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
};

static struct clk_lookup lookups[] = {

	/* main clocks */
	CLKDEV_CON_ID("extal",		&extal_clk),
	CLKDEV_CON_ID("extal_div2",	&extal_div2_clk),
	CLKDEV_CON_ID("main",		&main_clk),
	CLKDEV_CON_ID("pll1",		&pll1_clk),
	CLKDEV_CON_ID("pll1_div2",	&pll1_div2_clk),
	CLKDEV_CON_ID("pll3",		&pll3_clk),
	CLKDEV_CON_ID("zg",		&zg_clk),
	CLKDEV_CON_ID("zx",		&zx_clk),
	CLKDEV_CON_ID("zs",		&zs_clk),
	CLKDEV_CON_ID("hp",		&hp_clk),
	CLKDEV_CON_ID("i",		&i_clk),
	CLKDEV_CON_ID("b",		&b_clk),
	CLKDEV_CON_ID("lb",		&lb_clk),
	CLKDEV_CON_ID("p",		&p_clk),
	CLKDEV_CON_ID("cl",		&cl_clk),
	CLKDEV_CON_ID("m2",		&m2_clk),
	CLKDEV_CON_ID("imp",		&imp_clk),
	CLKDEV_CON_ID("rclk",		&rclk_clk),
	CLKDEV_CON_ID("oscclk",		&oscclk_clk),
	CLKDEV_CON_ID("zb3",		&zb3_clk),
	CLKDEV_CON_ID("zb3d2",		&zb3d2_clk),
	CLKDEV_CON_ID("ddr",		&ddr_clk),
	CLKDEV_CON_ID("mp",		&mp_clk),
	CLKDEV_CON_ID("qspi",		&qspi_clk),
	CLKDEV_CON_ID("cp",		&cp_clk),

	/* DIV4 */
	CLKDEV_CON_ID("sdh",		&div4_clks[DIV4_SDH]),
	CLKDEV_CON_ID("sd0",		&div4_clks[DIV4_SD0]),
	CLKDEV_CON_ID("sd1",		&div4_clks[DIV4_SD1]),

	/* DIV6 */
	CLKDEV_CON_ID("sd2",		&div6_clks[DIV6_SD2]),
	CLKDEV_CON_ID("sd3",		&div6_clks[DIV6_SD3]),
	CLKDEV_CON_ID("mmc0",		&div6_clks[DIV6_MMC0]),
	CLKDEV_CON_ID("mmc1",		&div6_clks[DIV6_MMC1]),
	CLKDEV_CON_ID("ssp",		&div6_clks[DIV6_SSP]),
	CLKDEV_CON_ID("ssprs",		&div6_clks[DIV6_SSPRS]),

	/* MSTP */
	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
};

#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
	extal_clk.rate	= e * 1000 * 1000;			\
	main_clk.parent	= m;					\
	SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);		\
	if (mode & MD(19))					\
		SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);	\
	else							\
		SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)


void __init r8a7790_clock_init(void)
{
	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
	u32 mode;
	int k, ret = 0;

	BUG_ON(!modemr);
	mode = ioread32(modemr);
	iounmap(modemr);

	switch (mode & (MD(14) | MD(13))) {
	case 0:
		R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
		break;
	case MD(13):
		R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
		break;
	case MD(14):
		R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
		break;
	case MD(13) | MD(14):
		R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
		break;
	}

	if (mode & (MD(18)))
		SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
	else
		SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);

	if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
	else
		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		shmobile_clk_init();
	else
		panic("failed to setup r8a7790 clocks\n");
}
Commit	Line	Data
0468b2d6 MD	1	/*
	2	* r8a7790 clock framework support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20	#include <linux/init.h>
	21	#include <linux/io.h>
	22	#include <linux/kernel.h>
	23	#include <linux/sh_clk.h>
	24	#include <linux/clkdev.h>
8d100c04	25	#include <mach/clock.h>
0468b2d6 MD	26	#include <mach/common.h>
0468b2d6 MD	27
8d100c04 KM	28	/*
	29	* MD EXTAL PLL0 PLL1 PLL3
	30	* 14 13 19 (MHz) 1 1
	31	*---------------------------------------------------
	32	* 0 0 0 15 x 1 x172/2 x208/2 x106
	33	* 0 0 1 15 x 1 x172/2 x208/2 x88
	34	* 0 1 0 20 x 1 x130/2 x156/2 x80
	35	* 0 1 1 20 x 1 x130/2 x156/2 x66
	36	* 1 0 0 26 / 2 x200/2 x240/2 x122
	37	* 1 0 1 26 / 2 x200/2 x240/2 x102
	38	* 1 1 0 30 / 2 x172/2 x208/2 x106
	39	* 1 1 1 30 / 2 x172/2 x208/2 x88
	40	*
	41	* *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
	42	* see "p1 / 2" on R8A7790_CLOCK_ROOT() below
	43	*/
	44
	45	#define MD(nr) (1 << nr)
	46
0468b2d6 MD	47	#define CPG_BASE 0xe6150000
	48	#define CPG_LEN 0x1000
	49
55d9fab2 MD	50	#define SMSTPCR2 0xe6150138
	51	#define SMSTPCR7 0xe615014c
	52
8d100c04	53	#define MODEMR 0xE6160060
9f13ee6f	54	#define SDCKCR 0xE6150074
46632512 KM	55	#define SD2CKCR 0xE6150078
	56	#define SD3CKCR 0xE615007C
	57	#define MMC0CKCR 0xE6150240
	58	#define MMC1CKCR 0xE6150244
	59	#define SSPCKCR 0xE6150248
	60	#define SSPRSCKCR 0xE615024C
8d100c04	61
0468b2d6 MD	62	static struct clk_mapping cpg_mapping = {
	63	.phys = CPG_BASE,
	64	.len = CPG_LEN,
	65	};
	66
8d100c04 KM	67	static struct clk extal_clk = {
8d100c04 KM	68	/* .rate will be updated on r8a7790_clock_init() */
55d9fab2 MD	69	.mapping = &cpg_mapping,
	70	};
	71
8d100c04 KM	72	static struct sh_clk_ops followparent_clk_ops = {
8d100c04 KM	73	.recalc = followparent_recalc,
55d9fab2 MD	74	};
55d9fab2 MD	75
8d100c04 KM	76	static struct clk main_clk = {
	77	/* .parent will be set r8a73a4_clock_init */
	78	.ops = &followparent_clk_ops,
	79	};
	80
	81	/*
	82	* clock ratio of these clock will be updated
	83	* on r8a7790_clock_init()
	84	*/
	85	SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
	86	SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
	87	SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
	88	SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
	89
	90	/* fixed ratio clock */
	91	SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
	92	SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
	93
	94	SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
	95	SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
	96	SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
	97	SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
	98	SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
	99	SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
	100	SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
	101	SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
	102	SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
	103	SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
	104	SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
	105	SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
	106	SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
	107
	108	SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
	109	SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
	110	SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
	111	SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
	112
0468b2d6	113	static struct clk *main_clks[] = {
8d100c04 KM	114	&extal_clk,
	115	&extal_div2_clk,
	116	&main_clk,
	117	&pll1_clk,
	118	&pll1_div2_clk,
	119	&pll3_clk,
	120	&lb_clk,
	121	&qspi_clk,
	122	&zg_clk,
	123	&zx_clk,
	124	&zs_clk,
	125	&hp_clk,
	126	&i_clk,
	127	&b_clk,
55d9fab2	128	&p_clk,
8d100c04 KM	129	&cl_clk,
	130	&m2_clk,
	131	&imp_clk,
	132	&rclk_clk,
	133	&oscclk_clk,
	134	&zb3_clk,
	135	&zb3d2_clk,
	136	&ddr_clk,
55d9fab2	137	&mp_clk,
8d100c04	138	&cp_clk,
0468b2d6 MD	139	};
0468b2d6 MD	140
9f13ee6f KM	141	/* SDHI (DIV4) clock */
	142	static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
	143
	144	static struct clk_div_mult_table div4_div_mult_table = {
	145	.divisors = divisors,
	146	.nr_divisors = ARRAY_SIZE(divisors),
	147	};
	148
	149	static struct clk_div4_table div4_table = {
	150	.div_mult_table = &div4_div_mult_table,
	151	};
	152
	153	enum {
	154	DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
	155	};
	156
	157	struct clk div4_clks[DIV4_NR] = {
	158	[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
	159	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
	160	[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
	161	};
	162
46632512 KM	163	/* DIV6 clocks */
	164	enum {
	165	DIV6_SD2, DIV6_SD3,
	166	DIV6_MMC0, DIV6_MMC1,
	167	DIV6_SSP, DIV6_SSPRS,
	168	DIV6_NR
	169	};
	170
	171	static struct clk div6_clks[DIV6_NR] = {
	172	[DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
	173	[DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
	174	[DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
	175	[DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
	176	[DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
	177	[DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
	178	};
	179
9f13ee6f	180	/* MSTP */
55d9fab2 MD	181	enum { MSTP721, MSTP720,
55d9fab2 MD	182	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
0468b2d6	183	static struct clk mstp_clks[MSTP_NR] = {
55d9fab2 MD	184	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
	185	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
	186	[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
	187	[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
	188	[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
	189	[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
	190	[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
	191	[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
0468b2d6 MD	192	};
	193
	194	static struct clk_lookup lookups[] = {
8d100c04 KM	195
	196	/* main clocks */
	197	CLKDEV_CON_ID("extal", &extal_clk),
	198	CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
	199	CLKDEV_CON_ID("main", &main_clk),
	200	CLKDEV_CON_ID("pll1", &pll1_clk),
	201	CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
	202	CLKDEV_CON_ID("pll3", &pll3_clk),
	203	CLKDEV_CON_ID("zg", &zg_clk),
	204	CLKDEV_CON_ID("zx", &zx_clk),
	205	CLKDEV_CON_ID("zs", &zs_clk),
	206	CLKDEV_CON_ID("hp", &hp_clk),
	207	CLKDEV_CON_ID("i", &i_clk),
	208	CLKDEV_CON_ID("b", &b_clk),
	209	CLKDEV_CON_ID("lb", &lb_clk),
	210	CLKDEV_CON_ID("p", &p_clk),
	211	CLKDEV_CON_ID("cl", &cl_clk),
	212	CLKDEV_CON_ID("m2", &m2_clk),
	213	CLKDEV_CON_ID("imp", &imp_clk),
	214	CLKDEV_CON_ID("rclk", &rclk_clk),
	215	CLKDEV_CON_ID("oscclk", &oscclk_clk),
	216	CLKDEV_CON_ID("zb3", &zb3_clk),
	217	CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
	218	CLKDEV_CON_ID("ddr", &ddr_clk),
	219	CLKDEV_CON_ID("mp", &mp_clk),
	220	CLKDEV_CON_ID("qspi", &qspi_clk),
	221	CLKDEV_CON_ID("cp", &cp_clk),
	222
9f13ee6f KM	223	/* DIV4 */
	224	CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
	225	CLKDEV_CON_ID("sd0", &div4_clks[DIV4_SD0]),
	226	CLKDEV_CON_ID("sd1", &div4_clks[DIV4_SD1]),
	227
46632512 KM	228	/* DIV6 */
	229	CLKDEV_CON_ID("sd2", &div6_clks[DIV6_SD2]),
	230	CLKDEV_CON_ID("sd3", &div6_clks[DIV6_SD3]),
	231	CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]),
	232	CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]),
	233	CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
	234	CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
	235
8d100c04	236	/* MSTP */
55d9fab2 MD	237	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
	238	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
	239	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
	240	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
	241	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
	242	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
	243	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
	244	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
0468b2d6 MD	245	};
0468b2d6 MD	246
8d100c04 KM	247	#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
	248	extal_clk.rate = e * 1000 * 1000; \
	249	main_clk.parent = m; \
	250	SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
	251	if (mode & MD(19)) \
	252	SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
	253	else \
	254	SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
	255
	256
0468b2d6 MD	257	void __init r8a7790_clock_init(void)
0468b2d6 MD	258	{
8d100c04 KM	259	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
8d100c04 KM	260	u32 mode;
0468b2d6 MD	261	int k, ret = 0;
0468b2d6 MD	262
8d100c04 KM	263	BUG_ON(!modemr);
	264	mode = ioread32(modemr);
	265	iounmap(modemr);
	266
	267	switch (mode & (MD(14) \| MD(13))) {
	268	case 0:
	269	R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
	270	break;
	271	case MD(13):
	272	R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
	273	break;
	274	case MD(14):
	275	R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
	276	break;
	277	case MD(13) \| MD(14):
	278	R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
	279	break;
	280	}
	281
	282	if (mode & (MD(18)))
	283	SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
	284	else
	285	SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
	286
	287	if ((mode & (MD(3) \| MD(2) \| MD(1))) == MD(2))
	288	SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
	289	else
	290	SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
	291
0468b2d6 MD	292	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	293	ret = clk_register(main_clks[k]);
	294
9f13ee6f KM	295	if (!ret)
	296	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	297
46632512 KM	298	if (!ret)
	299	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
	300
0468b2d6 MD	301	if (!ret)
	302	ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
	303
	304	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
	305
	306	if (!ret)
	307	shmobile_clk_init();
	308	else
	309	panic("failed to setup r8a7790 clocks\n");
	310	}