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6d9598e2 MD |
1 | /* |
2 | * sh73a0 clock framework support | |
3 | * | |
4 | * Copyright (C) 2010 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | #include <linux/init.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/sh_clk.h> | |
23 | #include <mach/common.h> | |
24 | #include <asm/clkdev.h> | |
25 | ||
26 | #define SMSTPCR0 0xe6150130 | |
27 | #define SMSTPCR1 0xe6150134 | |
28 | #define SMSTPCR2 0xe6150138 | |
29 | #define SMSTPCR3 0xe615013c | |
30 | #define SMSTPCR4 0xe6150140 | |
31 | #define SMSTPCR5 0xe6150144 | |
32 | ||
33 | /* Fixed 32 KHz root clock from EXTALR pin */ | |
34 | static struct clk r_clk = { | |
35 | .rate = 32768, | |
36 | }; | |
37 | ||
38 | /* Temporarily fixed 48 MHz SUB clock */ | |
39 | static struct clk sub_clk = { | |
40 | .rate = 48000000, | |
41 | }; | |
42 | ||
b028f94b YT |
43 | /* Temporarily fixed 104 MHz HP clock */ |
44 | static struct clk hp_clk = { | |
45 | .rate = 104000000, | |
46 | }; | |
47 | ||
6d9598e2 MD |
48 | static struct clk *main_clks[] = { |
49 | &r_clk, | |
50 | &sub_clk, | |
b028f94b | 51 | &hp_clk, |
6d9598e2 MD |
52 | }; |
53 | ||
54 | enum { MSTP219, | |
b028f94b YT |
55 | MSTP001, MSTP116, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, |
56 | MSTP201, MSTP200, MSTP323, MSTP331, MSTP329, MSTP312, MSTP411, | |
57 | MSTP410, MSTP403, | |
6d9598e2 MD |
58 | MSTP_NR }; |
59 | ||
60 | #define MSTP(_parent, _reg, _bit, _flags) \ | |
61 | SH_CLK_MSTP32(_parent, _reg, _bit, _flags) | |
62 | ||
63 | static struct clk mstp_clks[MSTP_NR] = { | |
b028f94b | 64 | [MSTP001] = MSTP(&hp_clk, SMSTPCR0, 1, 0), /* I2C2 */ |
6d9598e2 | 65 | [MSTP219] = MSTP(&sub_clk, SMSTPCR2, 19, 0), /* SCIFA7 */ |
b028f94b | 66 | [MSTP116] = MSTP(&hp_clk, SMSTPCR1, 16, 0), /* I2C0 */ |
6d9598e2 MD |
67 | [MSTP207] = MSTP(&sub_clk, SMSTPCR2, 7, 0), /* SCIFA5 */ |
68 | [MSTP206] = MSTP(&sub_clk, SMSTPCR2, 6, 0), /* SCIFB */ | |
69 | [MSTP204] = MSTP(&sub_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ | |
70 | [MSTP203] = MSTP(&sub_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ | |
71 | [MSTP202] = MSTP(&sub_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ | |
72 | [MSTP201] = MSTP(&sub_clk, SMSTPCR2, 1, 0), /* SCIFA3 */ | |
73 | [MSTP200] = MSTP(&sub_clk, SMSTPCR2, 0, 0), /* SCIFA4 */ | |
74 | [MSTP331] = MSTP(&sub_clk, SMSTPCR3, 31, 0), /* SCIFA6 */ | |
75 | [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ | |
b028f94b | 76 | [MSTP323] = MSTP(&hp_clk, SMSTPCR3, 23, 0), /* I2C1 */ |
2d22d486 | 77 | [MSTP403] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* KEYSC0 */ |
b028f94b YT |
78 | [MSTP411] = MSTP(&hp_clk, SMSTPCR4, 11, 0), /* I2C3 */ |
79 | [MSTP410] = MSTP(&hp_clk, SMSTPCR4, 10, 0), /* I2C4 */ | |
6d9598e2 MD |
80 | }; |
81 | ||
82 | #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } | |
83 | ||
84 | static struct clk_lookup lookups[] = { | |
85 | /* MSTP32 clocks */ | |
86 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */ | |
87 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ | |
88 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ | |
89 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ | |
90 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ | |
91 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ | |
92 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ | |
93 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ | |
94 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ | |
95 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ | |
2d22d486 | 96 | CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC0 */ |
b028f94b YT |
97 | CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */ |
98 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ | |
99 | CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ | |
100 | CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */ | |
101 | CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ | |
6d9598e2 MD |
102 | }; |
103 | ||
104 | void __init sh73a0_clock_init(void) | |
105 | { | |
106 | int k, ret = 0; | |
107 | ||
108 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) | |
109 | ret = clk_register(main_clks[k]); | |
110 | ||
111 | if (!ret) | |
112 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); | |
113 | ||
114 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | |
115 | ||
116 | if (!ret) | |
117 | clk_init(); | |
118 | else | |
119 | panic("failed to setup sh73a0 clocks\n"); | |
120 | } |