[deliverable/linux.git] / arch / arm / mach-shmobile / headsmp-scu.S

/*
 * Shared SCU setup for mach-shmobile
 *
 * Copyright (C) 2012 Bastian Hecht
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/memory.h>

/*
 * Boot code for secondary CPUs.
 *
 * First we turn on L1 cache coherency for our CPU. Then we jump to
 * secondary_startup that invalidates the cache and hands over control
 * to the common ARM startup code.
 */
ENTRY(shmobile_boot_scu)
					@ r0 = SCU base address
	mrc     p15, 0, r1, c0, c0, 5	@ read MPIDR
	and	r1, r1, #3		@ mask out cpu ID
	lsl	r1, r1, #3		@ we will shift by cpu_id * 8 bits
	ldr	r2, [r0, #8]		@ SCU Power Status Register
	mov	r3, #3
	lsl	r3, r3, r1
	bic	r2, r2, r3		@ Clear bits of our CPU (Run Mode)
	str	r2, [r0, #8]		@ write back

	b	secondary_startup
ENDPROC(shmobile_boot_scu)
Commit	Line	Data
ec0d84a8 MD	1	/*
	2	* Shared SCU setup for mach-shmobile
	3	*
	4	* Copyright (C) 2012 Bastian Hecht
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	14	* GNU General Public License for more details.
ec0d84a8 MD	15	*/
	16
	17	#include <linux/linkage.h>
	18	#include <linux/init.h>
	19	#include <asm/memory.h>
	20
ec0d84a8	21	/*
4f6da36f	22	* Boot code for secondary CPUs.
ec0d84a8 MD	23	*
ec0d84a8 MD	24	* First we turn on L1 cache coherency for our CPU. Then we jump to
02b4e275	25	* secondary_startup that invalidates the cache and hands over control
ec0d84a8	26	* to the common ARM startup code.
ec0d84a8	27	*/
bfabbcc6 MD	28	ENTRY(shmobile_boot_scu)
bfabbcc6 MD	29	@ r0 = SCU base address
e24f317c	30	mrc p15, 0, r1, c0, c0, 5 @ read MPIDR
bfabbcc6 MD	31	and r1, r1, #3 @ mask out cpu ID
	32	lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
	33	ldr r2, [r0, #8] @ SCU Power Status Register
	34	mov r3, #3
bdea6c65 TK	35	lsl r3, r3, r1
bdea6c65 TK	36	bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
bfabbcc6 MD	37	str r2, [r0, #8] @ write back
bfabbcc6 MD	38
02b4e275	39	b secondary_startup
bfabbcc6	40	ENDPROC(shmobile_boot_scu)