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e4e430c6 MD |
1 | /* |
2 | * sh7372 processor support - INTC hardware block | |
3 | * | |
4 | * Copyright (C) 2010 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
18 | */ | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/sh_intc.h> | |
25 | #include <asm/mach-types.h> | |
26 | #include <asm/mach/arch.h> | |
27 | ||
28 | enum { | |
29 | UNUSED_INTCA = 0, | |
c57a31ab MD |
30 | ENABLED, |
31 | DISABLED, | |
e4e430c6 MD |
32 | |
33 | /* interrupt sources INTCA */ | |
34 | IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, | |
35 | IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A, | |
36 | IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A, | |
37 | IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A, | |
38 | DIRC, | |
39 | CRYPT_STD, | |
40 | IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, | |
41 | AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX, | |
42 | MFI_MFIM, MFI_MFIS, | |
43 | BBIF1, BBIF2, | |
deded435 | 44 | USBHSDMAC0_USHDMI, |
e4e430c6 MD |
45 | _3DG_SGX540, |
46 | CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3, | |
47 | KEYSC_KEY, | |
48 | SCIFA0, SCIFA1, SCIFA2, SCIFA3, | |
49 | MSIOF2, MSIOF1, | |
50 | SCIFA4, SCIFA5, SCIFB, | |
51 | FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, | |
c57a31ab MD |
52 | SDHI0, |
53 | SDHI1, | |
e4e430c6 MD |
54 | IRREM, |
55 | IRDA, | |
56 | TPU0, | |
57 | TTI20, | |
58 | DDM, | |
c57a31ab | 59 | SDHI2, |
e4e430c6 | 60 | RWDT0, |
deded435 KM |
61 | DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, |
62 | DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, | |
e4e430c6 MD |
63 | DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, |
64 | DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, | |
65 | DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, | |
66 | DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, | |
67 | SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, | |
68 | HDMI, | |
69 | SPU2_SPU0, SPU2_SPU1, | |
70 | FSI, FMSI, | |
71 | MIPI_HSI, | |
72 | IPMMU_IPMMUD, | |
deded435 | 73 | CEC_1, CEC_2, |
e4e430c6 MD |
74 | AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ, |
75 | MFIS2, | |
76 | CPORTR2S, | |
77 | CMT14, CMT15, | |
78 | MMC_MMC_ERR, MMC_MMC_NOR, | |
79 | IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4, | |
80 | IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3, | |
81 | USB0_USB0I1, USB0_USB0I0, | |
82 | USB1_USB1I1, USB1_USB1I0, | |
deded435 | 83 | USBHSDMAC1_USHDMI, |
e4e430c6 MD |
84 | |
85 | /* interrupt groups INTCA */ | |
deded435 | 86 | DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT, |
c57a31ab | 87 | AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1 |
e4e430c6 MD |
88 | }; |
89 | ||
deded435 | 90 | static struct intc_vect intca_vectors[] __initdata = { |
e4e430c6 MD |
91 | INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220), |
92 | INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260), | |
93 | INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0), | |
94 | INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0), | |
95 | INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320), | |
96 | INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360), | |
97 | INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0), | |
98 | INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0), | |
99 | INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220), | |
100 | INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260), | |
3f25cb04 | 101 | INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ21A, 0x32a0), |
e4e430c6 MD |
102 | INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0), |
103 | INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320), | |
104 | INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360), | |
105 | INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0), | |
106 | INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0), | |
107 | INTC_VECT(DIRC, 0x0560), | |
108 | INTC_VECT(CRYPT_STD, 0x0700), | |
109 | INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), | |
110 | INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0), | |
111 | INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840), | |
112 | INTC_VECT(AP_ARM_COMMRX, 0x0860), | |
113 | INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920), | |
114 | INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960), | |
deded435 | 115 | INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00), |
e4e430c6 MD |
116 | INTC_VECT(_3DG_SGX540, 0x0a60), |
117 | INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20), | |
118 | INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60), | |
119 | INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0), | |
120 | INTC_VECT(KEYSC_KEY, 0x0be0), | |
121 | INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20), | |
122 | INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60), | |
123 | INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00), | |
124 | INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40), | |
125 | INTC_VECT(SCIFB, 0x0d60), | |
126 | INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), | |
127 | INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), | |
c57a31ab MD |
128 | INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20), |
129 | INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60), | |
130 | INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0), | |
131 | INTC_VECT(SDHI1, 0x0ec0), | |
e4e430c6 MD |
132 | INTC_VECT(IRREM, 0x0f60), |
133 | INTC_VECT(IRDA, 0x0480), | |
134 | INTC_VECT(TPU0, 0x04a0), | |
135 | INTC_VECT(TTI20, 0x1100), | |
136 | INTC_VECT(DDM, 0x1140), | |
c57a31ab MD |
137 | INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220), |
138 | INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260), | |
e4e430c6 | 139 | INTC_VECT(RWDT0, 0x1280), |
deded435 KM |
140 | INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020), |
141 | INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060), | |
142 | INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0), | |
143 | INTC_VECT(DMAC1_2_DADERR, 0x20c0), | |
e4e430c6 MD |
144 | INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120), |
145 | INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160), | |
146 | INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0), | |
147 | INTC_VECT(DMAC2_2_DADERR, 0x21c0), | |
148 | INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220), | |
149 | INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260), | |
150 | INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0), | |
151 | INTC_VECT(DMAC3_2_DADERR, 0x22c0), | |
deded435 | 152 | INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320), |
e4e430c6 MD |
153 | INTC_VECT(SHWYSTAT_COM, 0x1340), |
154 | INTC_VECT(HDMI, 0x17e0), | |
155 | INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820), | |
156 | INTC_VECT(FSI, 0x1840), | |
157 | INTC_VECT(FMSI, 0x1860), | |
158 | INTC_VECT(MIPI_HSI, 0x18e0), | |
159 | INTC_VECT(IPMMU_IPMMUD, 0x1920), | |
deded435 | 160 | INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960), |
e4e430c6 MD |
161 | INTC_VECT(AP_ARM_CTIIRQ, 0x1980), |
162 | INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0), | |
163 | INTC_VECT(AP_ARM_DMAIRQ, 0x19c0), | |
164 | INTC_VECT(AP_ARM_DMASIRQ, 0x19e0), | |
165 | INTC_VECT(MFIS2, 0x1a00), | |
166 | INTC_VECT(CPORTR2S, 0x1a20), | |
167 | INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60), | |
168 | INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0), | |
169 | INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20), | |
170 | INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60), | |
171 | INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0), | |
172 | INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0), | |
173 | INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0), | |
174 | INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0), | |
deded435 | 175 | INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00), |
e4e430c6 MD |
176 | }; |
177 | ||
178 | static struct intc_group intca_groups[] __initdata = { | |
deded435 KM |
179 | INTC_GROUP(DMAC1_1, DMAC1_1_DEI0, |
180 | DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3), | |
181 | INTC_GROUP(DMAC1_2, DMAC1_2_DEI4, | |
182 | DMAC1_2_DEI5, DMAC1_2_DADERR), | |
e4e430c6 MD |
183 | INTC_GROUP(DMAC2_1, DMAC2_1_DEI0, |
184 | DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), | |
185 | INTC_GROUP(DMAC2_2, DMAC2_2_DEI4, | |
186 | DMAC2_2_DEI5, DMAC2_2_DADERR), | |
187 | INTC_GROUP(DMAC3_1, DMAC3_1_DEI0, | |
188 | DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), | |
189 | INTC_GROUP(DMAC3_2, DMAC3_2_DEI4, | |
190 | DMAC3_2_DEI5, DMAC3_2_DADERR), | |
deded435 KM |
191 | INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX), |
192 | INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, | |
193 | AP_ARM_DMAIRQ, AP_ARM_DMASIRQ), | |
e4e430c6 MD |
194 | INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), |
195 | INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, | |
196 | FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), | |
197 | INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), | |
e4e430c6 MD |
198 | INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), |
199 | }; | |
200 | ||
deded435 | 201 | static struct intc_mask_reg intca_mask_registers[] __initdata = { |
e4e430c6 MD |
202 | { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */ |
203 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, | |
204 | { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */ | |
205 | { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, | |
206 | { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */ | |
207 | { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, | |
208 | { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */ | |
209 | { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, | |
210 | ||
211 | { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ | |
212 | { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, | |
213 | AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, | |
214 | { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */ | |
215 | { 0, CRYPT_STD, DIRC, 0, | |
deded435 | 216 | DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } }, |
e4e430c6 MD |
217 | { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */ |
218 | { 0, 0, 0, 0, | |
219 | BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } }, | |
220 | { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */ | |
221 | { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, | |
222 | DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, | |
223 | { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */ | |
224 | { DDM, 0, 0, 0, | |
225 | 0, 0, 0, 0 } }, | |
226 | { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */ | |
deded435 | 227 | { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4, |
e4e430c6 MD |
228 | SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, |
229 | { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */ | |
230 | { SCIFB, SCIFA5, SCIFA4, MSIOF1, | |
231 | 0, 0, MSIOF2, 0 } }, | |
232 | { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ | |
330e4e71 | 233 | { DISABLED, ENABLED, ENABLED, ENABLED, |
e4e430c6 MD |
234 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, |
235 | { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ | |
330e4e71 | 236 | { 0, ENABLED, ENABLED, ENABLED, |
deded435 | 237 | TTI20, USBHSDMAC0_USHDMI, 0, 0 } }, |
e4e430c6 MD |
238 | { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ |
239 | { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, | |
240 | CMT2, 0, 0, _3DG_SGX540 } }, | |
241 | { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */ | |
242 | { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, | |
243 | 0, 0, 0, 0 } }, | |
244 | { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */ | |
245 | { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1, | |
246 | 0, 0, IRREM, 0 } }, | |
247 | { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */ | |
248 | { 0, 0, TPU0, 0, | |
249 | 0, 0, 0, 0 } }, | |
250 | { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ | |
c57a31ab | 251 | { DISABLED, DISABLED, ENABLED, ENABLED, |
e4e430c6 MD |
252 | 0, CMT3, 0, RWDT0 } }, |
253 | { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */ | |
254 | { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, | |
255 | 0, 0, 0, 0 } }, | |
256 | { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */ | |
257 | { 0, 0, 0, 0, | |
258 | 0, 0, 0, HDMI } }, | |
259 | { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */ | |
260 | { SPU2_SPU0, SPU2_SPU1, FSI, FMSI, | |
261 | 0, 0, 0, MIPI_HSI } }, | |
262 | { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */ | |
deded435 | 263 | { 0, IPMMU_IPMMUD, CEC_1, CEC_2, |
e4e430c6 MD |
264 | AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, |
265 | AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } }, | |
266 | { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */ | |
267 | { MFIS2, CPORTR2S, CMT14, CMT15, | |
268 | 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } }, | |
269 | { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */ | |
270 | { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4, | |
271 | IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } }, | |
272 | { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */ | |
273 | { 0, 0, 0, 0, | |
274 | USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } }, | |
275 | { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */ | |
deded435 | 276 | { USBHSDMAC1_USHDMI, 0, 0, 0, |
e4e430c6 MD |
277 | 0, 0, 0, 0 } }, |
278 | }; | |
279 | ||
deded435 | 280 | static struct intc_prio_reg intca_prio_registers[] __initdata = { |
e4e430c6 MD |
281 | { 0xe6900010, 0, 32, 4, /* INTPRI00A */ |
282 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, | |
283 | { 0xe6900014, 0, 32, 4, /* INTPRI10A */ | |
284 | { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, | |
deded435 | 285 | { 0xe6900018, 0, 32, 4, /* INTPRI20A */ |
e4e430c6 MD |
286 | { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, |
287 | { 0xe690001c, 0, 32, 4, /* INTPRI30A */ | |
288 | { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, | |
289 | ||
290 | { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } }, | |
291 | { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, | |
292 | { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD, | |
293 | CMT1_CMT11, AP_ARM1 } }, | |
294 | { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, | |
295 | CMT1_CMT12, 0 } }, | |
deded435 | 296 | { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS, |
e4e430c6 | 297 | MFI_MFIM, 0 } }, |
deded435 | 298 | { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2, |
e4e430c6 MD |
299 | _3DG_SGX540, CMT1_CMT10 } }, |
300 | { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, | |
301 | SCIFA2, SCIFA3 } }, | |
deded435 | 302 | { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI, |
e4e430c6 | 303 | FLCTL, SDHI0 } }, |
deded435 KM |
304 | { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, |
305 | 0/* MSU */, IIC1 } }, | |
306 | { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, | |
307 | 0/* MSUG */, TTI20 } }, | |
e4e430c6 MD |
308 | { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } }, |
309 | { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } }, | |
310 | { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, | |
311 | { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, | |
312 | { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, | |
313 | { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, | |
314 | { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } }, | |
315 | { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, | |
316 | { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } }, | |
317 | { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0, | |
deded435 | 318 | CEC_1, CEC_2 } }, |
e4e430c6 MD |
319 | { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, |
320 | { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, | |
321 | CMT14, CMT15 } }, | |
0fff9ec1 | 322 | { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0, |
e4e430c6 | 323 | MMC_MMC_ERR, MMC_MMC_NOR } }, |
0fff9ec1 | 324 | { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4, |
e4e430c6 | 325 | IIC4_WAITI4, IIC4_DTEI4 } }, |
0fff9ec1 | 326 | { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3, |
e4e430c6 | 327 | IIC3_WAITI3, IIC3_DTEI3 } }, |
0fff9ec1 | 328 | { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/, |
deded435 | 329 | 0/*TXI*/, 0/*TEI*/} }, |
0fff9ec1 | 330 | { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0, |
e4e430c6 | 331 | USB1_USB1I1, USB1_USB1I0 } }, |
0fff9ec1 | 332 | { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, |
e4e430c6 MD |
333 | }; |
334 | ||
335 | static struct intc_sense_reg intca_sense_registers[] __initdata = { | |
deded435 | 336 | { 0xe6900000, 32, 4, /* ICR1A */ |
e4e430c6 | 337 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, |
deded435 | 338 | { 0xe6900004, 32, 4, /* ICR2A */ |
e4e430c6 | 339 | { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, |
deded435 | 340 | { 0xe6900008, 32, 4, /* ICR3A */ |
e4e430c6 | 341 | { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, |
deded435 | 342 | { 0xe690000c, 32, 4, /* ICR4A */ |
e4e430c6 MD |
343 | { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, |
344 | }; | |
345 | ||
346 | static struct intc_mask_reg intca_ack_registers[] __initdata = { | |
347 | { 0xe6900020, 0, 8, /* INTREQ00A */ | |
348 | { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, | |
349 | { 0xe6900024, 0, 8, /* INTREQ10A */ | |
350 | { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, | |
351 | { 0xe6900028, 0, 8, /* INTREQ20A */ | |
352 | { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } }, | |
353 | { 0xe690002c, 0, 8, /* INTREQ30A */ | |
354 | { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } }, | |
355 | }; | |
356 | ||
c57a31ab MD |
357 | static struct intc_desc intca_desc __initdata = { |
358 | .name = "sh7372-intca", | |
359 | .force_enable = ENABLED, | |
360 | .force_disable = DISABLED, | |
361 | .hw = INTC_HW_DESC(intca_vectors, intca_groups, | |
362 | intca_mask_registers, intca_prio_registers, | |
363 | intca_sense_registers, intca_ack_registers), | |
364 | }; | |
e4e430c6 | 365 | |
f4dd6185 MD |
366 | enum { |
367 | UNUSED_INTCS = 0, | |
368 | ||
369 | INTCS, | |
370 | ||
371 | /* interrupt sources INTCS */ | |
7923ac13 KM |
372 | |
373 | /* IRQ0S - IRQ31S */ | |
f4dd6185 MD |
374 | VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3, |
375 | RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3, | |
376 | CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2, | |
7923ac13 KM |
377 | /* MFI */ |
378 | /* BBIF2 */ | |
f4dd6185 MD |
379 | VPU, |
380 | TSIF1, | |
381 | _3DG_SGX530, | |
382 | _2DDMAC, | |
383 | IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, | |
384 | IPMMU_IPMMUR, IPMMU_IPMMUR2, | |
385 | RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR, | |
7923ac13 KM |
386 | /* KEYSC */ |
387 | /* TTI20 */ | |
f4dd6185 MD |
388 | MSIOF, |
389 | IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, | |
390 | TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, | |
391 | CMT0, | |
392 | TSIF0, | |
7923ac13 | 393 | /* CMT2 */ |
f4dd6185 MD |
394 | LMB, |
395 | CTI, | |
7923ac13 | 396 | /* RWDT0 */ |
f4dd6185 MD |
397 | ICB, |
398 | JPU_JPEG, | |
399 | LCDC, | |
400 | LCRC, | |
401 | RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3, | |
402 | RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, | |
403 | ISP, | |
404 | LCDC1, | |
405 | CSIRX, | |
406 | DSITX_DSITX0, | |
407 | DSITX_DSITX1, | |
7923ac13 KM |
408 | /* SPU2 */ |
409 | /* FSI */ | |
410 | /* FMSI */ | |
411 | /* HDMI */ | |
f4dd6185 MD |
412 | TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, |
413 | CMT4, | |
414 | DSITX1_DSITX1_0, | |
415 | DSITX1_DSITX1_1, | |
7923ac13 | 416 | /* MFIS2 */ |
f4dd6185 | 417 | CPORTS2R, |
7923ac13 | 418 | /* CEC */ |
f4dd6185 MD |
419 | JPU6E, |
420 | ||
421 | /* interrupt groups INTCS */ | |
422 | RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2, | |
423 | RTDMAC2_1, RTDMAC2_2, TMU1, DSITX, | |
424 | }; | |
425 | ||
426 | static struct intc_vect intcs_vectors[] = { | |
7923ac13 | 427 | /* IRQ0S - IRQ31S */ |
f4dd6185 MD |
428 | INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720), |
429 | INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760), | |
430 | INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820), | |
431 | INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860), | |
432 | INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0), | |
433 | INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0), | |
7923ac13 KM |
434 | /* MFI */ |
435 | /* BBIF2 */ | |
f4dd6185 MD |
436 | INTCS_VECT(VPU, 0x980), |
437 | INTCS_VECT(TSIF1, 0x9a0), | |
438 | INTCS_VECT(_3DG_SGX530, 0x9e0), | |
439 | INTCS_VECT(_2DDMAC, 0xa00), | |
440 | INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0), | |
441 | INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0), | |
442 | INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20), | |
443 | INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0), | |
444 | INTCS_VECT(RTDMAC_2_DADERR, 0xbc0), | |
7923ac13 KM |
445 | /* KEYSC */ |
446 | /* TTI20 */ | |
447 | INTCS_VECT(MSIOF, 0x0d20), | |
f4dd6185 MD |
448 | INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20), |
449 | INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60), | |
450 | INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0), | |
451 | INTCS_VECT(TMU_TUNI2, 0xec0), | |
452 | INTCS_VECT(CMT0, 0xf00), | |
453 | INTCS_VECT(TSIF0, 0xf20), | |
7923ac13 | 454 | /* CMT2 */ |
f4dd6185 MD |
455 | INTCS_VECT(LMB, 0xf60), |
456 | INTCS_VECT(CTI, 0x400), | |
7923ac13 | 457 | /* RWDT0 */ |
f4dd6185 MD |
458 | INTCS_VECT(ICB, 0x480), |
459 | INTCS_VECT(JPU_JPEG, 0x560), | |
460 | INTCS_VECT(LCDC, 0x580), | |
461 | INTCS_VECT(LCRC, 0x5a0), | |
462 | INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320), | |
463 | INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360), | |
464 | INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0), | |
465 | INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0), | |
466 | INTCS_VECT(ISP, 0x1720), | |
467 | INTCS_VECT(LCDC1, 0x1780), | |
468 | INTCS_VECT(CSIRX, 0x17a0), | |
469 | INTCS_VECT(DSITX_DSITX0, 0x17c0), | |
470 | INTCS_VECT(DSITX_DSITX1, 0x17e0), | |
7923ac13 KM |
471 | /* SPU2 */ |
472 | /* FSI */ | |
473 | /* FMSI */ | |
474 | /* HDMI */ | |
f4dd6185 MD |
475 | INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920), |
476 | INTCS_VECT(TMU1_TUNI2, 0x1940), | |
477 | INTCS_VECT(CMT4, 0x1980), | |
478 | INTCS_VECT(DSITX1_DSITX1_0, 0x19a0), | |
479 | INTCS_VECT(DSITX1_DSITX1_1, 0x19c0), | |
7923ac13 | 480 | /* MFIS2 */ |
f4dd6185 | 481 | INTCS_VECT(CPORTS2R, 0x1a20), |
7923ac13 | 482 | /* CEC */ |
f4dd6185 MD |
483 | INTCS_VECT(JPU6E, 0x1a80), |
484 | ||
485 | INTC_VECT(INTCS, 0xf80), | |
486 | }; | |
487 | ||
488 | static struct intc_group intcs_groups[] __initdata = { | |
489 | INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1, | |
490 | RTDMAC_1_DEI2, RTDMAC_1_DEI3), | |
491 | INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR), | |
492 | INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3), | |
493 | INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2), | |
494 | INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0), | |
495 | INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2), | |
496 | INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2), | |
497 | INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, | |
498 | RTDMAC2_1_DEI2, RTDMAC2_1_DEI3), | |
499 | INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, | |
500 | RTDMAC2_2_DEI5, RTDMAC2_2_DADERR), | |
501 | INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0), | |
502 | INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1), | |
503 | }; | |
504 | ||
505 | static struct intc_mask_reg intcs_mask_registers[] = { | |
506 | { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ | |
507 | { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU, | |
508 | VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } }, | |
509 | { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ | |
510 | { 0, 0, 0, VPU, | |
511 | 0, 0, 0, 0 } }, | |
512 | { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ | |
513 | { 0, 0, 0, _2DDMAC, | |
514 | 0, 0, 0, ICB } }, | |
515 | { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ | |
516 | { 0, 0, 0, CTI, | |
517 | JPU_JPEG, 0, LCRC, LCDC } }, | |
518 | { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ | |
519 | { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4, | |
520 | RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } }, | |
521 | { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ | |
522 | { 0, 0, MSIOF, 0, | |
523 | _3DG_SGX530, 0, 0, 0 } }, | |
524 | { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ | |
525 | { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0, | |
526 | 0, 0, 0, 0 } }, | |
527 | { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ | |
528 | { 0, 0, 0, CMT0, | |
529 | IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } }, | |
530 | { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */ | |
531 | { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR, | |
532 | 0, 0, 0, 0 } }, | |
533 | { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ | |
534 | { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0, | |
535 | 0, TSIF1, LMB, TSIF0 } }, | |
536 | { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */ | |
537 | { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4, | |
538 | RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } }, | |
539 | { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */ | |
540 | { 0, ISP, 0, 0, | |
541 | LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } }, | |
542 | { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */ | |
543 | { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, | |
544 | CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } }, | |
545 | { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ | |
546 | { 0, CPORTS2R, 0, 0, | |
547 | JPU6E, 0, 0, 0 } }, | |
548 | { 0xffd20104, 0, 16, /* INTAMASK */ | |
549 | { 0, 0, 0, 0, 0, 0, 0, 0, | |
550 | 0, 0, 0, 0, 0, 0, 0, INTCS } }, | |
551 | }; | |
552 | ||
553 | /* Priority is needed for INTCA to receive the INTCS interrupt */ | |
554 | static struct intc_prio_reg intcs_prio_registers[] = { | |
555 | { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } }, | |
556 | { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } }, | |
557 | { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } }, | |
558 | { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } }, | |
559 | { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1, | |
560 | TMU_TUNI2, TSIF1 } }, | |
561 | { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } }, | |
562 | { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } }, | |
563 | { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } }, | |
564 | { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } }, | |
565 | { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } }, | |
566 | { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } }, | |
567 | { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } }, | |
568 | { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } }, | |
569 | { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } }, | |
570 | { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } }, | |
571 | { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } }, | |
572 | { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0, | |
573 | DSITX1_DSITX1_1, 0 } }, | |
574 | { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } }, | |
575 | { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } }, | |
576 | }; | |
577 | ||
578 | static struct resource intcs_resources[] __initdata = { | |
579 | [0] = { | |
580 | .start = 0xffd20000, | |
581 | .end = 0xffd201ff, | |
582 | .flags = IORESOURCE_MEM, | |
583 | }, | |
584 | [1] = { | |
585 | .start = 0xffd50000, | |
586 | .end = 0xffd501ff, | |
587 | .flags = IORESOURCE_MEM, | |
588 | } | |
589 | }; | |
590 | ||
591 | static struct intc_desc intcs_desc __initdata = { | |
592 | .name = "sh7372-intcs", | |
593 | .resource = intcs_resources, | |
594 | .num_resources = ARRAY_SIZE(intcs_resources), | |
595 | .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, | |
596 | intcs_prio_registers, NULL, NULL), | |
597 | }; | |
598 | ||
599 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) | |
600 | { | |
601 | void __iomem *reg = (void *)get_irq_data(irq); | |
602 | unsigned int evtcodeas = ioread32(reg); | |
603 | ||
604 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | |
605 | } | |
606 | ||
e4e430c6 MD |
607 | void __init sh7372_init_irq(void) |
608 | { | |
f4dd6185 MD |
609 | void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); |
610 | ||
e4e430c6 | 611 | register_intc_controller(&intca_desc); |
f4dd6185 MD |
612 | register_intc_controller(&intcs_desc); |
613 | ||
614 | /* demux using INTEVTSA */ | |
615 | set_irq_data(evt2irq(0xf80), (void *)intevtsa); | |
616 | set_irq_chained_handler(evt2irq(0xf80), intcs_demux); | |
e4e430c6 | 617 | } |