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a662c082 MD |
1 | /* |
2 | * r8a7779 Power management support | |
3 | * | |
4 | * Copyright (C) 2011 Renesas Solutions Corp. | |
5 | * Copyright (C) 2011 Magnus Damm | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
12 | #include <linux/pm.h> | |
13 | #include <linux/suspend.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/pm_clock.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/console.h> | |
a662c082 MD |
21 | #include <asm/io.h> |
22 | #include <mach/common.h> | |
23 | #include <mach/r8a7779.h> | |
24 | ||
25 | static void __iomem *r8a7779_sysc_base; | |
26 | ||
27 | /* SYSC */ | |
28 | #define SYSCSR 0x00 | |
29 | #define SYSCISR 0x04 | |
30 | #define SYSCISCR 0x08 | |
31 | #define SYSCIER 0x0c | |
32 | #define SYSCIMR 0x10 | |
33 | #define PWRSR0 0x40 | |
34 | #define PWRSR1 0x80 | |
35 | #define PWRSR2 0xc0 | |
36 | #define PWRSR3 0x100 | |
37 | #define PWRSR4 0x140 | |
38 | ||
39 | #define PWRSR_OFFS 0x00 | |
40 | #define PWROFFCR_OFFS 0x04 | |
41 | #define PWRONCR_OFFS 0x0c | |
42 | #define PWRER_OFFS 0x14 | |
43 | ||
44 | #define SYSCSR_RETRIES 100 | |
45 | #define SYSCSR_DELAY_US 1 | |
46 | ||
47 | #define SYSCISR_RETRIES 1000 | |
48 | #define SYSCISR_DELAY_US 1 | |
49 | ||
f40aaf6d MD |
50 | #if defined(CONFIG_PM) || defined(CONFIG_SMP) |
51 | ||
52 | static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */ | |
a662c082 MD |
53 | |
54 | static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch, | |
55 | int sr_bit, int reg_offs) | |
56 | { | |
57 | int k; | |
58 | ||
59 | for (k = 0; k < SYSCSR_RETRIES; k++) { | |
60 | if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit)) | |
61 | break; | |
62 | udelay(SYSCSR_DELAY_US); | |
63 | } | |
64 | ||
65 | if (k == SYSCSR_RETRIES) | |
66 | return -EAGAIN; | |
67 | ||
68 | iowrite32(1 << r8a7779_ch->chan_bit, | |
69 | r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs); | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
74 | static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch) | |
75 | { | |
76 | return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS); | |
77 | } | |
78 | ||
79 | static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch) | |
80 | { | |
81 | return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS); | |
82 | } | |
83 | ||
84 | static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch, | |
85 | int (*on_off_fn)(struct r8a7779_pm_ch *)) | |
86 | { | |
87 | unsigned int isr_mask = 1 << r8a7779_ch->isr_bit; | |
88 | unsigned int chan_mask = 1 << r8a7779_ch->chan_bit; | |
89 | unsigned int status; | |
f40aaf6d | 90 | unsigned long flags; |
a662c082 MD |
91 | int ret = 0; |
92 | int k; | |
93 | ||
f40aaf6d MD |
94 | spin_lock_irqsave(&r8a7779_sysc_lock, flags); |
95 | ||
a662c082 MD |
96 | iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); |
97 | ||
98 | do { | |
99 | ret = on_off_fn(r8a7779_ch); | |
100 | if (ret) | |
101 | goto out; | |
102 | ||
103 | status = ioread32(r8a7779_sysc_base + | |
104 | r8a7779_ch->chan_offs + PWRER_OFFS); | |
105 | } while (status & chan_mask); | |
106 | ||
107 | for (k = 0; k < SYSCISR_RETRIES; k++) { | |
108 | if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask) | |
109 | break; | |
110 | udelay(SYSCISR_DELAY_US); | |
111 | } | |
112 | ||
113 | if (k == SYSCISR_RETRIES) | |
114 | ret = -EIO; | |
115 | ||
116 | iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); | |
117 | ||
118 | out: | |
f40aaf6d MD |
119 | spin_unlock_irqrestore(&r8a7779_sysc_lock, flags); |
120 | ||
a662c082 MD |
121 | pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n", |
122 | r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0), | |
123 | ioread32(r8a7779_sysc_base + PWRSR1), | |
124 | ioread32(r8a7779_sysc_base + PWRSR2), | |
125 | ioread32(r8a7779_sysc_base + PWRSR3), | |
126 | ioread32(r8a7779_sysc_base + PWRSR4), ret); | |
127 | return ret; | |
128 | } | |
129 | ||
f40aaf6d | 130 | int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch) |
a662c082 MD |
131 | { |
132 | return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off); | |
133 | } | |
134 | ||
f40aaf6d | 135 | int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch) |
a662c082 MD |
136 | { |
137 | return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on); | |
138 | } | |
139 | ||
140 | static void __init r8a7779_sysc_init(void) | |
141 | { | |
142 | r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE); | |
143 | if (!r8a7779_sysc_base) | |
144 | panic("unable to ioremap r8a7779 SYSC hardware block\n"); | |
145 | ||
146 | /* enable all interrupt sources, but do not use interrupt handler */ | |
147 | iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER); | |
148 | iowrite32(0, r8a7779_sysc_base + SYSCIMR); | |
149 | } | |
150 | ||
f40aaf6d MD |
151 | #else /* CONFIG_PM || CONFIG_SMP */ |
152 | ||
153 | static inline void r8a7779_sysc_init(void) {} | |
154 | ||
155 | #endif /* CONFIG_PM || CONFIG_SMP */ | |
156 | ||
157 | #ifdef CONFIG_PM | |
158 | ||
a662c082 MD |
159 | static int pd_power_down(struct generic_pm_domain *genpd) |
160 | { | |
161 | return r8a7779_sysc_power_down(to_r8a7779_ch(genpd)); | |
162 | } | |
163 | ||
164 | static int pd_power_up(struct generic_pm_domain *genpd) | |
165 | { | |
166 | return r8a7779_sysc_power_up(to_r8a7779_ch(genpd)); | |
167 | } | |
168 | ||
169 | static bool pd_is_off(struct generic_pm_domain *genpd) | |
170 | { | |
171 | struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd); | |
172 | unsigned int st; | |
173 | ||
174 | st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS); | |
175 | if (st & (1 << r8a7779_ch->chan_bit)) | |
176 | return true; | |
177 | ||
178 | return false; | |
179 | } | |
180 | ||
181 | static bool pd_active_wakeup(struct device *dev) | |
182 | { | |
183 | return true; | |
184 | } | |
185 | ||
45e5ca57 | 186 | static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd) |
a662c082 MD |
187 | { |
188 | struct generic_pm_domain *genpd = &r8a7779_pd->genpd; | |
189 | ||
190 | pm_genpd_init(genpd, NULL, false); | |
191 | genpd->dev_ops.stop = pm_clk_suspend; | |
192 | genpd->dev_ops.start = pm_clk_resume; | |
193 | genpd->dev_ops.active_wakeup = pd_active_wakeup; | |
194 | genpd->dev_irq_safe = true; | |
195 | genpd->power_off = pd_power_down; | |
196 | genpd->power_on = pd_power_up; | |
197 | ||
198 | if (pd_is_off(&r8a7779_pd->genpd)) | |
199 | pd_power_up(&r8a7779_pd->genpd); | |
200 | } | |
201 | ||
45e5ca57 RW |
202 | static struct r8a7779_pm_domain r8a7779_pm_domains[] = { |
203 | { | |
204 | .genpd.name = "SH4A", | |
205 | .ch = { | |
206 | .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */ | |
207 | .isr_bit = 16, /* SH4A */ | |
208 | }, | |
209 | }, | |
210 | { | |
211 | .genpd.name = "SGX", | |
212 | .ch = { | |
213 | .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */ | |
214 | .isr_bit = 20, /* SGX */ | |
215 | }, | |
216 | }, | |
217 | { | |
218 | .genpd.name = "VDP1", | |
219 | .ch = { | |
220 | .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */ | |
221 | .isr_bit = 21, /* VDP */ | |
222 | }, | |
223 | }, | |
224 | { | |
225 | .genpd.name = "IMPX3", | |
226 | .ch = { | |
227 | .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */ | |
228 | .isr_bit = 24, /* IMP */ | |
229 | }, | |
230 | }, | |
a662c082 MD |
231 | }; |
232 | ||
45e5ca57 RW |
233 | void __init r8a7779_init_pm_domains(void) |
234 | { | |
235 | int j; | |
a662c082 | 236 | |
45e5ca57 RW |
237 | for (j = 0; j < ARRAY_SIZE(r8a7779_pm_domains); j++) |
238 | r8a7779_init_pm_domain(&r8a7779_pm_domains[j]); | |
239 | } | |
a662c082 | 240 | |
a662c082 MD |
241 | #endif /* CONFIG_PM */ |
242 | ||
243 | void __init r8a7779_pm_init(void) | |
244 | { | |
f40aaf6d MD |
245 | static int once; |
246 | ||
247 | if (!once++) | |
248 | r8a7779_sysc_init(); | |
a662c082 | 249 | } |