[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a73a4.c

/*
 * r8a73a4 processor support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a73a4.h>
#include <asm/mach/arch.h>

#define SCIF_COMMON(scif_type, baseaddr, irq)			\
	.type		= scif_type,				\
	.mapbase	= baseaddr,				\
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,	\
	.scbrr_algo_id	= SCBRR_ALGO_4,				\
	.irqs		= SCIx_IRQ_MUXED(irq)

#define SCIFA_DATA(index, baseaddr, irq)		\
[index] = {						\
	SCIF_COMMON(PORT_SCIFA, baseaddr, irq),		\
	.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,	\
}

#define SCIFB_DATA(index, baseaddr, irq)	\
[index] = {					\
	SCIF_COMMON(PORT_SCIFB, baseaddr, irq),	\
	.scscr = SCSCR_RE | SCSCR_TE,		\
}

enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };

static const struct plat_sci_port scif[] = {
	SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
	SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
	SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
	SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
	SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
	SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
};

static inline void r8a73a4_register_scif(int idx)
{
	platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
				      sizeof(struct plat_sci_port));
}

static const struct renesas_irqc_config irqc0_data = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
};

static const struct resource irqc0_resources[] = {
	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
	DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
	DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
	DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
	DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
	DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
	DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
	DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
	DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
	DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
	DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
	DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
	DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
	DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
	DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
	DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
	DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
	DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
	DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
	DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
	DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
	DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
};

static const struct renesas_irqc_config irqc1_data = {
	.irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
};

static const struct resource irqc1_resources[] = {
	DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
	DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
	DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
	DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
	DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
	DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
	DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
	DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
	DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
	DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
	DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
	DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
	DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
	DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
	DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
	DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
	DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
	DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
	DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
	DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
	DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
	DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
	DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
	DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
	DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
	DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
	DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
};

#define r8a73a4_register_irqc(idx)					\
	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
					  idx, irqc##idx##_resources,	\
					  ARRAY_SIZE(irqc##idx##_resources), \
					  &irqc##idx##_data,		\
					  sizeof(struct renesas_irqc_config))

void __init r8a73a4_add_standard_devices(void)
{
	r8a73a4_register_scif(SCIFA0);
	r8a73a4_register_scif(SCIFA1);
	r8a73a4_register_scif(SCIFB0);
	r8a73a4_register_scif(SCIFB1);
	r8a73a4_register_scif(SCIFB2);
	r8a73a4_register_scif(SCIFB3);
	r8a73a4_register_irqc(0);
	r8a73a4_register_irqc(1);
}

#ifdef CONFIG_USE_OF
void __init r8a73a4_add_standard_devices_dt(void)
{
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static const char *r8a73a4_boards_compat_dt[] __initdata = {
	"renesas,r8a73a4",
	NULL,
};

DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
	.init_irq	= irqchip_init,
	.init_machine	= r8a73a4_add_standard_devices_dt,
	.init_time	= shmobile_timer_init,
	.dt_compat	= r8a73a4_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
Commit	Line	Data
eccf0607 MD	1	/*
	2	* r8a73a4 processor support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20	#include <linux/irq.h>
	21	#include <linux/irqchip.h>
	22	#include <linux/kernel.h>
	23	#include <linux/of_platform.h>
984ca295	24	#include <linux/platform_data/irq-renesas-irqc.h>
e481a528	25	#include <linux/serial_sci.h>
eccf0607 MD	26	#include <mach/common.h>
	27	#include <mach/irqs.h>
	28	#include <mach/r8a73a4.h>
	29	#include <asm/mach/arch.h>
	30
e481a528 MD	31	#define SCIF_COMMON(scif_type, baseaddr, irq) \
	32	.type = scif_type, \
	33	.mapbase = baseaddr, \
	34	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP, \
	35	.scbrr_algo_id = SCBRR_ALGO_4, \
	36	.irqs = SCIx_IRQ_MUXED(irq)
	37
	38	#define SCIFA_DATA(index, baseaddr, irq) \
	39	[index] = { \
	40	SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
	41	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE0, \
	42	}
	43
	44	#define SCIFB_DATA(index, baseaddr, irq) \
	45	[index] = { \
	46	SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
	47	.scscr = SCSCR_RE \| SCSCR_TE, \
	48	}
	49
	50	enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
	51
	52	static const struct plat_sci_port scif[] = {
	53	SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
	54	SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
	55	SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
	56	SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
	57	SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
	58	SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
	59	};
	60
	61	static inline void r8a73a4_register_scif(int idx)
	62	{
	63	platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
	64	sizeof(struct plat_sci_port));
	65	}
	66
984ca295 MD	67	static const struct renesas_irqc_config irqc0_data = {
	68	.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
	69	};
	70
	71	static const struct resource irqc0_resources[] = {
	72	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	73	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	74	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	75	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	76	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	77	DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
	78	DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
	79	DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
	80	DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
	81	DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
	82	DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
	83	DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
	84	DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
	85	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
	86	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
	87	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
	88	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
	89	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
	90	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
	91	DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
	92	DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
	93	DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
	94	DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
	95	DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
	96	DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
	97	DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
	98	DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
	99	DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
	100	DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
	101	DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
	102	DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
	103	DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
	104	DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
	105	};
	106
	107	static const struct renesas_irqc_config irqc1_data = {
	108	.irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
	109	};
	110
	111	static const struct resource irqc1_resources[] = {
	112	DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
	113	DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
	114	DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
	115	DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
	116	DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
	117	DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
	118	DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
	119	DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
	120	DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
	121	DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
	122	DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
	123	DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
	124	DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
	125	DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
	126	DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
	127	DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
	128	DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
	129	DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
	130	DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
131	DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
132	DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
133	DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
134	DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
135	DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
136	DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
137	DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
138	DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
139	};
140
141	#define r8a73a4_register_irqc(idx) \
142	platform_device_register_resndata(&platform_bus, "renesas_irqc", \
143	idx, irqc##idx##_resources, \
144	ARRAY_SIZE(irqc##idx##_resources), \
145	&irqc##idx##_data, \
146	sizeof(struct renesas_irqc_config))
147
eccf0607 MD	148	void __init r8a73a4_add_standard_devices(void)
eccf0607 MD	149	{
e481a528 MD	150	r8a73a4_register_scif(SCIFA0);
	151	r8a73a4_register_scif(SCIFA1);
	152	r8a73a4_register_scif(SCIFB0);
	153	r8a73a4_register_scif(SCIFB1);
	154	r8a73a4_register_scif(SCIFB2);
	155	r8a73a4_register_scif(SCIFB3);
984ca295 MD	156	r8a73a4_register_irqc(0);
984ca295 MD	157	r8a73a4_register_irqc(1);
eccf0607 MD	158	}
	159
	160	#ifdef CONFIG_USE_OF
	161	void __init r8a73a4_add_standard_devices_dt(void)
	162	{
	163	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	164	}
	165
	166	static const char *r8a73a4_boards_compat_dt[] __initdata = {
	167	"renesas,r8a73a4",
	168	NULL,
	169	};
	170
	171	DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
	172	.init_irq = irqchip_init,
	173	.init_machine = r8a73a4_add_standard_devices_dt,
	174	.init_time = shmobile_timer_init,
	175	.dt_compat = r8a73a4_boards_compat_dt,
	176	MACHINE_END
	177	#endif /* CONFIG_USE_OF */