projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'ecryptfs-3.13-rc1-quiet-checkers' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7740.c
CommitLineData
6c01ba44
KM		 1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
6831f3a9 20#include <linux/delay.h>
3841e6f5 21#include <linux/dma-mapping.h>
6c01ba44
KM		 22#include <linux/kernel.h>
23#include <linux/init.h>
6831f3a9 24#include <linux/io.h>
70e3f3d4
KM		 25#include <linux/irqchip.h>
26#include <linux/irqchip/arm-gic.h>
0b7d7820 27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
6c01ba44 28#include <linux/platform_device.h>
755d57b2 29#include <linux/of_platform.h>
6c01ba44 30#include <linux/serial_sci.h>
643c3307 31#include <linux/sh_dma.h>
6c01ba44 32#include <linux/sh_timer.h>
f671e022 33#include <linux/platform_data/sh_ipmmu.h>
d7de938f 34#include <mach/dma-register.h>
6c01ba44 35#include <mach/r8a7740.h>
8459293c 36#include <mach/pm-rmobile.h>
d3ab7221 37#include <mach/common.h>
250a2723 38#include <mach/irqs.h>
6c01ba44 39#include <asm/mach-types.h>
d3ab7221 40#include <asm/mach/map.h>
6c01ba44 41#include <asm/mach/arch.h>
23e5bc03 42#include <asm/mach/time.h>
6c01ba44 43
d3ab7221
MD		 44static struct map_desc r8a7740_io_desc[] __initdata = {
45 /*
46 * for CPGA/INTC/PFC
47 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
48 */
49 {
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
52 .length = 160 << 20,
53 .type = MT_DEVICE_NONSHARED
54 },
55#ifdef CONFIG_CACHE_L2X0
56 /*
57 * for l2x0_init()
58 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
59 */
60 {
61 .virtual = 0xf0002000,
62 .pfn = __phys_to_pfn(0xf0100000),
63 .length = PAGE_SIZE,
64 .type = MT_DEVICE_NONSHARED
65 },
66#endif
67};
68
69void __init r8a7740_map_io(void)
70{
71 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
72}
73
02b01adb 74/* PFC */
3404622a
MD		 75static const struct resource pfc_resources[] = {
76 DEFINE_RES_MEM(0xe6050000, 0x8000),
77 DEFINE_RES_MEM(0xe605800c, 0x0020),
02b01adb
LP		 78};
79
80void __init r8a7740_pinmux_init(void)
81{
3404622a
MD		 82 platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
83 ARRAY_SIZE(pfc_resources));
02b01adb
LP		 84}
85
0b7d7820
BH		 86static struct renesas_intc_irqpin_config irqpin0_platform_data = {
87 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
88};
89
90static struct resource irqpin0_resources[] = {
91 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
92 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
93 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
94 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
95 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
96 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
97 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
98 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
99 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
100 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
101 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
102 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
103 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
104};
105
106static struct platform_device irqpin0_device = {
107 .name = "renesas_intc_irqpin",
108 .id = 0,
109 .resource = irqpin0_resources,
110 .num_resources = ARRAY_SIZE(irqpin0_resources),
111 .dev = {
112 .platform_data = &irqpin0_platform_data,
113 },
114};
115
116static struct renesas_intc_irqpin_config irqpin1_platform_data = {
117 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
118};
119
120static struct resource irqpin1_resources[] = {
121 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
122 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
123 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
124 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
125 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
126 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
127 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
128 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
129 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
130 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
131 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
132 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
133 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
134};
135
136static struct platform_device irqpin1_device = {
137 .name = "renesas_intc_irqpin",
138 .id = 1,
139 .resource = irqpin1_resources,
140 .num_resources = ARRAY_SIZE(irqpin1_resources),
141 .dev = {
142 .platform_data = &irqpin1_platform_data,
143 },
144};
145
146static struct renesas_intc_irqpin_config irqpin2_platform_data = {
147 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
148};
149
150static struct resource irqpin2_resources[] = {
151 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
152 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
153 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
154 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
155 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
156 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
157 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
158 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
159 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
160 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
161 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
162 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
163 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
164};
165
166static struct platform_device irqpin2_device = {
167 .name = "renesas_intc_irqpin",
168 .id = 2,
169 .resource = irqpin2_resources,
170 .num_resources = ARRAY_SIZE(irqpin2_resources),
171 .dev = {
172 .platform_data = &irqpin2_platform_data,
173 },
174};
175
176static struct renesas_intc_irqpin_config irqpin3_platform_data = {
177 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
178};
179
180static struct resource irqpin3_resources[] = {
181 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
182 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
183 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
184 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
185 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
186 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
187 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
188 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
189 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
190 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
191 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
192 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
193 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
194};
195
196static struct platform_device irqpin3_device = {
197 .name = "renesas_intc_irqpin",
198 .id = 3,
199 .resource = irqpin3_resources,
200 .num_resources = ARRAY_SIZE(irqpin3_resources),
201 .dev = {
202 .platform_data = &irqpin3_platform_data,
203 },
204};
205
6c01ba44
KM		 206/* SCIFA0 */
207static struct plat_sci_port scif0_platform_data = {
208 .mapbase = 0xe6c40000,
209 .flags = UPF_BOOT_AUTOCONF,
210 .scscr = SCSCR_RE | SCSCR_TE,
211 .scbrr_algo_id = SCBRR_ALGO_4,
212 .type = PORT_SCIFA,
0b7d7820 213 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
6c01ba44
KM		 214};
215
216static struct platform_device scif0_device = {
217 .name = "sh-sci",
218 .id = 0,
219 .dev = {
220 .platform_data = &scif0_platform_data,
221 },
222};
223
224/* SCIFA1 */
225static struct plat_sci_port scif1_platform_data = {
226 .mapbase = 0xe6c50000,
227 .flags = UPF_BOOT_AUTOCONF,
228 .scscr = SCSCR_RE | SCSCR_TE,
229 .scbrr_algo_id = SCBRR_ALGO_4,
230 .type = PORT_SCIFA,
0b7d7820 231 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
6c01ba44
KM		 232};
233
234static struct platform_device scif1_device = {
235 .name = "sh-sci",
236 .id = 1,
237 .dev = {
238 .platform_data = &scif1_platform_data,
239 },
240};
241
242/* SCIFA2 */
243static struct plat_sci_port scif2_platform_data = {
244 .mapbase = 0xe6c60000,
245 .flags = UPF_BOOT_AUTOCONF,
246 .scscr = SCSCR_RE | SCSCR_TE,
247 .scbrr_algo_id = SCBRR_ALGO_4,
248 .type = PORT_SCIFA,
0b7d7820 249 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
6c01ba44
KM		 250};
251
252static struct platform_device scif2_device = {
253 .name = "sh-sci",
254 .id = 2,
255 .dev = {
256 .platform_data = &scif2_platform_data,
257 },
258};
259
260/* SCIFA3 */
261static struct plat_sci_port scif3_platform_data = {
262 .mapbase = 0xe6c70000,
263 .flags = UPF_BOOT_AUTOCONF,
264 .scscr = SCSCR_RE | SCSCR_TE,
265 .scbrr_algo_id = SCBRR_ALGO_4,
266 .type = PORT_SCIFA,
0b7d7820 267 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
6c01ba44
KM		 268};
269
270static struct platform_device scif3_device = {
271 .name = "sh-sci",
272 .id = 3,
273 .dev = {
274 .platform_data = &scif3_platform_data,
275 },
276};
277
278/* SCIFA4 */
279static struct plat_sci_port scif4_platform_data = {
280 .mapbase = 0xe6c80000,
281 .flags = UPF_BOOT_AUTOCONF,
282 .scscr = SCSCR_RE | SCSCR_TE,
283 .scbrr_algo_id = SCBRR_ALGO_4,
284 .type = PORT_SCIFA,
0b7d7820 285 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
6c01ba44
KM		 286};
287
288static struct platform_device scif4_device = {
289 .name = "sh-sci",
290 .id = 4,
291 .dev = {
292 .platform_data = &scif4_platform_data,
293 },
294};
295
296/* SCIFA5 */
297static struct plat_sci_port scif5_platform_data = {
298 .mapbase = 0xe6cb0000,
299 .flags = UPF_BOOT_AUTOCONF,
300 .scscr = SCSCR_RE | SCSCR_TE,
301 .scbrr_algo_id = SCBRR_ALGO_4,
302 .type = PORT_SCIFA,
0b7d7820 303 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
6c01ba44
KM		 304};
305
306static struct platform_device scif5_device = {
307 .name = "sh-sci",
308 .id = 5,
309 .dev = {
310 .platform_data = &scif5_platform_data,
311 },
312};
313
314/* SCIFA6 */
315static struct plat_sci_port scif6_platform_data = {
316 .mapbase = 0xe6cc0000,
317 .flags = UPF_BOOT_AUTOCONF,
318 .scscr = SCSCR_RE | SCSCR_TE,
319 .scbrr_algo_id = SCBRR_ALGO_4,
320 .type = PORT_SCIFA,
0b7d7820 321 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
6c01ba44
KM		 322};
323
324static struct platform_device scif6_device = {
325 .name = "sh-sci",
326 .id = 6,
327 .dev = {
328 .platform_data = &scif6_platform_data,
329 },
330};
331
332/* SCIFA7 */
333static struct plat_sci_port scif7_platform_data = {
334 .mapbase = 0xe6cd0000,
335 .flags = UPF_BOOT_AUTOCONF,
336 .scscr = SCSCR_RE | SCSCR_TE,
337 .scbrr_algo_id = SCBRR_ALGO_4,
338 .type = PORT_SCIFA,
0b7d7820 339 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
6c01ba44
KM		 340};
341
342static struct platform_device scif7_device = {
343 .name = "sh-sci",
344 .id = 7,
345 .dev = {
346 .platform_data = &scif7_platform_data,
347 },
348};
349
350/* SCIFB */
351static struct plat_sci_port scifb_platform_data = {
352 .mapbase = 0xe6c30000,
353 .flags = UPF_BOOT_AUTOCONF,
354 .scscr = SCSCR_RE | SCSCR_TE,
355 .scbrr_algo_id = SCBRR_ALGO_4,
356 .type = PORT_SCIFB,
0b7d7820 357 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
6c01ba44
KM		 358};
359
360static struct platform_device scifb_device = {
361 .name = "sh-sci",
362 .id = 8,
363 .dev = {
364 .platform_data = &scifb_platform_data,
365 },
366};
367
368/* CMT */
369static struct sh_timer_config cmt10_platform_data = {
370 .name = "CMT10",
371 .channel_offset = 0x10,
372 .timer_bit = 0,
373 .clockevent_rating = 125,
374 .clocksource_rating = 125,
375};
376
377static struct resource cmt10_resources[] = {
378 [0] = {
379 .name = "CMT10",
380 .start = 0xe6138010,
381 .end = 0xe613801b,
382 .flags = IORESOURCE_MEM,
383 },
384 [1] = {
0b7d7820 385 .start = gic_spi(58),
6c01ba44
KM		 386 .flags = IORESOURCE_IRQ,
387 },
388};
389
390static struct platform_device cmt10_device = {
391 .name = "sh_cmt",
392 .id = 10,
393 .dev = {
394 .platform_data = &cmt10_platform_data,
395 },
396 .resource = cmt10_resources,
397 .num_resources = ARRAY_SIZE(cmt10_resources),
398};
399
e67d7afc
KM		 400/* TMU */
401static struct sh_timer_config tmu00_platform_data = {
402 .name = "TMU00",
403 .channel_offset = 0x4,
404 .timer_bit = 0,
405 .clockevent_rating = 200,
406};
407
408static struct resource tmu00_resources[] = {
409 [0] = {
410 .name = "TMU00",
411 .start = 0xfff80008,
412 .end = 0xfff80014 - 1,
413 .flags = IORESOURCE_MEM,
414 },
415 [1] = {
0b7d7820 416 .start = gic_spi(198),
e67d7afc
KM		 417 .flags = IORESOURCE_IRQ,
418 },
419};
420
421static struct platform_device tmu00_device = {
422 .name = "sh_tmu",
423 .id = 0,
424 .dev = {
425 .platform_data = &tmu00_platform_data,
426 },
427 .resource = tmu00_resources,
428 .num_resources = ARRAY_SIZE(tmu00_resources),
429};
430
431static struct sh_timer_config tmu01_platform_data = {
432 .name = "TMU01",
433 .channel_offset = 0x10,
434 .timer_bit = 1,
435 .clocksource_rating = 200,
436};
437
438static struct resource tmu01_resources[] = {
439 [0] = {
440 .name = "TMU01",
441 .start = 0xfff80014,
442 .end = 0xfff80020 - 1,
443 .flags = IORESOURCE_MEM,
444 },
445 [1] = {
0b7d7820 446 .start = gic_spi(199),
e67d7afc
KM		 447 .flags = IORESOURCE_IRQ,
448 },
449};
450
451static struct platform_device tmu01_device = {
452 .name = "sh_tmu",
453 .id = 1,
454 .dev = {
455 .platform_data = &tmu01_platform_data,
456 },
457 .resource = tmu01_resources,
458 .num_resources = ARRAY_SIZE(tmu01_resources),
459};
460
461static struct sh_timer_config tmu02_platform_data = {
462 .name = "TMU02",
463 .channel_offset = 0x1C,
464 .timer_bit = 2,
465 .clocksource_rating = 200,
466};
467
468static struct resource tmu02_resources[] = {
469 [0] = {
470 .name = "TMU02",
471 .start = 0xfff80020,
472 .end = 0xfff8002C - 1,
473 .flags = IORESOURCE_MEM,
474 },
475 [1] = {
0b7d7820 476 .start = gic_spi(200),
e67d7afc
KM		 477 .flags = IORESOURCE_IRQ,
478 },
479};
480
481static struct platform_device tmu02_device = {
482 .name = "sh_tmu",
483 .id = 2,
484 .dev = {
485 .platform_data = &tmu02_platform_data,
486 },
487 .resource = tmu02_resources,
488 .num_resources = ARRAY_SIZE(tmu02_resources),
489};
490
f671e022
HE		 491/* IPMMUI (an IPMMU module for ICB/LMB) */
492static struct resource ipmmu_resources[] = {
493 [0] = {
494 .name = "IPMMUI",
495 .start = 0xfe951000,
496 .end = 0xfe9510ff,
497 .flags = IORESOURCE_MEM,
498 },
499};
500
501static const char * const ipmmu_dev_names[] = {
502 "sh_mobile_lcdc_fb.0",
503 "sh_mobile_lcdc_fb.1",
504 "sh_mobile_ceu.0",
505};
506
507static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
508 .dev_names = ipmmu_dev_names,
509 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
510};
511
512static struct platform_device ipmmu_device = {
513 .name = "ipmmu",
514 .id = -1,
515 .dev = {
516 .platform_data = &ipmmu_platform_data,
517 },
518 .resource = ipmmu_resources,
519 .num_resources = ARRAY_SIZE(ipmmu_resources),
520};
521
744fdc8d 522static struct platform_device *r8a7740_devices_dt[] __initdata = {
6c01ba44
KM		 523 &scif0_device,
524 &scif1_device,
525 &scif2_device,
526 &scif3_device,
527 &scif4_device,
528 &scif5_device,
529 &scif6_device,
530 &scif7_device,
531 &scifb_device,
532 &cmt10_device,
744fdc8d
BH		 533};
534
535static struct platform_device *r8a7740_early_devices[] __initdata = {
536 &irqpin0_device,
537 &irqpin1_device,
538 &irqpin2_device,
539 &irqpin3_device,
e67d7afc
KM		 540 &tmu00_device,
541 &tmu01_device,
542 &tmu02_device,
f671e022 543 &ipmmu_device,
6c01ba44
KM		 544};
545
643c3307 546/* DMA */
643c3307
KM		 547static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
548 {
cb76eb81
KM		 549 .slave_id = SHDMA_SLAVE_SDHI0_TX,
550 .addr = 0xe6850030,
551 .chcr = CHCR_TX(XMIT_SZ_16BIT),
552 .mid_rid = 0xc1,
553 }, {
554 .slave_id = SHDMA_SLAVE_SDHI0_RX,
555 .addr = 0xe6850030,
556 .chcr = CHCR_RX(XMIT_SZ_16BIT),
557 .mid_rid = 0xc2,
558 }, {
559 .slave_id = SHDMA_SLAVE_SDHI1_TX,
560 .addr = 0xe6860030,
561 .chcr = CHCR_TX(XMIT_SZ_16BIT),
562 .mid_rid = 0xc9,
563 }, {
564 .slave_id = SHDMA_SLAVE_SDHI1_RX,
565 .addr = 0xe6860030,
566 .chcr = CHCR_RX(XMIT_SZ_16BIT),
567 .mid_rid = 0xca,
568 }, {
569 .slave_id = SHDMA_SLAVE_SDHI2_TX,
570 .addr = 0xe6870030,
571 .chcr = CHCR_TX(XMIT_SZ_16BIT),
572 .mid_rid = 0xcd,
573 }, {
574 .slave_id = SHDMA_SLAVE_SDHI2_RX,
575 .addr = 0xe6870030,
576 .chcr = CHCR_RX(XMIT_SZ_16BIT),
577 .mid_rid = 0xce,
578 }, {
643c3307
KM		 579 .slave_id = SHDMA_SLAVE_FSIA_TX,
580 .addr = 0xfe1f0024,
581 .chcr = CHCR_TX(XMIT_SZ_32BIT),
582 .mid_rid = 0xb1,
583 }, {
584 .slave_id = SHDMA_SLAVE_FSIA_RX,
585 .addr = 0xfe1f0020,
586 .chcr = CHCR_RX(XMIT_SZ_32BIT),
587 .mid_rid = 0xb2,
588 }, {
589 .slave_id = SHDMA_SLAVE_FSIB_TX,
590 .addr = 0xfe1f0064,
591 .chcr = CHCR_TX(XMIT_SZ_32BIT),
592 .mid_rid = 0xb5,
9a145624
GL		 593 }, {
594 .slave_id = SHDMA_SLAVE_MMCIF_TX,
595 .addr = 0xe6bd0034,
596 .chcr = CHCR_TX(XMIT_SZ_32BIT),
597 .mid_rid = 0xd1,
598 }, {
599 .slave_id = SHDMA_SLAVE_MMCIF_RX,
600 .addr = 0xe6bd0034,
601 .chcr = CHCR_RX(XMIT_SZ_32BIT),
602 .mid_rid = 0xd2,
643c3307
KM		 603 },
604};
605
606#define DMA_CHANNEL(a, b, c) \
607{ \
608 .offset = a, \
609 .dmars = b, \
610 .dmars_bit = c, \
611 .chclr_offset = (0x220 - 0x20) + a \
612}
613
614static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
615 DMA_CHANNEL(0x00, 0, 0),
616 DMA_CHANNEL(0x10, 0, 8),
617 DMA_CHANNEL(0x20, 4, 0),
618 DMA_CHANNEL(0x30, 4, 8),
619 DMA_CHANNEL(0x50, 8, 0),
620 DMA_CHANNEL(0x60, 8, 8),
621};
622
643c3307
KM		 623static struct sh_dmae_pdata dma_platform_data = {
624 .slave = r8a7740_dmae_slaves,
625 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
626 .channel = r8a7740_dmae_channels,
627 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
d7de938f
KM		 628 .ts_low_shift = TS_LOW_SHIFT,
629 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
630 .ts_high_shift = TS_HI_SHIFT,
631 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
632 .ts_shift = dma_ts_shift,
633 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
643c3307
KM		 634 .dmaor_init = DMAOR_DME,
635 .chclr_present = 1,
636};
637
638/* Resource order important! */
639static struct resource r8a7740_dmae0_resources[] = {
640 {
641 /* Channel registers and DMAOR */
642 .start = 0xfe008020,
643 .end = 0xfe00828f,
644 .flags = IORESOURCE_MEM,
645 },
646 {
647 /* DMARSx */
648 .start = 0xfe009000,
649 .end = 0xfe00900b,
650 .flags = IORESOURCE_MEM,
651 },
652 {
653 .name = "error_irq",
0b7d7820
BH		 654 .start = gic_spi(34),
655 .end = gic_spi(34),
643c3307
KM		 656 .flags = IORESOURCE_IRQ,
657 },
658 {
659 /* IRQ for channels 0-5 */
0b7d7820
BH		 660 .start = gic_spi(28),
661 .end = gic_spi(33),
643c3307
KM		 662 .flags = IORESOURCE_IRQ,
663 },
664};
665
666/* Resource order important! */
667static struct resource r8a7740_dmae1_resources[] = {
668 {
669 /* Channel registers and DMAOR */
670 .start = 0xfe018020,
671 .end = 0xfe01828f,
672 .flags = IORESOURCE_MEM,
673 },
674 {
675 /* DMARSx */
676 .start = 0xfe019000,
677 .end = 0xfe01900b,
678 .flags = IORESOURCE_MEM,
679 },
680 {
681 .name = "error_irq",
0b7d7820
BH		 682 .start = gic_spi(41),
683 .end = gic_spi(41),
643c3307
KM		 684 .flags = IORESOURCE_IRQ,
685 },
686 {
687 /* IRQ for channels 0-5 */
0b7d7820
BH		 688 .start = gic_spi(35),
689 .end = gic_spi(40),
643c3307
KM		 690 .flags = IORESOURCE_IRQ,
691 },
692};
693
694/* Resource order important! */
695static struct resource r8a7740_dmae2_resources[] = {
696 {
697 /* Channel registers and DMAOR */
698 .start = 0xfe028020,
699 .end = 0xfe02828f,
700 .flags = IORESOURCE_MEM,
701 },
702 {
703 /* DMARSx */
704 .start = 0xfe029000,
705 .end = 0xfe02900b,
706 .flags = IORESOURCE_MEM,
707 },
708 {
709 .name = "error_irq",
0b7d7820
BH		 710 .start = gic_spi(48),
711 .end = gic_spi(48),
643c3307
KM		 712 .flags = IORESOURCE_IRQ,
713 },
714 {
715 /* IRQ for channels 0-5 */
0b7d7820
BH		 716 .start = gic_spi(42),
717 .end = gic_spi(47),
643c3307
KM		 718 .flags = IORESOURCE_IRQ,
719 },
720};
721
722static struct platform_device dma0_device = {
723 .name = "sh-dma-engine",
724 .id = 0,
725 .resource = r8a7740_dmae0_resources,
726 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
727 .dev = {
728 .platform_data = &dma_platform_data,
729 },
730};
731
732static struct platform_device dma1_device = {
733 .name = "sh-dma-engine",
734 .id = 1,
735 .resource = r8a7740_dmae1_resources,
736 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
737 .dev = {
738 .platform_data = &dma_platform_data,
739 },
740};
741
742static struct platform_device dma2_device = {
743 .name = "sh-dma-engine",
744 .id = 2,
745 .resource = r8a7740_dmae2_resources,
746 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
747 .dev = {
748 .platform_data = &dma_platform_data,
749 },
750};
751
dbf382e5 752/* USB-DMAC */
dbf382e5
KM		 753static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
754 {
755 .offset = 0,
756 }, {
757 .offset = 0x20,
758 },
759};
760
dbf382e5
KM		 761static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
762 {
763 .slave_id = SHDMA_SLAVE_USBHS_TX,
764 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
765 }, {
766 .slave_id = SHDMA_SLAVE_USBHS_RX,
767 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
768 },
769};
770
771static struct sh_dmae_pdata usb_dma_platform_data = {
772 .slave = r8a7740_usb_dma_slaves,
773 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
774 .channel = r8a7740_usb_dma_channels,
775 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
d7de938f
KM		 776 .ts_low_shift = USBTS_LOW_SHIFT,
777 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
778 .ts_high_shift = USBTS_HI_SHIFT,
779 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
dbf382e5
KM		 780 .ts_shift = dma_usbts_shift,
781 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
782 .dmaor_init = DMAOR_DME,
783 .chcr_offset = 0x14,
784 .chcr_ie_bit = 1 << 5,
785 .dmaor_is_32bit = 1,
786 .needs_tend_set = 1,
787 .no_dmars = 1,
788 .slave_only = 1,
789};
790
791static struct resource r8a7740_usb_dma_resources[] = {
792 {
793 /* Channel registers and DMAOR */
794 .start = 0xe68a0020,
795 .end = 0xe68a0064 - 1,
796 .flags = IORESOURCE_MEM,
797 },
798 {
799 /* VCR/SWR/DMICR */
800 .start = 0xe68a0000,
801 .end = 0xe68a0014 - 1,
802 .flags = IORESOURCE_MEM,
803 },
804 {
805 /* IRQ for channels */
0b7d7820
BH		 806 .start = gic_spi(49),
807 .end = gic_spi(49),
dbf382e5
KM		 808 .flags = IORESOURCE_IRQ,
809 },
810};
811
812static struct platform_device usb_dma_device = {
813 .name = "sh-dma-engine",
814 .id = 3,
815 .resource = r8a7740_usb_dma_resources,
816 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
817 .dev = {
818 .platform_data = &usb_dma_platform_data,
819 },
820};
821
6831f3a9
KM		 822/* I2C */
823static struct resource i2c0_resources[] = {
824 [0] = {
825 .name = "IIC0",
826 .start = 0xfff20000,
827 .end = 0xfff20425 - 1,
828 .flags = IORESOURCE_MEM,
829 },
830 [1] = {
0b7d7820
BH		 831 .start = gic_spi(201),
832 .end = gic_spi(204),
6831f3a9
KM		 833 .flags = IORESOURCE_IRQ,
834 },
835};
836
837static struct resource i2c1_resources[] = {
838 [0] = {
839 .name = "IIC1",
840 .start = 0xe6c20000,
841 .end = 0xe6c20425 - 1,
842 .flags = IORESOURCE_MEM,
843 },
844 [1] = {
0b7d7820
BH		 845 .start = gic_spi(70), /* IIC1_ALI1 */
846 .end = gic_spi(73), /* IIC1_DTEI1 */
6831f3a9
KM		 847 .flags = IORESOURCE_IRQ,
848 },
849};
850
851static struct platform_device i2c0_device = {
852 .name = "i2c-sh_mobile",
853 .id = 0,
854 .resource = i2c0_resources,
855 .num_resources = ARRAY_SIZE(i2c0_resources),
856};
857
858static struct platform_device i2c1_device = {
859 .name = "i2c-sh_mobile",
860 .id = 1,
861 .resource = i2c1_resources,
862 .num_resources = ARRAY_SIZE(i2c1_resources),
863};
864
86bc52ef
NI		 865static struct resource pmu_resources[] = {
866 [0] = {
0b7d7820
BH		 867 .start = gic_spi(83),
868 .end = gic_spi(83),
86bc52ef
NI		 869 .flags = IORESOURCE_IRQ,
870 },
871};
872
873static struct platform_device pmu_device = {
874 .name = "arm-pmu",
875 .id = -1,
876 .num_resources = ARRAY_SIZE(pmu_resources),
877 .resource = pmu_resources,
878};
879
6831f3a9
KM		 880static struct platform_device *r8a7740_late_devices[] __initdata = {
881 &i2c0_device,
882 &i2c1_device,
643c3307
KM		 883 &dma0_device,
884 &dma1_device,
885 &dma2_device,
dbf382e5 886 &usb_dma_device,
86bc52ef 887 &pmu_device,
6831f3a9
KM		 888};
889
d49679e5
KM		 890/*
891 * r8a7740 chip has lasting errata on MERAM buffer.
892 * this is work-around for it.
893 * see
894 * "Media RAM (MERAM)" on r8a7740 documentation
895 */
896#define MEBUFCNTR 0xFE950098
897void r8a7740_meram_workaround(void)
898{
899 void __iomem *reg;
900
901 reg = ioremap_nocache(MEBUFCNTR, 4);
902 if (reg) {
903 iowrite32(0x01600164, reg);
904 iounmap(reg);
905 }
906}
907
6831f3a9
KM		 908#define ICCR 0x0004
909#define ICSTART 0x0070
910
911#define i2c_read(reg, offset) ioread8(reg + offset)
912#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
913
914/*
915 * r8a7740 chip has lasting errata on I2C I/O pad reset.
916 * this is work-around for it.
917 */
918static void r8a7740_i2c_workaround(struct platform_device *pdev)
919{
920 struct resource *res;
921 void __iomem *reg;
922
923 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
924 if (unlikely(!res)) {
925 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
926 return;
927 }
928
929 reg = ioremap(res->start, resource_size(res));
930 if (unlikely(!reg)) {
931 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
932 return;
933 }
934
935 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
936 i2c_read(reg, ICCR); /* dummy read */
937
938 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
939 i2c_read(reg, ICSTART); /* dummy read */
940
4228716c 941 udelay(10);
6831f3a9
KM		 942
943 i2c_write(reg, ICCR, 0x01);
6831f3a9 944 i2c_write(reg, ICSTART, 0x00);
4228716c
KM		 945
946 udelay(10);
6831f3a9
KM		 947
948 i2c_write(reg, ICCR, 0x10);
4228716c 949 udelay(10);
6831f3a9 950 i2c_write(reg, ICCR, 0x00);
4228716c 951 udelay(10);
6831f3a9 952 i2c_write(reg, ICCR, 0x10);
4228716c 953 udelay(10);
6831f3a9
KM		 954
955 iounmap(reg);
956}
957
6c01ba44
KM		 958void __init r8a7740_add_standard_devices(void)
959{
6831f3a9
KM		 960 /* I2C work-around */
961 r8a7740_i2c_workaround(&i2c0_device);
962 r8a7740_i2c_workaround(&i2c1_device);
963
7b567407 964 r8a7740_init_pm_domains();
8459293c
KM		 965
966 /* add devices */
6c01ba44
KM		 967 platform_add_devices(r8a7740_early_devices,
968 ARRAY_SIZE(r8a7740_early_devices));
744fdc8d
BH		 969 platform_add_devices(r8a7740_devices_dt,
970 ARRAY_SIZE(r8a7740_devices_dt));
6831f3a9
KM		 971 platform_add_devices(r8a7740_late_devices,
972 ARRAY_SIZE(r8a7740_late_devices));
802a5639
KM		 973
974 /* add devices to PM domain */
975
8bdd9468
RW		 976 rmobile_add_device_to_domain("A3SP", &scif0_device);
977 rmobile_add_device_to_domain("A3SP", &scif1_device);
978 rmobile_add_device_to_domain("A3SP", &scif2_device);
979 rmobile_add_device_to_domain("A3SP", &scif3_device);
980 rmobile_add_device_to_domain("A3SP", &scif4_device);
981 rmobile_add_device_to_domain("A3SP", &scif5_device);
982 rmobile_add_device_to_domain("A3SP", &scif6_device);
983 rmobile_add_device_to_domain("A3SP", &scif7_device);
984 rmobile_add_device_to_domain("A3SP", &scifb_device);
985 rmobile_add_device_to_domain("A3SP", &i2c1_device);
6c01ba44
KM		 986}
987
988void __init r8a7740_add_early_devices(void)
989{
990 early_platform_add_devices(r8a7740_early_devices,
991 ARRAY_SIZE(r8a7740_early_devices));
744fdc8d
BH		 992 early_platform_add_devices(r8a7740_devices_dt,
993 ARRAY_SIZE(r8a7740_devices_dt));
d3ab7221
MD		 994
995 /* setup early console here as well */
996 shmobile_setup_console();
6c01ba44 997}
755d57b2
MD		 998
999#ifdef CONFIG_USE_OF
1000
88378837
MD		 1001void __init r8a7740_add_early_devices_dt(void)
1002{
1003 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
1004
1005 early_platform_add_devices(r8a7740_early_devices,
1006 ARRAY_SIZE(r8a7740_early_devices));
1007
1008 /* setup early console here as well */
1009 shmobile_setup_console();
1010}
755d57b2
MD		 1011
1012void __init r8a7740_add_standard_devices_dt(void)
1013{
744fdc8d
BH		 1014 platform_add_devices(r8a7740_devices_dt,
1015 ARRAY_SIZE(r8a7740_devices_dt));
88378837 1016 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
755d57b2
MD		 1017}
1018
744fdc8d
BH		 1019void __init r8a7740_init_delay(void)
1020{
1021 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
1022};
1023
70e3f3d4
KM		 1024void __init r8a7740_init_irq_of(void)
1025{
1026 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
1027 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
1028 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
1029
1030 irqchip_init();
1031
1032 /* route signals to GIC */
1033 iowrite32(0x0, pfc_inta_ctrl);
1034
1035 /*
1036 * To mask the shared interrupt to SPI 149 we must ensure to set
1037 * PRIO *and* MASK. Else we run into IRQ floods when registering
1038 * the intc_irqpin devices
1039 */
1040 iowrite32(0x0, intc_prio_base + 0x0);
1041 iowrite32(0x0, intc_prio_base + 0x4);
1042 iowrite32(0x0, intc_prio_base + 0x8);
1043 iowrite32(0x0, intc_prio_base + 0xc);
1044 iowrite8(0xff, intc_msk_base + 0x0);
1045 iowrite8(0xff, intc_msk_base + 0x4);
1046 iowrite8(0xff, intc_msk_base + 0x8);
1047 iowrite8(0xff, intc_msk_base + 0xc);
1048
1049 iounmap(intc_prio_base);
1050 iounmap(intc_msk_base);
1051 iounmap(pfc_inta_ctrl);
1052}
1053
744fdc8d
BH		 1054static void __init r8a7740_generic_init(void)
1055{
1056 r8a7740_clock_init(0);
1057 r8a7740_add_standard_devices_dt();
1058}
1059
755d57b2
MD		 1060static const char *r8a7740_boards_compat_dt[] __initdata = {
1061 "renesas,r8a7740",
1062 NULL,
1063};
1064
a41acc4a 1065DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
755d57b2 1066 .map_io = r8a7740_map_io,
744fdc8d
BH		 1067 .init_early = r8a7740_init_delay,
1068 .init_irq = r8a7740_init_irq_of,
1069 .init_machine = r8a7740_generic_init,
755d57b2
MD		 1070 .dt_compat = r8a7740_boards_compat_dt,
1071MACHINE_END
1072
1073#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
This page took 0.147349 seconds and 5 git commands to generate.