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6c01ba44 KM |
1 | /* |
2 | * R8A7740 processor support | |
3 | * | |
4 | * Copyright (C) 2011 Renesas Solutions Corp. | |
5 | * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
6c01ba44 | 15 | */ |
6831f3a9 | 16 | #include <linux/delay.h> |
3841e6f5 | 17 | #include <linux/dma-mapping.h> |
6c01ba44 KM |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
6831f3a9 | 20 | #include <linux/io.h> |
70e3f3d4 KM |
21 | #include <linux/irqchip.h> |
22 | #include <linux/irqchip/arm-gic.h> | |
0b7d7820 | 23 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> |
6c01ba44 | 24 | #include <linux/platform_device.h> |
755d57b2 | 25 | #include <linux/of_platform.h> |
6c01ba44 | 26 | #include <linux/serial_sci.h> |
643c3307 | 27 | #include <linux/sh_dma.h> |
6c01ba44 | 28 | #include <linux/sh_timer.h> |
f671e022 | 29 | #include <linux/platform_data/sh_ipmmu.h> |
9e38b84b | 30 | |
6c01ba44 | 31 | #include <asm/mach-types.h> |
d3ab7221 | 32 | #include <asm/mach/map.h> |
6c01ba44 | 33 | #include <asm/mach/arch.h> |
23e5bc03 | 34 | #include <asm/mach/time.h> |
c41215b7 | 35 | #include <asm/hardware/cache-l2x0.h> |
9e38b84b | 36 | |
fd44aa5e | 37 | #include "common.h" |
74ac0de8 | 38 | #include "dma-register.h" |
b6bab126 | 39 | #include "irqs.h" |
6b8b0cb4 | 40 | #include "pm-rmobile.h" |
9e38b84b | 41 | #include "r8a7740.h" |
6c01ba44 | 42 | |
d3ab7221 MD |
43 | static struct map_desc r8a7740_io_desc[] __initdata = { |
44 | /* | |
45 | * for CPGA/INTC/PFC | |
46 | * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff | |
47 | */ | |
48 | { | |
49 | .virtual = 0xe6000000, | |
50 | .pfn = __phys_to_pfn(0xe6000000), | |
51 | .length = 160 << 20, | |
52 | .type = MT_DEVICE_NONSHARED | |
53 | }, | |
54 | #ifdef CONFIG_CACHE_L2X0 | |
55 | /* | |
56 | * for l2x0_init() | |
57 | * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000 | |
58 | */ | |
59 | { | |
60 | .virtual = 0xf0002000, | |
61 | .pfn = __phys_to_pfn(0xf0100000), | |
62 | .length = PAGE_SIZE, | |
63 | .type = MT_DEVICE_NONSHARED | |
64 | }, | |
65 | #endif | |
66 | }; | |
67 | ||
68 | void __init r8a7740_map_io(void) | |
69 | { | |
7a2071c5 | 70 | debug_ll_io_init(); |
d3ab7221 MD |
71 | iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc)); |
72 | } | |
73 | ||
02b01adb | 74 | /* PFC */ |
3404622a MD |
75 | static const struct resource pfc_resources[] = { |
76 | DEFINE_RES_MEM(0xe6050000, 0x8000), | |
77 | DEFINE_RES_MEM(0xe605800c, 0x0020), | |
02b01adb LP |
78 | }; |
79 | ||
80 | void __init r8a7740_pinmux_init(void) | |
81 | { | |
3404622a MD |
82 | platform_device_register_simple("pfc-r8a7740", -1, pfc_resources, |
83 | ARRAY_SIZE(pfc_resources)); | |
02b01adb LP |
84 | } |
85 | ||
0b7d7820 BH |
86 | static struct renesas_intc_irqpin_config irqpin0_platform_data = { |
87 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ | |
88 | }; | |
89 | ||
90 | static struct resource irqpin0_resources[] = { | |
91 | DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ | |
92 | DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ | |
93 | DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ | |
94 | DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ | |
95 | DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ | |
96 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */ | |
97 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */ | |
98 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */ | |
99 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */ | |
100 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */ | |
101 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */ | |
102 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */ | |
103 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */ | |
104 | }; | |
105 | ||
106 | static struct platform_device irqpin0_device = { | |
107 | .name = "renesas_intc_irqpin", | |
108 | .id = 0, | |
109 | .resource = irqpin0_resources, | |
110 | .num_resources = ARRAY_SIZE(irqpin0_resources), | |
111 | .dev = { | |
112 | .platform_data = &irqpin0_platform_data, | |
113 | }, | |
114 | }; | |
115 | ||
116 | static struct renesas_intc_irqpin_config irqpin1_platform_data = { | |
117 | .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ | |
118 | }; | |
119 | ||
120 | static struct resource irqpin1_resources[] = { | |
121 | DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ | |
122 | DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ | |
123 | DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ | |
124 | DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ | |
125 | DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ | |
126 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */ | |
127 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */ | |
128 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */ | |
129 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */ | |
130 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */ | |
131 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */ | |
132 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */ | |
133 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */ | |
134 | }; | |
135 | ||
136 | static struct platform_device irqpin1_device = { | |
137 | .name = "renesas_intc_irqpin", | |
138 | .id = 1, | |
139 | .resource = irqpin1_resources, | |
140 | .num_resources = ARRAY_SIZE(irqpin1_resources), | |
141 | .dev = { | |
142 | .platform_data = &irqpin1_platform_data, | |
143 | }, | |
144 | }; | |
145 | ||
146 | static struct renesas_intc_irqpin_config irqpin2_platform_data = { | |
147 | .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ | |
148 | }; | |
149 | ||
150 | static struct resource irqpin2_resources[] = { | |
151 | DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ | |
152 | DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */ | |
153 | DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */ | |
154 | DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */ | |
155 | DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */ | |
156 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */ | |
157 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */ | |
158 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */ | |
159 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */ | |
160 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */ | |
161 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */ | |
162 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */ | |
163 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */ | |
164 | }; | |
165 | ||
166 | static struct platform_device irqpin2_device = { | |
167 | .name = "renesas_intc_irqpin", | |
168 | .id = 2, | |
169 | .resource = irqpin2_resources, | |
170 | .num_resources = ARRAY_SIZE(irqpin2_resources), | |
171 | .dev = { | |
172 | .platform_data = &irqpin2_platform_data, | |
173 | }, | |
174 | }; | |
175 | ||
176 | static struct renesas_intc_irqpin_config irqpin3_platform_data = { | |
177 | .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ | |
178 | }; | |
179 | ||
180 | static struct resource irqpin3_resources[] = { | |
181 | DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */ | |
182 | DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ | |
183 | DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ | |
184 | DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ | |
185 | DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ | |
186 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */ | |
187 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */ | |
188 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */ | |
189 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */ | |
190 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */ | |
191 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */ | |
192 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */ | |
193 | DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */ | |
194 | }; | |
195 | ||
196 | static struct platform_device irqpin3_device = { | |
197 | .name = "renesas_intc_irqpin", | |
198 | .id = 3, | |
199 | .resource = irqpin3_resources, | |
200 | .num_resources = ARRAY_SIZE(irqpin3_resources), | |
201 | .dev = { | |
202 | .platform_data = &irqpin3_platform_data, | |
203 | }, | |
204 | }; | |
205 | ||
c9e06d8e LP |
206 | /* SCIF */ |
207 | #define R8A7740_SCIF(scif_type, index, baseaddr, irq) \ | |
208 | static struct plat_sci_port scif##index##_platform_data = { \ | |
209 | .type = scif_type, \ | |
c9e06d8e | 210 | .flags = UPF_BOOT_AUTOCONF, \ |
c9e06d8e LP |
211 | .scscr = SCSCR_RE | SCSCR_TE, \ |
212 | }; \ | |
213 | \ | |
8bf2f8c5 LP |
214 | static struct resource scif##index##_resources[] = { \ |
215 | DEFINE_RES_MEM(baseaddr, 0x100), \ | |
216 | DEFINE_RES_IRQ(irq), \ | |
217 | }; \ | |
218 | \ | |
c9e06d8e LP |
219 | static struct platform_device scif##index##_device = { \ |
220 | .name = "sh-sci", \ | |
221 | .id = index, \ | |
8bf2f8c5 LP |
222 | .resource = scif##index##_resources, \ |
223 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ | |
c9e06d8e LP |
224 | .dev = { \ |
225 | .platform_data = &scif##index##_platform_data, \ | |
226 | }, \ | |
227 | } | |
6c01ba44 | 228 | |
c9e06d8e LP |
229 | R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100)); |
230 | R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101)); | |
231 | R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102)); | |
232 | R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103)); | |
233 | R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104)); | |
234 | R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105)); | |
235 | R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106)); | |
236 | R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107)); | |
237 | R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108)); | |
6c01ba44 KM |
238 | |
239 | /* CMT */ | |
e0ad56a3 LP |
240 | static struct sh_timer_config cmt1_platform_data = { |
241 | .channels_mask = 0x3f, | |
6c01ba44 KM |
242 | }; |
243 | ||
e0ad56a3 LP |
244 | static struct resource cmt1_resources[] = { |
245 | DEFINE_RES_MEM(0xe6138000, 0x170), | |
246 | DEFINE_RES_IRQ(gic_spi(58)), | |
6c01ba44 KM |
247 | }; |
248 | ||
e0ad56a3 LP |
249 | static struct platform_device cmt1_device = { |
250 | .name = "sh-cmt-48", | |
251 | .id = 1, | |
6c01ba44 | 252 | .dev = { |
e0ad56a3 | 253 | .platform_data = &cmt1_platform_data, |
6c01ba44 | 254 | }, |
e0ad56a3 LP |
255 | .resource = cmt1_resources, |
256 | .num_resources = ARRAY_SIZE(cmt1_resources), | |
6c01ba44 KM |
257 | }; |
258 | ||
e67d7afc | 259 | /* TMU */ |
8ec72e46 LP |
260 | static struct sh_timer_config tmu0_platform_data = { |
261 | .channels_mask = 7, | |
e67d7afc KM |
262 | }; |
263 | ||
8ec72e46 LP |
264 | static struct resource tmu0_resources[] = { |
265 | DEFINE_RES_MEM(0xfff80000, 0x2c), | |
266 | DEFINE_RES_IRQ(gic_spi(198)), | |
267 | DEFINE_RES_IRQ(gic_spi(199)), | |
268 | DEFINE_RES_IRQ(gic_spi(200)), | |
e67d7afc KM |
269 | }; |
270 | ||
8ec72e46 LP |
271 | static struct platform_device tmu0_device = { |
272 | .name = "sh-tmu", | |
e67d7afc KM |
273 | .id = 0, |
274 | .dev = { | |
8ec72e46 | 275 | .platform_data = &tmu0_platform_data, |
e67d7afc | 276 | }, |
8ec72e46 LP |
277 | .resource = tmu0_resources, |
278 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
e67d7afc KM |
279 | }; |
280 | ||
f671e022 HE |
281 | /* IPMMUI (an IPMMU module for ICB/LMB) */ |
282 | static struct resource ipmmu_resources[] = { | |
283 | [0] = { | |
284 | .name = "IPMMUI", | |
285 | .start = 0xfe951000, | |
286 | .end = 0xfe9510ff, | |
287 | .flags = IORESOURCE_MEM, | |
288 | }, | |
289 | }; | |
290 | ||
291 | static const char * const ipmmu_dev_names[] = { | |
292 | "sh_mobile_lcdc_fb.0", | |
293 | "sh_mobile_lcdc_fb.1", | |
294 | "sh_mobile_ceu.0", | |
295 | }; | |
296 | ||
297 | static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { | |
298 | .dev_names = ipmmu_dev_names, | |
299 | .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), | |
300 | }; | |
301 | ||
302 | static struct platform_device ipmmu_device = { | |
303 | .name = "ipmmu", | |
304 | .id = -1, | |
305 | .dev = { | |
306 | .platform_data = &ipmmu_platform_data, | |
307 | }, | |
308 | .resource = ipmmu_resources, | |
309 | .num_resources = ARRAY_SIZE(ipmmu_resources), | |
310 | }; | |
311 | ||
c4fac6f2 | 312 | static struct platform_device *r8a7740_early_devices[] __initdata = { |
6c01ba44 KM |
313 | &scif0_device, |
314 | &scif1_device, | |
315 | &scif2_device, | |
316 | &scif3_device, | |
317 | &scif4_device, | |
318 | &scif5_device, | |
319 | &scif6_device, | |
320 | &scif7_device, | |
c9e06d8e | 321 | &scif8_device, |
744fdc8d BH |
322 | &irqpin0_device, |
323 | &irqpin1_device, | |
324 | &irqpin2_device, | |
325 | &irqpin3_device, | |
8ec72e46 | 326 | &tmu0_device, |
f671e022 | 327 | &ipmmu_device, |
1145eaab | 328 | &cmt1_device, |
6c01ba44 KM |
329 | }; |
330 | ||
643c3307 | 331 | /* DMA */ |
643c3307 KM |
332 | static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = { |
333 | { | |
cb76eb81 KM |
334 | .slave_id = SHDMA_SLAVE_SDHI0_TX, |
335 | .addr = 0xe6850030, | |
336 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
337 | .mid_rid = 0xc1, | |
338 | }, { | |
339 | .slave_id = SHDMA_SLAVE_SDHI0_RX, | |
340 | .addr = 0xe6850030, | |
341 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
342 | .mid_rid = 0xc2, | |
343 | }, { | |
344 | .slave_id = SHDMA_SLAVE_SDHI1_TX, | |
345 | .addr = 0xe6860030, | |
346 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
347 | .mid_rid = 0xc9, | |
348 | }, { | |
349 | .slave_id = SHDMA_SLAVE_SDHI1_RX, | |
350 | .addr = 0xe6860030, | |
351 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
352 | .mid_rid = 0xca, | |
353 | }, { | |
354 | .slave_id = SHDMA_SLAVE_SDHI2_TX, | |
355 | .addr = 0xe6870030, | |
356 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
357 | .mid_rid = 0xcd, | |
358 | }, { | |
359 | .slave_id = SHDMA_SLAVE_SDHI2_RX, | |
360 | .addr = 0xe6870030, | |
361 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
362 | .mid_rid = 0xce, | |
363 | }, { | |
643c3307 KM |
364 | .slave_id = SHDMA_SLAVE_FSIA_TX, |
365 | .addr = 0xfe1f0024, | |
366 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
367 | .mid_rid = 0xb1, | |
368 | }, { | |
369 | .slave_id = SHDMA_SLAVE_FSIA_RX, | |
370 | .addr = 0xfe1f0020, | |
371 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
372 | .mid_rid = 0xb2, | |
373 | }, { | |
374 | .slave_id = SHDMA_SLAVE_FSIB_TX, | |
375 | .addr = 0xfe1f0064, | |
376 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
377 | .mid_rid = 0xb5, | |
9a145624 GL |
378 | }, { |
379 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | |
380 | .addr = 0xe6bd0034, | |
381 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
382 | .mid_rid = 0xd1, | |
383 | }, { | |
384 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | |
385 | .addr = 0xe6bd0034, | |
386 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
387 | .mid_rid = 0xd2, | |
643c3307 KM |
388 | }, |
389 | }; | |
390 | ||
391 | #define DMA_CHANNEL(a, b, c) \ | |
392 | { \ | |
393 | .offset = a, \ | |
394 | .dmars = b, \ | |
395 | .dmars_bit = c, \ | |
396 | .chclr_offset = (0x220 - 0x20) + a \ | |
397 | } | |
398 | ||
399 | static const struct sh_dmae_channel r8a7740_dmae_channels[] = { | |
400 | DMA_CHANNEL(0x00, 0, 0), | |
401 | DMA_CHANNEL(0x10, 0, 8), | |
402 | DMA_CHANNEL(0x20, 4, 0), | |
403 | DMA_CHANNEL(0x30, 4, 8), | |
404 | DMA_CHANNEL(0x50, 8, 0), | |
405 | DMA_CHANNEL(0x60, 8, 8), | |
406 | }; | |
407 | ||
643c3307 KM |
408 | static struct sh_dmae_pdata dma_platform_data = { |
409 | .slave = r8a7740_dmae_slaves, | |
410 | .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves), | |
411 | .channel = r8a7740_dmae_channels, | |
412 | .channel_num = ARRAY_SIZE(r8a7740_dmae_channels), | |
d7de938f KM |
413 | .ts_low_shift = TS_LOW_SHIFT, |
414 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | |
415 | .ts_high_shift = TS_HI_SHIFT, | |
416 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | |
417 | .ts_shift = dma_ts_shift, | |
418 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | |
643c3307 KM |
419 | .dmaor_init = DMAOR_DME, |
420 | .chclr_present = 1, | |
421 | }; | |
422 | ||
423 | /* Resource order important! */ | |
424 | static struct resource r8a7740_dmae0_resources[] = { | |
425 | { | |
426 | /* Channel registers and DMAOR */ | |
427 | .start = 0xfe008020, | |
428 | .end = 0xfe00828f, | |
429 | .flags = IORESOURCE_MEM, | |
430 | }, | |
431 | { | |
432 | /* DMARSx */ | |
433 | .start = 0xfe009000, | |
434 | .end = 0xfe00900b, | |
435 | .flags = IORESOURCE_MEM, | |
436 | }, | |
437 | { | |
438 | .name = "error_irq", | |
0b7d7820 BH |
439 | .start = gic_spi(34), |
440 | .end = gic_spi(34), | |
643c3307 KM |
441 | .flags = IORESOURCE_IRQ, |
442 | }, | |
443 | { | |
444 | /* IRQ for channels 0-5 */ | |
0b7d7820 BH |
445 | .start = gic_spi(28), |
446 | .end = gic_spi(33), | |
643c3307 KM |
447 | .flags = IORESOURCE_IRQ, |
448 | }, | |
449 | }; | |
450 | ||
451 | /* Resource order important! */ | |
452 | static struct resource r8a7740_dmae1_resources[] = { | |
453 | { | |
454 | /* Channel registers and DMAOR */ | |
455 | .start = 0xfe018020, | |
456 | .end = 0xfe01828f, | |
457 | .flags = IORESOURCE_MEM, | |
458 | }, | |
459 | { | |
460 | /* DMARSx */ | |
461 | .start = 0xfe019000, | |
462 | .end = 0xfe01900b, | |
463 | .flags = IORESOURCE_MEM, | |
464 | }, | |
465 | { | |
466 | .name = "error_irq", | |
0b7d7820 BH |
467 | .start = gic_spi(41), |
468 | .end = gic_spi(41), | |
643c3307 KM |
469 | .flags = IORESOURCE_IRQ, |
470 | }, | |
471 | { | |
472 | /* IRQ for channels 0-5 */ | |
0b7d7820 BH |
473 | .start = gic_spi(35), |
474 | .end = gic_spi(40), | |
643c3307 KM |
475 | .flags = IORESOURCE_IRQ, |
476 | }, | |
477 | }; | |
478 | ||
479 | /* Resource order important! */ | |
480 | static struct resource r8a7740_dmae2_resources[] = { | |
481 | { | |
482 | /* Channel registers and DMAOR */ | |
483 | .start = 0xfe028020, | |
484 | .end = 0xfe02828f, | |
485 | .flags = IORESOURCE_MEM, | |
486 | }, | |
487 | { | |
488 | /* DMARSx */ | |
489 | .start = 0xfe029000, | |
490 | .end = 0xfe02900b, | |
491 | .flags = IORESOURCE_MEM, | |
492 | }, | |
493 | { | |
494 | .name = "error_irq", | |
0b7d7820 BH |
495 | .start = gic_spi(48), |
496 | .end = gic_spi(48), | |
643c3307 KM |
497 | .flags = IORESOURCE_IRQ, |
498 | }, | |
499 | { | |
500 | /* IRQ for channels 0-5 */ | |
0b7d7820 BH |
501 | .start = gic_spi(42), |
502 | .end = gic_spi(47), | |
643c3307 KM |
503 | .flags = IORESOURCE_IRQ, |
504 | }, | |
505 | }; | |
506 | ||
507 | static struct platform_device dma0_device = { | |
508 | .name = "sh-dma-engine", | |
509 | .id = 0, | |
510 | .resource = r8a7740_dmae0_resources, | |
511 | .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources), | |
512 | .dev = { | |
513 | .platform_data = &dma_platform_data, | |
514 | }, | |
515 | }; | |
516 | ||
517 | static struct platform_device dma1_device = { | |
518 | .name = "sh-dma-engine", | |
519 | .id = 1, | |
520 | .resource = r8a7740_dmae1_resources, | |
521 | .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources), | |
522 | .dev = { | |
523 | .platform_data = &dma_platform_data, | |
524 | }, | |
525 | }; | |
526 | ||
527 | static struct platform_device dma2_device = { | |
528 | .name = "sh-dma-engine", | |
529 | .id = 2, | |
530 | .resource = r8a7740_dmae2_resources, | |
531 | .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources), | |
532 | .dev = { | |
533 | .platform_data = &dma_platform_data, | |
534 | }, | |
535 | }; | |
536 | ||
dbf382e5 | 537 | /* USB-DMAC */ |
dbf382e5 KM |
538 | static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = { |
539 | { | |
540 | .offset = 0, | |
541 | }, { | |
542 | .offset = 0x20, | |
543 | }, | |
544 | }; | |
545 | ||
dbf382e5 KM |
546 | static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = { |
547 | { | |
548 | .slave_id = SHDMA_SLAVE_USBHS_TX, | |
549 | .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), | |
550 | }, { | |
551 | .slave_id = SHDMA_SLAVE_USBHS_RX, | |
552 | .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE), | |
553 | }, | |
554 | }; | |
555 | ||
556 | static struct sh_dmae_pdata usb_dma_platform_data = { | |
557 | .slave = r8a7740_usb_dma_slaves, | |
558 | .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves), | |
559 | .channel = r8a7740_usb_dma_channels, | |
560 | .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels), | |
d7de938f KM |
561 | .ts_low_shift = USBTS_LOW_SHIFT, |
562 | .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT, | |
563 | .ts_high_shift = USBTS_HI_SHIFT, | |
564 | .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT, | |
dbf382e5 KM |
565 | .ts_shift = dma_usbts_shift, |
566 | .ts_shift_num = ARRAY_SIZE(dma_usbts_shift), | |
567 | .dmaor_init = DMAOR_DME, | |
568 | .chcr_offset = 0x14, | |
569 | .chcr_ie_bit = 1 << 5, | |
570 | .dmaor_is_32bit = 1, | |
571 | .needs_tend_set = 1, | |
572 | .no_dmars = 1, | |
573 | .slave_only = 1, | |
574 | }; | |
575 | ||
576 | static struct resource r8a7740_usb_dma_resources[] = { | |
577 | { | |
578 | /* Channel registers and DMAOR */ | |
579 | .start = 0xe68a0020, | |
580 | .end = 0xe68a0064 - 1, | |
581 | .flags = IORESOURCE_MEM, | |
582 | }, | |
583 | { | |
584 | /* VCR/SWR/DMICR */ | |
585 | .start = 0xe68a0000, | |
586 | .end = 0xe68a0014 - 1, | |
587 | .flags = IORESOURCE_MEM, | |
588 | }, | |
589 | { | |
590 | /* IRQ for channels */ | |
0b7d7820 BH |
591 | .start = gic_spi(49), |
592 | .end = gic_spi(49), | |
dbf382e5 KM |
593 | .flags = IORESOURCE_IRQ, |
594 | }, | |
595 | }; | |
596 | ||
597 | static struct platform_device usb_dma_device = { | |
598 | .name = "sh-dma-engine", | |
599 | .id = 3, | |
600 | .resource = r8a7740_usb_dma_resources, | |
601 | .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources), | |
602 | .dev = { | |
603 | .platform_data = &usb_dma_platform_data, | |
604 | }, | |
605 | }; | |
606 | ||
6831f3a9 KM |
607 | /* I2C */ |
608 | static struct resource i2c0_resources[] = { | |
609 | [0] = { | |
610 | .name = "IIC0", | |
611 | .start = 0xfff20000, | |
612 | .end = 0xfff20425 - 1, | |
613 | .flags = IORESOURCE_MEM, | |
614 | }, | |
615 | [1] = { | |
0b7d7820 BH |
616 | .start = gic_spi(201), |
617 | .end = gic_spi(204), | |
6831f3a9 KM |
618 | .flags = IORESOURCE_IRQ, |
619 | }, | |
620 | }; | |
621 | ||
622 | static struct resource i2c1_resources[] = { | |
623 | [0] = { | |
624 | .name = "IIC1", | |
625 | .start = 0xe6c20000, | |
626 | .end = 0xe6c20425 - 1, | |
627 | .flags = IORESOURCE_MEM, | |
628 | }, | |
629 | [1] = { | |
0b7d7820 BH |
630 | .start = gic_spi(70), /* IIC1_ALI1 */ |
631 | .end = gic_spi(73), /* IIC1_DTEI1 */ | |
6831f3a9 KM |
632 | .flags = IORESOURCE_IRQ, |
633 | }, | |
634 | }; | |
635 | ||
636 | static struct platform_device i2c0_device = { | |
637 | .name = "i2c-sh_mobile", | |
638 | .id = 0, | |
639 | .resource = i2c0_resources, | |
640 | .num_resources = ARRAY_SIZE(i2c0_resources), | |
641 | }; | |
642 | ||
643 | static struct platform_device i2c1_device = { | |
644 | .name = "i2c-sh_mobile", | |
645 | .id = 1, | |
646 | .resource = i2c1_resources, | |
647 | .num_resources = ARRAY_SIZE(i2c1_resources), | |
648 | }; | |
649 | ||
86bc52ef NI |
650 | static struct resource pmu_resources[] = { |
651 | [0] = { | |
0b7d7820 BH |
652 | .start = gic_spi(83), |
653 | .end = gic_spi(83), | |
86bc52ef NI |
654 | .flags = IORESOURCE_IRQ, |
655 | }, | |
656 | }; | |
657 | ||
658 | static struct platform_device pmu_device = { | |
659 | .name = "arm-pmu", | |
660 | .id = -1, | |
661 | .num_resources = ARRAY_SIZE(pmu_resources), | |
662 | .resource = pmu_resources, | |
663 | }; | |
664 | ||
6831f3a9 KM |
665 | static struct platform_device *r8a7740_late_devices[] __initdata = { |
666 | &i2c0_device, | |
667 | &i2c1_device, | |
643c3307 KM |
668 | &dma0_device, |
669 | &dma1_device, | |
670 | &dma2_device, | |
dbf382e5 | 671 | &usb_dma_device, |
86bc52ef | 672 | &pmu_device, |
6831f3a9 KM |
673 | }; |
674 | ||
d49679e5 KM |
675 | /* |
676 | * r8a7740 chip has lasting errata on MERAM buffer. | |
677 | * this is work-around for it. | |
678 | * see | |
679 | * "Media RAM (MERAM)" on r8a7740 documentation | |
680 | */ | |
681 | #define MEBUFCNTR 0xFE950098 | |
bb6c3d58 | 682 | void __init r8a7740_meram_workaround(void) |
d49679e5 KM |
683 | { |
684 | void __iomem *reg; | |
685 | ||
686 | reg = ioremap_nocache(MEBUFCNTR, 4); | |
687 | if (reg) { | |
688 | iowrite32(0x01600164, reg); | |
689 | iounmap(reg); | |
690 | } | |
691 | } | |
692 | ||
6831f3a9 KM |
693 | #define ICCR 0x0004 |
694 | #define ICSTART 0x0070 | |
695 | ||
696 | #define i2c_read(reg, offset) ioread8(reg + offset) | |
697 | #define i2c_write(reg, offset, data) iowrite8(data, reg + offset) | |
698 | ||
699 | /* | |
700 | * r8a7740 chip has lasting errata on I2C I/O pad reset. | |
701 | * this is work-around for it. | |
702 | */ | |
703 | static void r8a7740_i2c_workaround(struct platform_device *pdev) | |
704 | { | |
705 | struct resource *res; | |
706 | void __iomem *reg; | |
707 | ||
708 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
709 | if (unlikely(!res)) { | |
710 | pr_err("r8a7740 i2c workaround fail (cannot find resource)\n"); | |
711 | return; | |
712 | } | |
713 | ||
714 | reg = ioremap(res->start, resource_size(res)); | |
715 | if (unlikely(!reg)) { | |
716 | pr_err("r8a7740 i2c workaround fail (cannot map IO)\n"); | |
717 | return; | |
718 | } | |
719 | ||
720 | i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80); | |
721 | i2c_read(reg, ICCR); /* dummy read */ | |
722 | ||
723 | i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10); | |
724 | i2c_read(reg, ICSTART); /* dummy read */ | |
725 | ||
4228716c | 726 | udelay(10); |
6831f3a9 KM |
727 | |
728 | i2c_write(reg, ICCR, 0x01); | |
6831f3a9 | 729 | i2c_write(reg, ICSTART, 0x00); |
4228716c KM |
730 | |
731 | udelay(10); | |
6831f3a9 KM |
732 | |
733 | i2c_write(reg, ICCR, 0x10); | |
4228716c | 734 | udelay(10); |
6831f3a9 | 735 | i2c_write(reg, ICCR, 0x00); |
4228716c | 736 | udelay(10); |
6831f3a9 | 737 | i2c_write(reg, ICCR, 0x10); |
4228716c | 738 | udelay(10); |
6831f3a9 KM |
739 | |
740 | iounmap(reg); | |
741 | } | |
742 | ||
6c01ba44 KM |
743 | void __init r8a7740_add_standard_devices(void) |
744 | { | |
c839f93b | 745 | static struct pm_domain_device domain_devices[] __initdata = { |
1618a677 GU |
746 | { "A4R", &tmu0_device }, |
747 | { "A4R", &i2c0_device }, | |
3b358cb8 GU |
748 | { "A4S", &irqpin0_device }, |
749 | { "A4S", &irqpin1_device }, | |
750 | { "A4S", &irqpin2_device }, | |
751 | { "A4S", &irqpin3_device }, | |
c839f93b GU |
752 | { "A3SP", &scif0_device }, |
753 | { "A3SP", &scif1_device }, | |
754 | { "A3SP", &scif2_device }, | |
755 | { "A3SP", &scif3_device }, | |
756 | { "A3SP", &scif4_device }, | |
757 | { "A3SP", &scif5_device }, | |
758 | { "A3SP", &scif6_device }, | |
759 | { "A3SP", &scif7_device }, | |
760 | { "A3SP", &scif8_device }, | |
761 | { "A3SP", &i2c1_device }, | |
80f643b3 GU |
762 | { "A3SP", &ipmmu_device }, |
763 | { "A3SP", &dma0_device }, | |
764 | { "A3SP", &dma1_device }, | |
765 | { "A3SP", &dma2_device }, | |
766 | { "A3SP", &usb_dma_device }, | |
c839f93b GU |
767 | }; |
768 | ||
6831f3a9 KM |
769 | /* I2C work-around */ |
770 | r8a7740_i2c_workaround(&i2c0_device); | |
771 | r8a7740_i2c_workaround(&i2c1_device); | |
772 | ||
7b567407 | 773 | r8a7740_init_pm_domains(); |
8459293c KM |
774 | |
775 | /* add devices */ | |
6c01ba44 KM |
776 | platform_add_devices(r8a7740_early_devices, |
777 | ARRAY_SIZE(r8a7740_early_devices)); | |
6831f3a9 KM |
778 | platform_add_devices(r8a7740_late_devices, |
779 | ARRAY_SIZE(r8a7740_late_devices)); | |
802a5639 KM |
780 | |
781 | /* add devices to PM domain */ | |
c839f93b GU |
782 | rmobile_add_devices_to_domains(domain_devices, |
783 | ARRAY_SIZE(domain_devices)); | |
6c01ba44 KM |
784 | } |
785 | ||
786 | void __init r8a7740_add_early_devices(void) | |
787 | { | |
788 | early_platform_add_devices(r8a7740_early_devices, | |
789 | ARRAY_SIZE(r8a7740_early_devices)); | |
d3ab7221 MD |
790 | |
791 | /* setup early console here as well */ | |
792 | shmobile_setup_console(); | |
6c01ba44 | 793 | } |
755d57b2 MD |
794 | |
795 | #ifdef CONFIG_USE_OF | |
796 | ||
70e3f3d4 KM |
797 | void __init r8a7740_init_irq_of(void) |
798 | { | |
799 | void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); | |
800 | void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); | |
801 | void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); | |
802 | ||
803 | irqchip_init(); | |
804 | ||
805 | /* route signals to GIC */ | |
806 | iowrite32(0x0, pfc_inta_ctrl); | |
807 | ||
808 | /* | |
809 | * To mask the shared interrupt to SPI 149 we must ensure to set | |
810 | * PRIO *and* MASK. Else we run into IRQ floods when registering | |
811 | * the intc_irqpin devices | |
812 | */ | |
813 | iowrite32(0x0, intc_prio_base + 0x0); | |
814 | iowrite32(0x0, intc_prio_base + 0x4); | |
815 | iowrite32(0x0, intc_prio_base + 0x8); | |
816 | iowrite32(0x0, intc_prio_base + 0xc); | |
817 | iowrite8(0xff, intc_msk_base + 0x0); | |
818 | iowrite8(0xff, intc_msk_base + 0x4); | |
819 | iowrite8(0xff, intc_msk_base + 0x8); | |
820 | iowrite8(0xff, intc_msk_base + 0xc); | |
821 | ||
822 | iounmap(intc_prio_base); | |
823 | iounmap(intc_msk_base); | |
824 | iounmap(pfc_inta_ctrl); | |
825 | } | |
826 | ||
744fdc8d BH |
827 | static void __init r8a7740_generic_init(void) |
828 | { | |
c41215b7 MD |
829 | r8a7740_meram_workaround(); |
830 | ||
831 | #ifdef CONFIG_CACHE_L2X0 | |
832 | /* Shared attribute override enable, 32K*8way */ | |
833 | l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff); | |
834 | #endif | |
43330674 | 835 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
744fdc8d BH |
836 | } |
837 | ||
1174c712 MD |
838 | #define RESCNT2 IOMEM(0xe6188020) |
839 | static void r8a7740_restart(enum reboot_mode mode, const char *cmd) | |
840 | { | |
841 | /* Do soft power on reset */ | |
842 | writel(1 << 31, RESCNT2); | |
744fdc8d BH |
843 | } |
844 | ||
755d57b2 MD |
845 | static const char *r8a7740_boards_compat_dt[] __initdata = { |
846 | "renesas,r8a7740", | |
847 | NULL, | |
848 | }; | |
849 | ||
a41acc4a | 850 | DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") |
755d57b2 | 851 | .map_io = r8a7740_map_io, |
a0c1fb0c | 852 | .init_early = shmobile_init_delay, |
744fdc8d BH |
853 | .init_irq = r8a7740_init_irq_of, |
854 | .init_machine = r8a7740_generic_init, | |
34b9fa40 | 855 | .init_late = shmobile_init_late, |
755d57b2 | 856 | .dt_compat = r8a7740_boards_compat_dt, |
1174c712 | 857 | .restart = r8a7740_restart, |
755d57b2 MD |
858 | MACHINE_END |
859 | ||
860 | #endif /* CONFIG_USE_OF */ |