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sh-pfc: Add shx3 pinmux support
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7740.c
CommitLineData
6c01ba44
KM		 1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
6831f3a9 20#include <linux/delay.h>
3841e6f5 21#include <linux/dma-mapping.h>
6c01ba44
KM		 22#include <linux/kernel.h>
23#include <linux/init.h>
6831f3a9 24#include <linux/io.h>
6c01ba44 25#include <linux/platform_device.h>
755d57b2 26#include <linux/of_platform.h>
6c01ba44 27#include <linux/serial_sci.h>
643c3307 28#include <linux/sh_dma.h>
6c01ba44 29#include <linux/sh_timer.h>
643c3307 30#include <linux/dma-mapping.h>
d7de938f 31#include <mach/dma-register.h>
6c01ba44 32#include <mach/r8a7740.h>
8459293c 33#include <mach/pm-rmobile.h>
d3ab7221 34#include <mach/common.h>
250a2723 35#include <mach/irqs.h>
6c01ba44 36#include <asm/mach-types.h>
d3ab7221 37#include <asm/mach/map.h>
6c01ba44 38#include <asm/mach/arch.h>
23e5bc03 39#include <asm/mach/time.h>
6c01ba44 40
d3ab7221
MD		 41static struct map_desc r8a7740_io_desc[] __initdata = {
42 /*
43 * for CPGA/INTC/PFC
44 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
45 */
46 {
47 .virtual = 0xe6000000,
48 .pfn = __phys_to_pfn(0xe6000000),
49 .length = 160 << 20,
50 .type = MT_DEVICE_NONSHARED
51 },
52#ifdef CONFIG_CACHE_L2X0
53 /*
54 * for l2x0_init()
55 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
56 */
57 {
58 .virtual = 0xf0002000,
59 .pfn = __phys_to_pfn(0xf0100000),
60 .length = PAGE_SIZE,
61 .type = MT_DEVICE_NONSHARED
62 },
63#endif
64};
65
66void __init r8a7740_map_io(void)
67{
68 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
69}
70
6c01ba44
KM		 71/* SCIFA0 */
72static struct plat_sci_port scif0_platform_data = {
73 .mapbase = 0xe6c40000,
74 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_RE | SCSCR_TE,
76 .scbrr_algo_id = SCBRR_ALGO_4,
77 .type = PORT_SCIFA,
215d6cc9 78 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
6c01ba44
KM		 79};
80
81static struct platform_device scif0_device = {
82 .name = "sh-sci",
83 .id = 0,
84 .dev = {
85 .platform_data = &scif0_platform_data,
86 },
87};
88
89/* SCIFA1 */
90static struct plat_sci_port scif1_platform_data = {
91 .mapbase = 0xe6c50000,
92 .flags = UPF_BOOT_AUTOCONF,
93 .scscr = SCSCR_RE | SCSCR_TE,
94 .scbrr_algo_id = SCBRR_ALGO_4,
95 .type = PORT_SCIFA,
215d6cc9 96 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
6c01ba44
KM		 97};
98
99static struct platform_device scif1_device = {
100 .name = "sh-sci",
101 .id = 1,
102 .dev = {
103 .platform_data = &scif1_platform_data,
104 },
105};
106
107/* SCIFA2 */
108static struct plat_sci_port scif2_platform_data = {
109 .mapbase = 0xe6c60000,
110 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE,
112 .scbrr_algo_id = SCBRR_ALGO_4,
113 .type = PORT_SCIFA,
215d6cc9 114 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
6c01ba44
KM		 115};
116
117static struct platform_device scif2_device = {
118 .name = "sh-sci",
119 .id = 2,
120 .dev = {
121 .platform_data = &scif2_platform_data,
122 },
123};
124
125/* SCIFA3 */
126static struct plat_sci_port scif3_platform_data = {
127 .mapbase = 0xe6c70000,
128 .flags = UPF_BOOT_AUTOCONF,
129 .scscr = SCSCR_RE | SCSCR_TE,
130 .scbrr_algo_id = SCBRR_ALGO_4,
131 .type = PORT_SCIFA,
215d6cc9 132 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
6c01ba44
KM		 133};
134
135static struct platform_device scif3_device = {
136 .name = "sh-sci",
137 .id = 3,
138 .dev = {
139 .platform_data = &scif3_platform_data,
140 },
141};
142
143/* SCIFA4 */
144static struct plat_sci_port scif4_platform_data = {
145 .mapbase = 0xe6c80000,
146 .flags = UPF_BOOT_AUTOCONF,
147 .scscr = SCSCR_RE | SCSCR_TE,
148 .scbrr_algo_id = SCBRR_ALGO_4,
149 .type = PORT_SCIFA,
215d6cc9 150 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
6c01ba44
KM		 151};
152
153static struct platform_device scif4_device = {
154 .name = "sh-sci",
155 .id = 4,
156 .dev = {
157 .platform_data = &scif4_platform_data,
158 },
159};
160
161/* SCIFA5 */
162static struct plat_sci_port scif5_platform_data = {
163 .mapbase = 0xe6cb0000,
164 .flags = UPF_BOOT_AUTOCONF,
165 .scscr = SCSCR_RE | SCSCR_TE,
166 .scbrr_algo_id = SCBRR_ALGO_4,
167 .type = PORT_SCIFA,
215d6cc9 168 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
6c01ba44
KM		 169};
170
171static struct platform_device scif5_device = {
172 .name = "sh-sci",
173 .id = 5,
174 .dev = {
175 .platform_data = &scif5_platform_data,
176 },
177};
178
179/* SCIFA6 */
180static struct plat_sci_port scif6_platform_data = {
181 .mapbase = 0xe6cc0000,
182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE,
184 .scbrr_algo_id = SCBRR_ALGO_4,
185 .type = PORT_SCIFA,
215d6cc9 186 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
6c01ba44
KM		 187};
188
189static struct platform_device scif6_device = {
190 .name = "sh-sci",
191 .id = 6,
192 .dev = {
193 .platform_data = &scif6_platform_data,
194 },
195};
196
197/* SCIFA7 */
198static struct plat_sci_port scif7_platform_data = {
199 .mapbase = 0xe6cd0000,
200 .flags = UPF_BOOT_AUTOCONF,
201 .scscr = SCSCR_RE | SCSCR_TE,
202 .scbrr_algo_id = SCBRR_ALGO_4,
203 .type = PORT_SCIFA,
215d6cc9 204 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
6c01ba44
KM		 205};
206
207static struct platform_device scif7_device = {
208 .name = "sh-sci",
209 .id = 7,
210 .dev = {
211 .platform_data = &scif7_platform_data,
212 },
213};
214
215/* SCIFB */
216static struct plat_sci_port scifb_platform_data = {
217 .mapbase = 0xe6c30000,
218 .flags = UPF_BOOT_AUTOCONF,
219 .scscr = SCSCR_RE | SCSCR_TE,
220 .scbrr_algo_id = SCBRR_ALGO_4,
221 .type = PORT_SCIFB,
215d6cc9 222 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
6c01ba44
KM		 223};
224
225static struct platform_device scifb_device = {
226 .name = "sh-sci",
227 .id = 8,
228 .dev = {
229 .platform_data = &scifb_platform_data,
230 },
231};
232
233/* CMT */
234static struct sh_timer_config cmt10_platform_data = {
235 .name = "CMT10",
236 .channel_offset = 0x10,
237 .timer_bit = 0,
238 .clockevent_rating = 125,
239 .clocksource_rating = 125,
240};
241
242static struct resource cmt10_resources[] = {
243 [0] = {
244 .name = "CMT10",
245 .start = 0xe6138010,
246 .end = 0xe613801b,
247 .flags = IORESOURCE_MEM,
248 },
249 [1] = {
215d6cc9 250 .start = evt2irq(0x0b00),
6c01ba44
KM		 251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255static struct platform_device cmt10_device = {
256 .name = "sh_cmt",
257 .id = 10,
258 .dev = {
259 .platform_data = &cmt10_platform_data,
260 },
261 .resource = cmt10_resources,
262 .num_resources = ARRAY_SIZE(cmt10_resources),
263};
264
265static struct platform_device *r8a7740_early_devices[] __initdata = {
266 &scif0_device,
267 &scif1_device,
268 &scif2_device,
269 &scif3_device,
270 &scif4_device,
271 &scif5_device,
272 &scif6_device,
273 &scif7_device,
274 &scifb_device,
275 &cmt10_device,
276};
277
643c3307 278/* DMA */
643c3307
KM		 279static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
280 {
cb76eb81
KM		 281 .slave_id = SHDMA_SLAVE_SDHI0_TX,
282 .addr = 0xe6850030,
283 .chcr = CHCR_TX(XMIT_SZ_16BIT),
284 .mid_rid = 0xc1,
285 }, {
286 .slave_id = SHDMA_SLAVE_SDHI0_RX,
287 .addr = 0xe6850030,
288 .chcr = CHCR_RX(XMIT_SZ_16BIT),
289 .mid_rid = 0xc2,
290 }, {
291 .slave_id = SHDMA_SLAVE_SDHI1_TX,
292 .addr = 0xe6860030,
293 .chcr = CHCR_TX(XMIT_SZ_16BIT),
294 .mid_rid = 0xc9,
295 }, {
296 .slave_id = SHDMA_SLAVE_SDHI1_RX,
297 .addr = 0xe6860030,
298 .chcr = CHCR_RX(XMIT_SZ_16BIT),
299 .mid_rid = 0xca,
300 }, {
301 .slave_id = SHDMA_SLAVE_SDHI2_TX,
302 .addr = 0xe6870030,
303 .chcr = CHCR_TX(XMIT_SZ_16BIT),
304 .mid_rid = 0xcd,
305 }, {
306 .slave_id = SHDMA_SLAVE_SDHI2_RX,
307 .addr = 0xe6870030,
308 .chcr = CHCR_RX(XMIT_SZ_16BIT),
309 .mid_rid = 0xce,
310 }, {
643c3307
KM		 311 .slave_id = SHDMA_SLAVE_FSIA_TX,
312 .addr = 0xfe1f0024,
313 .chcr = CHCR_TX(XMIT_SZ_32BIT),
314 .mid_rid = 0xb1,
315 }, {
316 .slave_id = SHDMA_SLAVE_FSIA_RX,
317 .addr = 0xfe1f0020,
318 .chcr = CHCR_RX(XMIT_SZ_32BIT),
319 .mid_rid = 0xb2,
320 }, {
321 .slave_id = SHDMA_SLAVE_FSIB_TX,
322 .addr = 0xfe1f0064,
323 .chcr = CHCR_TX(XMIT_SZ_32BIT),
324 .mid_rid = 0xb5,
325 },
326};
327
328#define DMA_CHANNEL(a, b, c) \
329{ \
330 .offset = a, \
331 .dmars = b, \
332 .dmars_bit = c, \
333 .chclr_offset = (0x220 - 0x20) + a \
334}
335
336static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
337 DMA_CHANNEL(0x00, 0, 0),
338 DMA_CHANNEL(0x10, 0, 8),
339 DMA_CHANNEL(0x20, 4, 0),
340 DMA_CHANNEL(0x30, 4, 8),
341 DMA_CHANNEL(0x50, 8, 0),
342 DMA_CHANNEL(0x60, 8, 8),
343};
344
643c3307
KM		 345static struct sh_dmae_pdata dma_platform_data = {
346 .slave = r8a7740_dmae_slaves,
347 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
348 .channel = r8a7740_dmae_channels,
349 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
d7de938f
KM		 350 .ts_low_shift = TS_LOW_SHIFT,
351 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
352 .ts_high_shift = TS_HI_SHIFT,
353 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
354 .ts_shift = dma_ts_shift,
355 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
643c3307
KM		 356 .dmaor_init = DMAOR_DME,
357 .chclr_present = 1,
358};
359
360/* Resource order important! */
361static struct resource r8a7740_dmae0_resources[] = {
362 {
363 /* Channel registers and DMAOR */
364 .start = 0xfe008020,
365 .end = 0xfe00828f,
366 .flags = IORESOURCE_MEM,
367 },
368 {
369 /* DMARSx */
370 .start = 0xfe009000,
371 .end = 0xfe00900b,
372 .flags = IORESOURCE_MEM,
373 },
374 {
375 .name = "error_irq",
376 .start = evt2irq(0x20c0),
377 .end = evt2irq(0x20c0),
378 .flags = IORESOURCE_IRQ,
379 },
380 {
381 /* IRQ for channels 0-5 */
382 .start = evt2irq(0x2000),
383 .end = evt2irq(0x20a0),
384 .flags = IORESOURCE_IRQ,
385 },
386};
387
388/* Resource order important! */
389static struct resource r8a7740_dmae1_resources[] = {
390 {
391 /* Channel registers and DMAOR */
392 .start = 0xfe018020,
393 .end = 0xfe01828f,
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 /* DMARSx */
398 .start = 0xfe019000,
399 .end = 0xfe01900b,
400 .flags = IORESOURCE_MEM,
401 },
402 {
403 .name = "error_irq",
404 .start = evt2irq(0x21c0),
405 .end = evt2irq(0x21c0),
406 .flags = IORESOURCE_IRQ,
407 },
408 {
409 /* IRQ for channels 0-5 */
410 .start = evt2irq(0x2100),
411 .end = evt2irq(0x21a0),
412 .flags = IORESOURCE_IRQ,
413 },
414};
415
416/* Resource order important! */
417static struct resource r8a7740_dmae2_resources[] = {
418 {
419 /* Channel registers and DMAOR */
420 .start = 0xfe028020,
421 .end = 0xfe02828f,
422 .flags = IORESOURCE_MEM,
423 },
424 {
425 /* DMARSx */
426 .start = 0xfe029000,
427 .end = 0xfe02900b,
428 .flags = IORESOURCE_MEM,
429 },
430 {
431 .name = "error_irq",
432 .start = evt2irq(0x22c0),
433 .end = evt2irq(0x22c0),
434 .flags = IORESOURCE_IRQ,
435 },
436 {
437 /* IRQ for channels 0-5 */
438 .start = evt2irq(0x2200),
439 .end = evt2irq(0x22a0),
440 .flags = IORESOURCE_IRQ,
441 },
442};
443
444static struct platform_device dma0_device = {
445 .name = "sh-dma-engine",
446 .id = 0,
447 .resource = r8a7740_dmae0_resources,
448 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
449 .dev = {
450 .platform_data = &dma_platform_data,
451 },
452};
453
454static struct platform_device dma1_device = {
455 .name = "sh-dma-engine",
456 .id = 1,
457 .resource = r8a7740_dmae1_resources,
458 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
459 .dev = {
460 .platform_data = &dma_platform_data,
461 },
462};
463
464static struct platform_device dma2_device = {
465 .name = "sh-dma-engine",
466 .id = 2,
467 .resource = r8a7740_dmae2_resources,
468 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
469 .dev = {
470 .platform_data = &dma_platform_data,
471 },
472};
473
dbf382e5 474/* USB-DMAC */
dbf382e5
KM		 475static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
476 {
477 .offset = 0,
478 }, {
479 .offset = 0x20,
480 },
481};
482
dbf382e5
KM		 483static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
484 {
485 .slave_id = SHDMA_SLAVE_USBHS_TX,
486 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
487 }, {
488 .slave_id = SHDMA_SLAVE_USBHS_RX,
489 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
490 },
491};
492
493static struct sh_dmae_pdata usb_dma_platform_data = {
494 .slave = r8a7740_usb_dma_slaves,
495 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
496 .channel = r8a7740_usb_dma_channels,
497 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
d7de938f
KM		 498 .ts_low_shift = USBTS_LOW_SHIFT,
499 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
500 .ts_high_shift = USBTS_HI_SHIFT,
501 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
dbf382e5
KM		 502 .ts_shift = dma_usbts_shift,
503 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
504 .dmaor_init = DMAOR_DME,
505 .chcr_offset = 0x14,
506 .chcr_ie_bit = 1 << 5,
507 .dmaor_is_32bit = 1,
508 .needs_tend_set = 1,
509 .no_dmars = 1,
510 .slave_only = 1,
511};
512
513static struct resource r8a7740_usb_dma_resources[] = {
514 {
515 /* Channel registers and DMAOR */
516 .start = 0xe68a0020,
517 .end = 0xe68a0064 - 1,
518 .flags = IORESOURCE_MEM,
519 },
520 {
521 /* VCR/SWR/DMICR */
522 .start = 0xe68a0000,
523 .end = 0xe68a0014 - 1,
524 .flags = IORESOURCE_MEM,
525 },
526 {
527 /* IRQ for channels */
528 .start = evt2irq(0x0a00),
529 .end = evt2irq(0x0a00),
530 .flags = IORESOURCE_IRQ,
531 },
532};
533
534static struct platform_device usb_dma_device = {
535 .name = "sh-dma-engine",
536 .id = 3,
537 .resource = r8a7740_usb_dma_resources,
538 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
539 .dev = {
540 .platform_data = &usb_dma_platform_data,
541 },
542};
543
6831f3a9
KM		 544/* I2C */
545static struct resource i2c0_resources[] = {
546 [0] = {
547 .name = "IIC0",
548 .start = 0xfff20000,
549 .end = 0xfff20425 - 1,
550 .flags = IORESOURCE_MEM,
551 },
552 [1] = {
215d6cc9
KM		 553 .start = intcs_evt2irq(0xe00),
554 .end = intcs_evt2irq(0xe60),
6831f3a9
KM		 555 .flags = IORESOURCE_IRQ,
556 },
557};
558
559static struct resource i2c1_resources[] = {
560 [0] = {
561 .name = "IIC1",
562 .start = 0xe6c20000,
563 .end = 0xe6c20425 - 1,
564 .flags = IORESOURCE_MEM,
565 },
566 [1] = {
215d6cc9
KM		 567 .start = evt2irq(0x780), /* IIC1_ALI1 */
568 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
6831f3a9
KM		 569 .flags = IORESOURCE_IRQ,
570 },
571};
572
573static struct platform_device i2c0_device = {
574 .name = "i2c-sh_mobile",
575 .id = 0,
576 .resource = i2c0_resources,
577 .num_resources = ARRAY_SIZE(i2c0_resources),
578};
579
580static struct platform_device i2c1_device = {
581 .name = "i2c-sh_mobile",
582 .id = 1,
583 .resource = i2c1_resources,
584 .num_resources = ARRAY_SIZE(i2c1_resources),
585};
586
86bc52ef
NI		 587static struct resource pmu_resources[] = {
588 [0] = {
589 .start = evt2irq(0x19a0),
590 .end = evt2irq(0x19a0),
591 .flags = IORESOURCE_IRQ,
592 },
593};
594
595static struct platform_device pmu_device = {
596 .name = "arm-pmu",
597 .id = -1,
598 .num_resources = ARRAY_SIZE(pmu_resources),
599 .resource = pmu_resources,
600};
601
6831f3a9
KM		 602static struct platform_device *r8a7740_late_devices[] __initdata = {
603 &i2c0_device,
604 &i2c1_device,
643c3307
KM		 605 &dma0_device,
606 &dma1_device,
607 &dma2_device,
dbf382e5 608 &usb_dma_device,
86bc52ef 609 &pmu_device,
6831f3a9
KM		 610};
611
d49679e5
KM		 612/*
613 * r8a7740 chip has lasting errata on MERAM buffer.
614 * this is work-around for it.
615 * see
616 * "Media RAM (MERAM)" on r8a7740 documentation
617 */
618#define MEBUFCNTR 0xFE950098
619void r8a7740_meram_workaround(void)
620{
621 void __iomem *reg;
622
623 reg = ioremap_nocache(MEBUFCNTR, 4);
624 if (reg) {
625 iowrite32(0x01600164, reg);
626 iounmap(reg);
627 }
628}
629
6831f3a9
KM		 630#define ICCR 0x0004
631#define ICSTART 0x0070
632
633#define i2c_read(reg, offset) ioread8(reg + offset)
634#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
635
636/*
637 * r8a7740 chip has lasting errata on I2C I/O pad reset.
638 * this is work-around for it.
639 */
640static void r8a7740_i2c_workaround(struct platform_device *pdev)
641{
642 struct resource *res;
643 void __iomem *reg;
644
645 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
646 if (unlikely(!res)) {
647 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
648 return;
649 }
650
651 reg = ioremap(res->start, resource_size(res));
652 if (unlikely(!reg)) {
653 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
654 return;
655 }
656
657 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
658 i2c_read(reg, ICCR); /* dummy read */
659
660 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
661 i2c_read(reg, ICSTART); /* dummy read */
662
4228716c 663 udelay(10);
6831f3a9
KM		 664
665 i2c_write(reg, ICCR, 0x01);
6831f3a9 666 i2c_write(reg, ICSTART, 0x00);
4228716c
KM		 667
668 udelay(10);
6831f3a9
KM		 669
670 i2c_write(reg, ICCR, 0x10);
4228716c 671 udelay(10);
6831f3a9 672 i2c_write(reg, ICCR, 0x00);
4228716c 673 udelay(10);
6831f3a9 674 i2c_write(reg, ICCR, 0x10);
4228716c 675 udelay(10);
6831f3a9
KM		 676
677 iounmap(reg);
678}
679
6c01ba44
KM		 680void __init r8a7740_add_standard_devices(void)
681{
6831f3a9
KM		 682 /* I2C work-around */
683 r8a7740_i2c_workaround(&i2c0_device);
684 r8a7740_i2c_workaround(&i2c1_device);
685
7b567407 686 r8a7740_init_pm_domains();
8459293c
KM		 687
688 /* add devices */
6c01ba44
KM		 689 platform_add_devices(r8a7740_early_devices,
690 ARRAY_SIZE(r8a7740_early_devices));
6831f3a9
KM		 691 platform_add_devices(r8a7740_late_devices,
692 ARRAY_SIZE(r8a7740_late_devices));
802a5639
KM		 693
694 /* add devices to PM domain */
695
8bdd9468
RW		 696 rmobile_add_device_to_domain("A3SP", &scif0_device);
697 rmobile_add_device_to_domain("A3SP", &scif1_device);
698 rmobile_add_device_to_domain("A3SP", &scif2_device);
699 rmobile_add_device_to_domain("A3SP", &scif3_device);
700 rmobile_add_device_to_domain("A3SP", &scif4_device);
701 rmobile_add_device_to_domain("A3SP", &scif5_device);
702 rmobile_add_device_to_domain("A3SP", &scif6_device);
703 rmobile_add_device_to_domain("A3SP", &scif7_device);
704 rmobile_add_device_to_domain("A3SP", &scifb_device);
705 rmobile_add_device_to_domain("A3SP", &i2c1_device);
6c01ba44
KM		 706}
707
23e5bc03
MD		 708static void __init r8a7740_earlytimer_init(void)
709{
710 r8a7740_clock_init(0);
711 shmobile_earlytimer_init();
712}
713
6c01ba44
KM		 714void __init r8a7740_add_early_devices(void)
715{
716 early_platform_add_devices(r8a7740_early_devices,
717 ARRAY_SIZE(r8a7740_early_devices));
d3ab7221
MD		 718
719 /* setup early console here as well */
720 shmobile_setup_console();
23e5bc03
MD		 721
722 /* override timer setup with soc-specific code */
723 shmobile_timer.init = r8a7740_earlytimer_init;
6c01ba44 724}
755d57b2
MD		 725
726#ifdef CONFIG_USE_OF
727
728void __init r8a7740_add_early_devices_dt(void)
729{
730 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
731
732 early_platform_add_devices(r8a7740_early_devices,
733 ARRAY_SIZE(r8a7740_early_devices));
734
735 /* setup early console here as well */
736 shmobile_setup_console();
737}
738
739static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
740 { }
741};
742
743void __init r8a7740_add_standard_devices_dt(void)
744{
745 /* clocks are setup late during boot in the case of DT */
746 r8a7740_clock_init(0);
747
748 platform_add_devices(r8a7740_early_devices,
749 ARRAY_SIZE(r8a7740_early_devices));
750
751 of_platform_populate(NULL, of_default_bus_match_table,
752 r8a7740_auxdata_lookup, NULL);
753}
754
755static const char *r8a7740_boards_compat_dt[] __initdata = {
756 "renesas,r8a7740",
757 NULL,
758};
759
a41acc4a 760DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
755d57b2
MD		 761 .map_io = r8a7740_map_io,
762 .init_early = r8a7740_add_early_devices_dt,
763 .init_irq = r8a7740_init_irq,
764 .handle_irq = shmobile_handle_irq_intc,
765 .init_machine = r8a7740_add_standard_devices_dt,
766 .timer = &shmobile_timer,
767 .dt_compat = r8a7740_boards_compat_dt,
768MACHINE_END
769
770#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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