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[deliverable/linux.git] / arch / arm / mach-shmobile / setup-r8a7790.c
CommitLineData
0468b2d6
MD		 1/*
2 * r8a7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
0468b2d6
MD		 15 */
16
17#include <linux/irq.h>
0468b2d6
MD		 18#include <linux/kernel.h>
19#include <linux/of_platform.h>
43ca9cbb 20#include <linux/platform_data/gpio-rcar.h>
8f5ec0a5 21#include <linux/platform_data/irq-renesas-irqc.h>
99ade1a0 22#include <linux/serial_sci.h>
2c578a1b 23#include <linux/sh_dma.h>
99ade1a0 24#include <linux/sh_timer.h>
fccae893 25
0468b2d6
MD		 26#include <asm/mach/arch.h>
27
fd44aa5e 28#include "common.h"
74ac0de8 29#include "dma-register.h"
b6bab126 30#include "irqs.h"
fccae893 31#include "r8a7790.h"
62872989 32#include "rcar-gen2.h"
0468b2d6 33
2c578a1b
KM		 34/* Audio-DMAC */
35#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
36{ \
37 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
38 .addr = _addr + 0x8, \
39 .chcr = CHCR_TX(XMIT_SZ_32BIT), \
40 .mid_rid = t, \
41}, { \
42 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
43 .addr = _addr + 0xc, \
44 .chcr = CHCR_RX(XMIT_SZ_32BIT), \
45 .mid_rid = r, \
46}
47
48static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
49 AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
50 AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
51 AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
52 AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
53 AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
54 AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
55 AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
56 AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
57 AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
58 AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
59};
60
61#define DMAE_CHANNEL(a, b) \
62{ \
63 .offset = (a) - 0x20, \
64 .dmars = (a) - 0x20 + 0x40, \
65 .chclr_bit = (b), \
66 .chclr_offset = 0x80 - 0x20, \
67}
68
69static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
70 DMAE_CHANNEL(0x8000, 0),
71 DMAE_CHANNEL(0x8080, 1),
72 DMAE_CHANNEL(0x8100, 2),
73 DMAE_CHANNEL(0x8180, 3),
74 DMAE_CHANNEL(0x8200, 4),
75 DMAE_CHANNEL(0x8280, 5),
76 DMAE_CHANNEL(0x8300, 6),
77 DMAE_CHANNEL(0x8380, 7),
78 DMAE_CHANNEL(0x8400, 8),
79 DMAE_CHANNEL(0x8480, 9),
80 DMAE_CHANNEL(0x8500, 10),
81 DMAE_CHANNEL(0x8580, 11),
82 DMAE_CHANNEL(0x8600, 12),
83};
84
85static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
86 .slave = r8a7790_audio_dmac_slaves,
87 .slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
88 .channel = r8a7790_audio_dmac_channels,
89 .channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
90 .ts_low_shift = TS_LOW_SHIFT,
91 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
92 .ts_high_shift = TS_HI_SHIFT,
93 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
94 .ts_shift = dma_ts_shift,
95 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
96 .dmaor_init = DMAOR_DME,
97 .chclr_present = 1,
98 .chclr_bitwise = 1,
99};
100
101static struct resource r8a7790_audio_dmac_resources[] = {
102 /* Channel registers and DMAOR for low */
103 DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
104 DEFINE_RES_IRQ(gic_spi(346)),
105 DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
106
107 /* Channel registers and DMAOR for hi */
108 DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
109 DEFINE_RES_IRQ(gic_spi(347)),
110 DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
111};
112
113#define r8a7790_register_audio_dmac(id) \
114 platform_device_register_resndata( \
d2168146 115 NULL, "sh-dma-engine", id, \
2c578a1b
KM		 116 &r8a7790_audio_dmac_resources[id * 3], 3, \
117 &r8a7790_audio_dmac_platform_data, \
118 sizeof(r8a7790_audio_dmac_platform_data))
119
cde214a8 120static const struct resource pfc_resources[] __initconst = {
69e351d0
MD		 121 DEFINE_RES_MEM(0xe6060000, 0x250),
122};
123
8d0b3bf7
MD		 124#define r8a7790_register_pfc() \
125 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
126 ARRAY_SIZE(pfc_resources))
127
43ca9cbb 128#define R8A7790_GPIO(idx) \
cde214a8 129static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
43ca9cbb
LP		 130 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
131 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
132}; \
133 \
cde214a8
LP		 134static const struct gpio_rcar_config \
135r8a7790_gpio##idx##_platform_data __initconst = { \
43ca9cbb
LP		 136 .gpio_base = 32 * (idx), \
137 .irq_base = 0, \
138 .number_of_pins = 32, \
139 .pctl_name = "pfc-r8a7790", \
d93906b8 140 .has_both_edge_trigger = 1, \
43ca9cbb
LP		 141}; \
142
143R8A7790_GPIO(0);
144R8A7790_GPIO(1);
145R8A7790_GPIO(2);
146R8A7790_GPIO(3);
147R8A7790_GPIO(4);
148R8A7790_GPIO(5);
149
150#define r8a7790_register_gpio(idx) \
d2168146 151 platform_device_register_resndata(NULL, "gpio_rcar", idx, \
43ca9cbb
LP		 152 r8a7790_gpio##idx##_resources, \
153 ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
154 &r8a7790_gpio##idx##_platform_data, \
155 sizeof(r8a7790_gpio##idx##_platform_data))
156
b448c904
KM		 157static struct resource i2c_resources[] __initdata = {
158 /* I2C0 */
159 DEFINE_RES_MEM(0xE6508000, 0x40),
160 DEFINE_RES_IRQ(gic_spi(287)),
161 /* I2C1 */
162 DEFINE_RES_MEM(0xE6518000, 0x40),
163 DEFINE_RES_IRQ(gic_spi(288)),
164 /* I2C2 */
165 DEFINE_RES_MEM(0xE6530000, 0x40),
166 DEFINE_RES_IRQ(gic_spi(286)),
167 /* I2C3 */
168 DEFINE_RES_MEM(0xE6540000, 0x40),
169 DEFINE_RES_IRQ(gic_spi(290)),
170
171};
172
173#define r8a7790_register_i2c(idx) \
174 platform_device_register_simple( \
db455c78 175 "i2c-rcar_gen2", idx, \
b448c904
KM		 176 i2c_resources + (2 * idx), 2); \
177
69e351d0
MD		 178void __init r8a7790_pinmux_init(void)
179{
8d0b3bf7 180 r8a7790_register_pfc();
43ca9cbb
LP		 181 r8a7790_register_gpio(0);
182 r8a7790_register_gpio(1);
183 r8a7790_register_gpio(2);
184 r8a7790_register_gpio(3);
185 r8a7790_register_gpio(4);
186 r8a7790_register_gpio(5);
69e351d0
MD		 187}
188
6319ea50 189#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
302d8898
LP		 190static struct plat_sci_port scif##index##_platform_data = { \
191 .type = scif_type, \
302d8898 192 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
302d8898 193 .scscr = _scscr, \
c0a384f5
LP		 194}; \
195 \
196static struct resource scif##index##_resources[] = { \
197 DEFINE_RES_MEM(baseaddr, 0x100), \
198 DEFINE_RES_IRQ(irq), \
d44f8308
UH		 199}
200
302d8898
LP		 201#define R8A7790_SCIF(index, baseaddr, irq) \
202 __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
6319ea50 203 index, baseaddr, irq)
302d8898
LP		 204
205#define R8A7790_SCIFA(index, baseaddr, irq) \
206 __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
6319ea50 207 index, baseaddr, irq)
302d8898
LP		 208
209#define R8A7790_SCIFB(index, baseaddr, irq) \
210 __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
6319ea50 211 index, baseaddr, irq)
302d8898
LP		 212
213#define R8A7790_HSCIF(index, baseaddr, irq) \
214 __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
6319ea50 215 index, baseaddr, irq)
302d8898
LP		 216
217R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
218R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
219R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
220R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
221R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
222R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
223R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
224R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
225R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
226R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
227
228#define r8a7790_register_scif(index) \
d2168146 229 platform_device_register_resndata(NULL, "sh-sci", index, \
c0a384f5
LP		 230 scif##index##_resources, \
231 ARRAY_SIZE(scif##index##_resources), \
232 &scif##index##_platform_data, \
233 sizeof(scif##index##_platform_data))
55d9fab2 234
cde214a8 235static const struct renesas_irqc_config irqc0_data __initconst = {
8f5ec0a5
MD		 236 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
237};
238
cde214a8 239static const struct resource irqc0_resources[] __initconst = {
8f5ec0a5
MD		 240 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
241 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
242 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
243 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
244 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
245};
246
247#define r8a7790_register_irqc(idx) \
d2168146 248 platform_device_register_resndata(NULL, "renesas_irqc", \
8f5ec0a5
MD		 249 idx, irqc##idx##_resources, \
250 ARRAY_SIZE(irqc##idx##_resources), \
251 &irqc##idx##_data, \
252 sizeof(struct renesas_irqc_config))
253
cde214a8 254static const struct resource thermal_resources[] __initconst = {
0b8eeba4
SH		 255 DEFINE_RES_MEM(0xe61f0000, 0x14),
256 DEFINE_RES_MEM(0xe61f0100, 0x38),
257 DEFINE_RES_IRQ(gic_spi(69)),
258};
259
260#define r8a7790_register_thermal() \
261 platform_device_register_simple("rcar_thermal", -1, \
262 thermal_resources, \
263 ARRAY_SIZE(thermal_resources))
264
711ee6c8
LP		 265static struct sh_timer_config cmt0_platform_data = {
266 .channels_mask = 0x60,
99ade1a0
MD		 267};
268
711ee6c8
LP		 269static struct resource cmt0_resources[] = {
270 DEFINE_RES_MEM(0xffca0000, 0x1004),
271 DEFINE_RES_IRQ(gic_spi(142)),
99ade1a0
MD		 272};
273
274#define r8a7790_register_cmt(idx) \
d2168146 275 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
99ade1a0
MD		 276 idx, cmt##idx##_resources, \
277 ARRAY_SIZE(cmt##idx##_resources), \
278 &cmt##idx##_platform_data, \
279 sizeof(struct sh_timer_config))
280
4e9c4877 281void __init r8a7790_add_standard_devices(void)
0468b2d6 282{
302d8898
LP		 283 r8a7790_register_scif(0);
284 r8a7790_register_scif(1);
285 r8a7790_register_scif(2);
286 r8a7790_register_scif(3);
287 r8a7790_register_scif(4);
288 r8a7790_register_scif(5);
289 r8a7790_register_scif(6);
290 r8a7790_register_scif(7);
291 r8a7790_register_scif(8);
292 r8a7790_register_scif(9);
247fd5ec 293 r8a7790_register_cmt(0);
8f5ec0a5 294 r8a7790_register_irqc(0);
0b8eeba4 295 r8a7790_register_thermal();
f05b4b52
MD		 296 r8a7790_register_i2c(0);
297 r8a7790_register_i2c(1);
298 r8a7790_register_i2c(2);
299 r8a7790_register_i2c(3);
300 r8a7790_register_audio_dmac(0);
301 r8a7790_register_audio_dmac(1);
0468b2d6
MD		 302}
303
304#ifdef CONFIG_USE_OF
0468b2d6 305
cde214a8 306static const char * const r8a7790_boards_compat_dt[] __initconst = {
0468b2d6
MD		 307 "renesas,r8a7790",
308 NULL,
309};
310
311DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
ad09cb83 312 .smp = smp_ops(r8a7790_smp_ops),
ed06ecbc 313 .init_early = shmobile_init_delay,
50c517d9 314 .init_time = rcar_gen2_timer_init,
7d95b9dd 315 .init_late = shmobile_init_late,
f8e81935 316 .reserve = rcar_gen2_reserve,
0468b2d6
MD		 317 .dt_compat = r8a7790_boards_compat_dt,
318MACHINE_END
319#endif /* CONFIG_USE_OF */
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