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Merge tag 'iio-fixes-for-3.19a' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / arm / mach-shmobile / setup-sh7372.c
CommitLineData
2b7eda63
MD		 1/*
2 * sh7372 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
2b7eda63
MD		 15 */
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/platform_device.h>
3b7b7055 21#include <linux/of_platform.h>
6822471e 22#include <linux/uio_driver.h>
2b7eda63
MD		 23#include <linux/delay.h>
24#include <linux/input.h>
25#include <linux/io.h>
26#include <linux/serial_sci.h>
69bf6f45 27#include <linux/sh_dma.h>
2b7eda63 28#include <linux/sh_timer.h>
111058c3 29#include <linux/pm_domain.h>
426f1af9 30#include <linux/dma-mapping.h>
3cfb8439 31#include <linux/platform_data/sh_ipmmu.h>
113522ee 32
5d7220ec 33#include <asm/mach/map.h>
2b7eda63
MD		 34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
17254bff 36#include <asm/mach/time.h>
113522ee 37
fd44aa5e 38#include "common.h"
74ac0de8 39#include "dma-register.h"
86155b35 40#include "intc.h"
b6bab126 41#include "irqs.h"
6b8b0cb4 42#include "pm-rmobile.h"
113522ee 43#include "sh7372.h"
2b7eda63 44
5d7220ec 45static struct map_desc sh7372_io_desc[] __initdata = {
44091c11 46 /* create a 1:1 identity mapping for 0xe6xxxxxx
5d7220ec
MD		 47 * used by CPGA, INTC and PFC.
48 */
49 {
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
52 .length = 256 << 20,
53 .type = MT_DEVICE_NONSHARED
54 },
55};
56
57void __init sh7372_map_io(void)
58{
7a2071c5 59 debug_ll_io_init();
5d7220ec
MD		 60 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
61}
2b7eda63 62
5967fe09
LP		 63/* PFC */
64static struct resource sh7372_pfc_resources[] = {
65 [0] = {
66 .start = 0xe6050000,
67 .end = 0xe6057fff,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = 0xe605800c,
72 .end = 0xe6058027,
73 .flags = IORESOURCE_MEM,
74 }
75};
76
77static struct platform_device sh7372_pfc_device = {
78 .name = "pfc-sh7372",
79 .id = -1,
80 .resource = sh7372_pfc_resources,
81 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
82};
83
84void __init sh7372_pinmux_init(void)
85{
86 platform_device_register(&sh7372_pfc_device);
87}
88
c6a0d864
LP		 89/* SCIF */
90#define SH7372_SCIF(scif_type, index, baseaddr, irq) \
91static struct plat_sci_port scif##index##_platform_data = { \
92 .type = scif_type, \
c6a0d864 93 .flags = UPF_BOOT_AUTOCONF, \
c6a0d864
LP		 94 .scscr = SCSCR_RE | SCSCR_TE, \
95}; \
96 \
d39f98b3
LP		 97static struct resource scif##index##_resources[] = { \
98 DEFINE_RES_MEM(baseaddr, 0x100), \
99 DEFINE_RES_IRQ(irq), \
100}; \
101 \
c6a0d864
LP		 102static struct platform_device scif##index##_device = { \
103 .name = "sh-sci", \
104 .id = index, \
d39f98b3
LP		 105 .resource = scif##index##_resources, \
106 .num_resources = ARRAY_SIZE(scif##index##_resources), \
c6a0d864
LP		 107 .dev = { \
108 .platform_data = &scif##index##_platform_data, \
109 }, \
110}
2b7eda63 111
c6a0d864
LP		 112SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
113SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
114SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
115SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
116SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
117SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
118SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
2b7eda63 119
c1909cc1 120/* CMT */
0ed61fc9 121static struct sh_timer_config cmt2_platform_data = {
386f60aa 122 .channels_mask = 0x20,
2b7eda63
MD		 123};
124
0ed61fc9 125static struct resource cmt2_resources[] = {
386f60aa
LP		 126 DEFINE_RES_MEM(0xe6130000, 0x50),
127 DEFINE_RES_IRQ(evt2irq(0x0b80)),
2b7eda63
MD		 128};
129
0ed61fc9 130static struct platform_device cmt2_device = {
386f60aa 131 .name = "sh-cmt-32-fast",
0ed61fc9 132 .id = 2,
2b7eda63 133 .dev = {
0ed61fc9 134 .platform_data = &cmt2_platform_data,
2b7eda63 135 },
0ed61fc9
MD		 136 .resource = cmt2_resources,
137 .num_resources = ARRAY_SIZE(cmt2_resources),
2b7eda63
MD		 138};
139
c6c049ec 140/* TMU */
8e8236a9
LP		 141static struct sh_timer_config tmu0_platform_data = {
142 .channels_mask = 7,
c6c049ec
MD		 143};
144
8e8236a9
LP		 145static struct resource tmu0_resources[] = {
146 DEFINE_RES_MEM(0xfff60000, 0x2c),
147 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
148 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
149 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
c6c049ec
MD		 150};
151
8e8236a9
LP		 152static struct platform_device tmu0_device = {
153 .name = "sh-tmu",
c6c049ec
MD		 154 .id = 0,
155 .dev = {
8e8236a9 156 .platform_data = &tmu0_platform_data,
c6c049ec 157 },
8e8236a9
LP		 158 .resource = tmu0_resources,
159 .num_resources = ARRAY_SIZE(tmu0_resources),
c6c049ec
MD		 160};
161
c1909cc1
KM		 162/* I2C */
163static struct resource iic0_resources[] = {
164 [0] = {
165 .name = "IIC0",
166 .start = 0xFFF20000,
167 .end = 0xFFF20425 - 1,
168 .flags = IORESOURCE_MEM,
169 },
170 [1] = {
33c9607a
MD		 171 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
172 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
c1909cc1
KM		 173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct platform_device iic0_device = {
178 .name = "i2c-sh_mobile",
179 .id = 0, /* "i2c0" clock */
180 .num_resources = ARRAY_SIZE(iic0_resources),
181 .resource = iic0_resources,
182};
183
184static struct resource iic1_resources[] = {
185 [0] = {
186 .name = "IIC1",
187 .start = 0xE6C20000,
188 .end = 0xE6C20425 - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 [1] = {
33c9607a
MD		 192 .start = evt2irq(0x780), /* IIC1_ALI1 */
193 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
c1909cc1
KM		 194 .flags = IORESOURCE_IRQ,
195 },
196};
197
198static struct platform_device iic1_device = {
199 .name = "i2c-sh_mobile",
200 .id = 1, /* "i2c1" clock */
201 .num_resources = ARRAY_SIZE(iic1_resources),
202 .resource = iic1_resources,
203};
204
69bf6f45 205/* DMA */
69bf6f45
GL		 206static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
207 {
8d3e17ba
GL		 208 .slave_id = SHDMA_SLAVE_SCIF0_TX,
209 .addr = 0xe6c40020,
c317fc59 210 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 211 .mid_rid = 0x21,
212 }, {
213 .slave_id = SHDMA_SLAVE_SCIF0_RX,
214 .addr = 0xe6c40024,
c317fc59 215 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 216 .mid_rid = 0x22,
217 }, {
218 .slave_id = SHDMA_SLAVE_SCIF1_TX,
219 .addr = 0xe6c50020,
c317fc59 220 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 221 .mid_rid = 0x25,
222 }, {
223 .slave_id = SHDMA_SLAVE_SCIF1_RX,
224 .addr = 0xe6c50024,
c317fc59 225 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 226 .mid_rid = 0x26,
227 }, {
228 .slave_id = SHDMA_SLAVE_SCIF2_TX,
229 .addr = 0xe6c60020,
c317fc59 230 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 231 .mid_rid = 0x29,
232 }, {
233 .slave_id = SHDMA_SLAVE_SCIF2_RX,
234 .addr = 0xe6c60024,
c317fc59 235 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 236 .mid_rid = 0x2a,
237 }, {
238 .slave_id = SHDMA_SLAVE_SCIF3_TX,
239 .addr = 0xe6c70020,
c317fc59 240 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 241 .mid_rid = 0x2d,
242 }, {
243 .slave_id = SHDMA_SLAVE_SCIF3_RX,
244 .addr = 0xe6c70024,
c317fc59 245 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 246 .mid_rid = 0x2e,
247 }, {
248 .slave_id = SHDMA_SLAVE_SCIF4_TX,
249 .addr = 0xe6c80020,
c317fc59 250 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 251 .mid_rid = 0x39,
252 }, {
253 .slave_id = SHDMA_SLAVE_SCIF4_RX,
254 .addr = 0xe6c80024,
c317fc59 255 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 256 .mid_rid = 0x3a,
257 }, {
258 .slave_id = SHDMA_SLAVE_SCIF5_TX,
259 .addr = 0xe6cb0020,
c317fc59 260 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 261 .mid_rid = 0x35,
262 }, {
263 .slave_id = SHDMA_SLAVE_SCIF5_RX,
264 .addr = 0xe6cb0024,
c317fc59 265 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 266 .mid_rid = 0x36,
267 }, {
268 .slave_id = SHDMA_SLAVE_SCIF6_TX,
269 .addr = 0xe6c30040,
c317fc59 270 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 271 .mid_rid = 0x3d,
272 }, {
273 .slave_id = SHDMA_SLAVE_SCIF6_RX,
274 .addr = 0xe6c30060,
c317fc59 275 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba 276 .mid_rid = 0x3e,
40eaed7f
BH		 277 }, {
278 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
279 .addr = 0xe6a30050,
280 .chcr = CHCR_TX(XMIT_SZ_32BIT),
281 .mid_rid = 0x83,
282 }, {
283 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
284 .addr = 0xe6a30050,
285 .chcr = CHCR_RX(XMIT_SZ_32BIT),
286 .mid_rid = 0x83,
287 }, {
288 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
289 .addr = 0xe6a30060,
290 .chcr = CHCR_TX(XMIT_SZ_32BIT),
291 .mid_rid = 0x87,
292 }, {
293 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
294 .addr = 0xe6a30060,
295 .chcr = CHCR_RX(XMIT_SZ_32BIT),
296 .mid_rid = 0x87,
8d3e17ba 297 }, {
69bf6f45
GL		 298 .slave_id = SHDMA_SLAVE_SDHI0_TX,
299 .addr = 0xe6850030,
c317fc59 300 .chcr = CHCR_TX(XMIT_SZ_16BIT),
69bf6f45
GL		 301 .mid_rid = 0xc1,
302 }, {
303 .slave_id = SHDMA_SLAVE_SDHI0_RX,
304 .addr = 0xe6850030,
c317fc59 305 .chcr = CHCR_RX(XMIT_SZ_16BIT),
69bf6f45
GL		 306 .mid_rid = 0xc2,
307 }, {
308 .slave_id = SHDMA_SLAVE_SDHI1_TX,
309 .addr = 0xe6860030,
c317fc59 310 .chcr = CHCR_TX(XMIT_SZ_16BIT),
69bf6f45
GL		 311 .mid_rid = 0xc9,
312 }, {
313 .slave_id = SHDMA_SLAVE_SDHI1_RX,
314 .addr = 0xe6860030,
c317fc59 315 .chcr = CHCR_RX(XMIT_SZ_16BIT),
69bf6f45
GL		 316 .mid_rid = 0xca,
317 }, {
318 .slave_id = SHDMA_SLAVE_SDHI2_TX,
319 .addr = 0xe6870030,
c317fc59 320 .chcr = CHCR_TX(XMIT_SZ_16BIT),
69bf6f45
GL		 321 .mid_rid = 0xcd,
322 }, {
323 .slave_id = SHDMA_SLAVE_SDHI2_RX,
324 .addr = 0xe6870030,
c317fc59 325 .chcr = CHCR_RX(XMIT_SZ_16BIT),
69bf6f45 326 .mid_rid = 0xce,
880452b6
KM		 327 }, {
328 .slave_id = SHDMA_SLAVE_FSIA_TX,
329 .addr = 0xfe1f0024,
c317fc59 330 .chcr = CHCR_TX(XMIT_SZ_32BIT),
880452b6
KM		 331 .mid_rid = 0xb1,
332 }, {
333 .slave_id = SHDMA_SLAVE_FSIA_RX,
334 .addr = 0xfe1f0020,
c317fc59 335 .chcr = CHCR_RX(XMIT_SZ_32BIT),
880452b6 336 .mid_rid = 0xb2,
6d11dc14
GL		 337 }, {
338 .slave_id = SHDMA_SLAVE_MMCIF_TX,
339 .addr = 0xe6bd0034,
c317fc59 340 .chcr = CHCR_TX(XMIT_SZ_32BIT),
6d11dc14
GL		 341 .mid_rid = 0xd1,
342 }, {
343 .slave_id = SHDMA_SLAVE_MMCIF_RX,
344 .addr = 0xe6bd0034,
c317fc59 345 .chcr = CHCR_RX(XMIT_SZ_32BIT),
6d11dc14 346 .mid_rid = 0xd2,
69bf6f45
GL		 347 },
348};
349
4d6344f3 350#define SH7372_CHCLR (0x220 - 0x20)
e08b881a 351
69bf6f45
GL		 352static const struct sh_dmae_channel sh7372_dmae_channels[] = {
353 {
354 .offset = 0,
355 .dmars = 0,
356 .dmars_bit = 0,
e08b881a 357 .chclr_offset = SH7372_CHCLR + 0,
69bf6f45
GL		 358 }, {
359 .offset = 0x10,
360 .dmars = 0,
361 .dmars_bit = 8,
e08b881a 362 .chclr_offset = SH7372_CHCLR + 0x10,
69bf6f45
GL		 363 }, {
364 .offset = 0x20,
365 .dmars = 4,
366 .dmars_bit = 0,
e08b881a 367 .chclr_offset = SH7372_CHCLR + 0x20,
69bf6f45
GL		 368 }, {
369 .offset = 0x30,
370 .dmars = 4,
371 .dmars_bit = 8,
e08b881a 372 .chclr_offset = SH7372_CHCLR + 0x30,
69bf6f45
GL		 373 }, {
374 .offset = 0x50,
375 .dmars = 8,
376 .dmars_bit = 0,
e08b881a 377 .chclr_offset = SH7372_CHCLR + 0x50,
69bf6f45
GL		 378 }, {
379 .offset = 0x60,
380 .dmars = 8,
381 .dmars_bit = 8,
e08b881a 382 .chclr_offset = SH7372_CHCLR + 0x60,
69bf6f45
GL		 383 }
384};
385
69bf6f45
GL		 386static struct sh_dmae_pdata dma_platform_data = {
387 .slave = sh7372_dmae_slaves,
388 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
389 .channel = sh7372_dmae_channels,
390 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
c317fc59
KM		 391 .ts_low_shift = TS_LOW_SHIFT,
392 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
393 .ts_high_shift = TS_HI_SHIFT,
394 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
395 .ts_shift = dma_ts_shift,
396 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
69bf6f45 397 .dmaor_init = DMAOR_DME,
e08b881a 398 .chclr_present = 1,
69bf6f45
GL		 399};
400
401/* Resource order important! */
402static struct resource sh7372_dmae0_resources[] = {
403 {
404 /* Channel registers and DMAOR */
405 .start = 0xfe008020,
e08b881a 406 .end = 0xfe00828f,
69bf6f45
GL		 407 .flags = IORESOURCE_MEM,
408 },
409 {
410 /* DMARSx */
411 .start = 0xfe009000,
412 .end = 0xfe00900b,
413 .flags = IORESOURCE_MEM,
414 },
415 {
20052462 416 .name = "error_irq",
f989ae5b
MD		 417 .start = evt2irq(0x20c0),
418 .end = evt2irq(0x20c0),
69bf6f45
GL		 419 .flags = IORESOURCE_IRQ,
420 },
421 {
422 /* IRQ for channels 0-5 */
f989ae5b
MD		 423 .start = evt2irq(0x2000),
424 .end = evt2irq(0x20a0),
69bf6f45
GL		 425 .flags = IORESOURCE_IRQ,
426 },
427};
428
429/* Resource order important! */
430static struct resource sh7372_dmae1_resources[] = {
431 {
432 /* Channel registers and DMAOR */
433 .start = 0xfe018020,
e08b881a 434 .end = 0xfe01828f,
69bf6f45
GL		 435 .flags = IORESOURCE_MEM,
436 },
437 {
438 /* DMARSx */
439 .start = 0xfe019000,
440 .end = 0xfe01900b,
441 .flags = IORESOURCE_MEM,
442 },
443 {
20052462 444 .name = "error_irq",
f989ae5b
MD		 445 .start = evt2irq(0x21c0),
446 .end = evt2irq(0x21c0),
69bf6f45
GL		 447 .flags = IORESOURCE_IRQ,
448 },
449 {
450 /* IRQ for channels 0-5 */
f989ae5b
MD		 451 .start = evt2irq(0x2100),
452 .end = evt2irq(0x21a0),
69bf6f45
GL		 453 .flags = IORESOURCE_IRQ,
454 },
455};
456
457/* Resource order important! */
458static struct resource sh7372_dmae2_resources[] = {
459 {
460 /* Channel registers and DMAOR */
461 .start = 0xfe028020,
e08b881a 462 .end = 0xfe02828f,
69bf6f45
GL		 463 .flags = IORESOURCE_MEM,
464 },
465 {
466 /* DMARSx */
467 .start = 0xfe029000,
468 .end = 0xfe02900b,
469 .flags = IORESOURCE_MEM,
470 },
471 {
20052462 472 .name = "error_irq",
f989ae5b
MD		 473 .start = evt2irq(0x22c0),
474 .end = evt2irq(0x22c0),
69bf6f45
GL		 475 .flags = IORESOURCE_IRQ,
476 },
477 {
478 /* IRQ for channels 0-5 */
f989ae5b
MD		 479 .start = evt2irq(0x2200),
480 .end = evt2irq(0x22a0),
69bf6f45
GL		 481 .flags = IORESOURCE_IRQ,
482 },
483};
484
485static struct platform_device dma0_device = {
486 .name = "sh-dma-engine",
487 .id = 0,
488 .resource = sh7372_dmae0_resources,
489 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
490 .dev = {
491 .platform_data = &dma_platform_data,
492 },
493};
494
495static struct platform_device dma1_device = {
496 .name = "sh-dma-engine",
497 .id = 1,
498 .resource = sh7372_dmae1_resources,
499 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
500 .dev = {
501 .platform_data = &dma_platform_data,
502 },
503};
504
505static struct platform_device dma2_device = {
506 .name = "sh-dma-engine",
507 .id = 2,
508 .resource = sh7372_dmae2_resources,
509 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
510 .dev = {
511 .platform_data = &dma_platform_data,
512 },
513};
514
afe48049
KM		 515/*
516 * USB-DMAC
517 */
afe48049
KM		 518static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
519 {
520 .offset = 0,
521 }, {
522 .offset = 0x20,
523 },
524};
525
526/* USB DMAC0 */
527static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
528 {
529 .slave_id = SHDMA_SLAVE_USB0_TX,
c317fc59 530 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 531 }, {
532 .slave_id = SHDMA_SLAVE_USB0_RX,
c317fc59 533 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 534 },
535};
536
537static struct sh_dmae_pdata usb_dma0_platform_data = {
538 .slave = sh7372_usb_dmae0_slaves,
539 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
540 .channel = sh7372_usb_dmae_channels,
541 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
c317fc59
KM		 542 .ts_low_shift = USBTS_LOW_SHIFT,
543 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
544 .ts_high_shift = USBTS_HI_SHIFT,
545 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
546 .ts_shift = dma_usbts_shift,
547 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
afe48049
KM		 548 .dmaor_init = DMAOR_DME,
549 .chcr_offset = 0x14,
550 .chcr_ie_bit = 1 << 5,
551 .dmaor_is_32bit = 1,
552 .needs_tend_set = 1,
553 .no_dmars = 1,
c8ddf036 554 .slave_only = 1,
afe48049
KM		 555};
556
557static struct resource sh7372_usb_dmae0_resources[] = {
558 {
559 /* Channel registers and DMAOR */
560 .start = 0xe68a0020,
561 .end = 0xe68a0064 - 1,
562 .flags = IORESOURCE_MEM,
563 },
564 {
565 /* VCR/SWR/DMICR */
566 .start = 0xe68a0000,
567 .end = 0xe68a0014 - 1,
568 .flags = IORESOURCE_MEM,
569 },
570 {
571 /* IRQ for channels */
572 .start = evt2irq(0x0a00),
573 .end = evt2irq(0x0a00),
574 .flags = IORESOURCE_IRQ,
575 },
576};
577
578static struct platform_device usb_dma0_device = {
579 .name = "sh-dma-engine",
580 .id = 3,
581 .resource = sh7372_usb_dmae0_resources,
582 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
583 .dev = {
584 .platform_data = &usb_dma0_platform_data,
585 },
586};
587
588/* USB DMAC1 */
589static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
590 {
591 .slave_id = SHDMA_SLAVE_USB1_TX,
c317fc59 592 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 593 }, {
594 .slave_id = SHDMA_SLAVE_USB1_RX,
c317fc59 595 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 596 },
597};
598
599static struct sh_dmae_pdata usb_dma1_platform_data = {
600 .slave = sh7372_usb_dmae1_slaves,
601 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
602 .channel = sh7372_usb_dmae_channels,
603 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
c317fc59
KM		 604 .ts_low_shift = USBTS_LOW_SHIFT,
605 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
606 .ts_high_shift = USBTS_HI_SHIFT,
607 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
608 .ts_shift = dma_usbts_shift,
609 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
afe48049
KM		 610 .dmaor_init = DMAOR_DME,
611 .chcr_offset = 0x14,
612 .chcr_ie_bit = 1 << 5,
613 .dmaor_is_32bit = 1,
614 .needs_tend_set = 1,
615 .no_dmars = 1,
c8ddf036 616 .slave_only = 1,
afe48049
KM		 617};
618
619static struct resource sh7372_usb_dmae1_resources[] = {
620 {
621 /* Channel registers and DMAOR */
622 .start = 0xe68c0020,
623 .end = 0xe68c0064 - 1,
624 .flags = IORESOURCE_MEM,
625 },
626 {
627 /* VCR/SWR/DMICR */
628 .start = 0xe68c0000,
629 .end = 0xe68c0014 - 1,
630 .flags = IORESOURCE_MEM,
631 },
632 {
633 /* IRQ for channels */
634 .start = evt2irq(0x1d00),
635 .end = evt2irq(0x1d00),
636 .flags = IORESOURCE_IRQ,
637 },
638};
639
640static struct platform_device usb_dma1_device = {
641 .name = "sh-dma-engine",
642 .id = 4,
643 .resource = sh7372_usb_dmae1_resources,
644 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
645 .dev = {
646 .platform_data = &usb_dma1_platform_data,
647 },
648};
649
6822471e
MD		 650/* VPU */
651static struct uio_info vpu_platform_data = {
652 .name = "VPU5HG",
653 .version = "0",
654 .irq = intcs_evt2irq(0x980),
655};
656
657static struct resource vpu_resources[] = {
658 [0] = {
659 .name = "VPU",
660 .start = 0xfe900000,
661 .end = 0xfe900157,
662 .flags = IORESOURCE_MEM,
663 },
664};
665
666static struct platform_device vpu_device = {
667 .name = "uio_pdrv_genirq",
668 .id = 0,
669 .dev = {
670 .platform_data = &vpu_platform_data,
671 },
672 .resource = vpu_resources,
673 .num_resources = ARRAY_SIZE(vpu_resources),
674};
675
676/* VEU0 */
677static struct uio_info veu0_platform_data = {
678 .name = "VEU0",
679 .version = "0",
680 .irq = intcs_evt2irq(0x700),
681};
682
683static struct resource veu0_resources[] = {
684 [0] = {
685 .name = "VEU0",
686 .start = 0xfe920000,
687 .end = 0xfe9200cb,
688 .flags = IORESOURCE_MEM,
689 },
690};
691
692static struct platform_device veu0_device = {
693 .name = "uio_pdrv_genirq",
694 .id = 1,
695 .dev = {
696 .platform_data = &veu0_platform_data,
697 },
698 .resource = veu0_resources,
699 .num_resources = ARRAY_SIZE(veu0_resources),
700};
701
702/* VEU1 */
703static struct uio_info veu1_platform_data = {
704 .name = "VEU1",
705 .version = "0",
706 .irq = intcs_evt2irq(0x720),
707};
708
709static struct resource veu1_resources[] = {
710 [0] = {
711 .name = "VEU1",
712 .start = 0xfe924000,
713 .end = 0xfe9240cb,
714 .flags = IORESOURCE_MEM,
715 },
716};
717
718static struct platform_device veu1_device = {
719 .name = "uio_pdrv_genirq",
720 .id = 2,
721 .dev = {
722 .platform_data = &veu1_platform_data,
723 },
724 .resource = veu1_resources,
725 .num_resources = ARRAY_SIZE(veu1_resources),
726};
727
728/* VEU2 */
729static struct uio_info veu2_platform_data = {
730 .name = "VEU2",
731 .version = "0",
732 .irq = intcs_evt2irq(0x740),
733};
734
735static struct resource veu2_resources[] = {
736 [0] = {
737 .name = "VEU2",
738 .start = 0xfe928000,
739 .end = 0xfe928307,
740 .flags = IORESOURCE_MEM,
741 },
742};
743
744static struct platform_device veu2_device = {
745 .name = "uio_pdrv_genirq",
746 .id = 3,
747 .dev = {
748 .platform_data = &veu2_platform_data,
749 },
750 .resource = veu2_resources,
751 .num_resources = ARRAY_SIZE(veu2_resources),
752};
753
754/* VEU3 */
755static struct uio_info veu3_platform_data = {
756 .name = "VEU3",
757 .version = "0",
758 .irq = intcs_evt2irq(0x760),
759};
760
761static struct resource veu3_resources[] = {
762 [0] = {
763 .name = "VEU3",
764 .start = 0xfe92c000,
765 .end = 0xfe92c307,
766 .flags = IORESOURCE_MEM,
767 },
768};
769
770static struct platform_device veu3_device = {
771 .name = "uio_pdrv_genirq",
772 .id = 4,
773 .dev = {
774 .platform_data = &veu3_platform_data,
775 },
776 .resource = veu3_resources,
777 .num_resources = ARRAY_SIZE(veu3_resources),
778};
779
780/* JPU */
781static struct uio_info jpu_platform_data = {
782 .name = "JPU",
783 .version = "0",
784 .irq = intcs_evt2irq(0x560),
785};
786
787static struct resource jpu_resources[] = {
788 [0] = {
789 .name = "JPU",
790 .start = 0xfe980000,
791 .end = 0xfe9902d3,
792 .flags = IORESOURCE_MEM,
793 },
794};
795
796static struct platform_device jpu_device = {
797 .name = "uio_pdrv_genirq",
798 .id = 5,
799 .dev = {
800 .platform_data = &jpu_platform_data,
801 },
802 .resource = jpu_resources,
803 .num_resources = ARRAY_SIZE(jpu_resources),
804};
805
806/* SPU2DSP0 */
807static struct uio_info spu0_platform_data = {
808 .name = "SPU2DSP0",
809 .version = "0",
810 .irq = evt2irq(0x1800),
811};
812
813static struct resource spu0_resources[] = {
814 [0] = {
815 .name = "SPU2DSP0",
816 .start = 0xfe200000,
817 .end = 0xfe2fffff,
818 .flags = IORESOURCE_MEM,
819 },
820};
821
822static struct platform_device spu0_device = {
823 .name = "uio_pdrv_genirq",
824 .id = 6,
825 .dev = {
826 .platform_data = &spu0_platform_data,
827 },
828 .resource = spu0_resources,
829 .num_resources = ARRAY_SIZE(spu0_resources),
830};
831
832/* SPU2DSP1 */
833static struct uio_info spu1_platform_data = {
834 .name = "SPU2DSP1",
835 .version = "0",
836 .irq = evt2irq(0x1820),
837};
838
839static struct resource spu1_resources[] = {
840 [0] = {
841 .name = "SPU2DSP1",
842 .start = 0xfe300000,
843 .end = 0xfe3fffff,
844 .flags = IORESOURCE_MEM,
845 },
846};
847
848static struct platform_device spu1_device = {
849 .name = "uio_pdrv_genirq",
850 .id = 7,
851 .dev = {
852 .platform_data = &spu1_platform_data,
853 },
854 .resource = spu1_resources,
855 .num_resources = ARRAY_SIZE(spu1_resources),
856};
857
3cfb8439
HE		 858/* IPMMUI (an IPMMU module for ICB/LMB) */
859static struct resource ipmmu_resources[] = {
860 [0] = {
861 .name = "IPMMUI",
862 .start = 0xfe951000,
863 .end = 0xfe9510ff,
864 .flags = IORESOURCE_MEM,
865 },
866};
867
868static const char * const ipmmu_dev_names[] = {
869 "sh_mobile_lcdc_fb.0",
870 "sh_mobile_lcdc_fb.1",
871 "sh_mobile_ceu.0",
872 "uio_pdrv_genirq.0",
873 "uio_pdrv_genirq.1",
874 "uio_pdrv_genirq.2",
875 "uio_pdrv_genirq.3",
876 "uio_pdrv_genirq.4",
877 "uio_pdrv_genirq.5",
878};
879
880static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
881 .dev_names = ipmmu_dev_names,
882 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
883};
884
885static struct platform_device ipmmu_device = {
886 .name = "ipmmu",
887 .id = -1,
888 .dev = {
889 .platform_data = &ipmmu_platform_data,
890 },
891 .resource = ipmmu_resources,
892 .num_resources = ARRAY_SIZE(ipmmu_resources),
893};
894
2b7eda63
MD		 895static struct platform_device *sh7372_early_devices[] __initdata = {
896 &scif0_device,
897 &scif1_device,
898 &scif2_device,
899 &scif3_device,
900 &scif4_device,
901 &scif5_device,
902 &scif6_device,
0ed61fc9 903 &cmt2_device,
8e8236a9 904 &tmu0_device,
3cfb8439 905 &ipmmu_device,
934e4078
MD		 906};
907
908static struct platform_device *sh7372_late_devices[] __initdata = {
c1909cc1
KM		 909 &iic0_device,
910 &iic1_device,
69bf6f45
GL		 911 &dma0_device,
912 &dma1_device,
913 &dma2_device,
afe48049
KM		 914 &usb_dma0_device,
915 &usb_dma1_device,
6822471e
MD		 916 &vpu_device,
917 &veu0_device,
918 &veu1_device,
919 &veu2_device,
920 &veu3_device,
921 &jpu_device,
922 &spu0_device,
923 &spu1_device,
2b7eda63
MD		 924};
925
926void __init sh7372_add_standard_devices(void)
927{
9eda01b2 928 static struct pm_domain_device domain_devices[] __initdata = {
ac18e02d
RW		 929 { "A3RV", &vpu_device, },
930 { "A4MP", &spu0_device, },
931 { "A4MP", &spu1_device, },
932 { "A3SP", &scif0_device, },
933 { "A3SP", &scif1_device, },
934 { "A3SP", &scif2_device, },
935 { "A3SP", &scif3_device, },
936 { "A3SP", &scif4_device, },
937 { "A3SP", &scif5_device, },
938 { "A3SP", &scif6_device, },
939 { "A3SP", &iic1_device, },
940 { "A3SP", &dma0_device, },
941 { "A3SP", &dma1_device, },
942 { "A3SP", &dma2_device, },
943 { "A3SP", &usb_dma0_device, },
944 { "A3SP", &usb_dma1_device, },
945 { "A4R", &iic0_device, },
946 { "A4R", &veu0_device, },
947 { "A4R", &veu1_device, },
948 { "A4R", &veu2_device, },
949 { "A4R", &veu3_device, },
950 { "A4R", &jpu_device, },
8e8236a9 951 { "A4R", &tmu0_device, },
c37b7a7b
RW		 952 };
953
e7e59a4b 954 sh7372_init_pm_domains();
f7dadb37 955
2b7eda63
MD		 956 platform_add_devices(sh7372_early_devices,
957 ARRAY_SIZE(sh7372_early_devices));
934e4078
MD		 958
959 platform_add_devices(sh7372_late_devices,
960 ARRAY_SIZE(sh7372_late_devices));
33afebf3 961
ac18e02d
RW		 962 rmobile_add_devices_to_domains(domain_devices,
963 ARRAY_SIZE(domain_devices));
2b7eda63
MD		 964}
965
6bb27d73 966void __init sh7372_earlytimer_init(void)
17254bff
MD		 967{
968 sh7372_clock_init();
969 shmobile_earlytimer_init();
970}
971
2b7eda63
MD		 972void __init sh7372_add_early_devices(void)
973{
2b7eda63
MD		 974 early_platform_add_devices(sh7372_early_devices,
975 ARRAY_SIZE(sh7372_early_devices));
5d7220ec
MD		 976
977 /* setup early console here as well */
978 shmobile_setup_console();
2b7eda63 979}
3b7b7055
MD		 980
981#ifdef CONFIG_USE_OF
982
983void __init sh7372_add_early_devices_dt(void)
984{
39b22e20 985 shmobile_init_delay();
3b7b7055 986
1fba31f0 987 sh7372_add_early_devices();
3b7b7055
MD		 988}
989
3b7b7055
MD		 990void __init sh7372_add_standard_devices_dt(void)
991{
992 /* clocks are setup late during boot in the case of DT */
993 sh7372_clock_init();
994
995 platform_add_devices(sh7372_early_devices,
996 ARRAY_SIZE(sh7372_early_devices));
997
975e5af9 998 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
3b7b7055
MD		 999}
1000
1001static const char *sh7372_boards_compat_dt[] __initdata = {
1002 "renesas,sh7372",
1003 NULL,
1004};
1005
1006DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1007 .map_io = sh7372_map_io,
1008 .init_early = sh7372_add_early_devices_dt,
3b7b7055
MD		 1009 .init_irq = sh7372_init_irq,
1010 .handle_irq = shmobile_handle_irq_intc,
1011 .init_machine = sh7372_add_standard_devices_dt,
27c1bb20 1012 .init_late = shmobile_init_late,
3b7b7055
MD		 1013 .dt_compat = sh7372_boards_compat_dt,
1014MACHINE_END
1015
1016#endif /* CONFIG_USE_OF */
Linux kernel - Deliverables
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