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6d9598e2 MD |
1 | /* |
2 | * sh73a0 processor support | |
3 | * | |
4 | * Copyright (C) 2010 Takashi Yoshii | |
5 | * Copyright (C) 2010 Magnus Damm | |
6 | * Copyright (C) 2008 Yoshihiro Shimoda | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | */ | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/platform_device.h> | |
48609533 | 26 | #include <linux/of_platform.h> |
6d9598e2 MD |
27 | #include <linux/delay.h> |
28 | #include <linux/input.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/serial_sci.h> | |
681e1b3e | 31 | #include <linux/sh_dma.h> |
6d9598e2 MD |
32 | #include <linux/sh_intc.h> |
33 | #include <linux/sh_timer.h> | |
9a27dee7 | 34 | #include <linux/platform_data/sh_ipmmu.h> |
341eb546 | 35 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> |
6088b422 | 36 | #include <mach/dma-register.h> |
250a2723 | 37 | #include <mach/irqs.h> |
681e1b3e | 38 | #include <mach/sh73a0.h> |
50e15c34 | 39 | #include <mach/common.h> |
6d9598e2 | 40 | #include <asm/mach-types.h> |
50e15c34 | 41 | #include <asm/mach/map.h> |
6d9598e2 | 42 | #include <asm/mach/arch.h> |
3be26fdb | 43 | #include <asm/mach/time.h> |
6d9598e2 | 44 | |
50e15c34 MD |
45 | static struct map_desc sh73a0_io_desc[] __initdata = { |
46 | /* create a 1:1 entity map for 0xe6xxxxxx | |
47 | * used by CPGA, INTC and PFC. | |
48 | */ | |
49 | { | |
50 | .virtual = 0xe6000000, | |
51 | .pfn = __phys_to_pfn(0xe6000000), | |
52 | .length = 256 << 20, | |
53 | .type = MT_DEVICE_NONSHARED | |
54 | }, | |
55 | }; | |
56 | ||
57 | void __init sh73a0_map_io(void) | |
58 | { | |
59 | iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); | |
60 | } | |
61 | ||
474f6758 MD |
62 | /* PFC */ |
63 | static struct resource pfc_resources[] __initdata = { | |
64 | DEFINE_RES_MEM(0xe6050000, 0x8000), | |
65 | DEFINE_RES_MEM(0xe605801c, 0x000c), | |
994d66a4 LP |
66 | }; |
67 | ||
68 | void __init sh73a0_pinmux_init(void) | |
69 | { | |
474f6758 MD |
70 | platform_device_register_simple("pfc-sh73a0", -1, pfc_resources, |
71 | ARRAY_SIZE(pfc_resources)); | |
994d66a4 LP |
72 | } |
73 | ||
6d9598e2 MD |
74 | static struct plat_sci_port scif0_platform_data = { |
75 | .mapbase = 0xe6c40000, | |
76 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
77 | .scscr = SCSCR_RE | SCSCR_TE, |
78 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
79 | .type = PORT_SCIFA, |
80 | .irqs = { gic_spi(72), gic_spi(72), | |
81 | gic_spi(72), gic_spi(72) }, | |
82 | }; | |
83 | ||
84 | static struct platform_device scif0_device = { | |
85 | .name = "sh-sci", | |
86 | .id = 0, | |
87 | .dev = { | |
88 | .platform_data = &scif0_platform_data, | |
89 | }, | |
90 | }; | |
91 | ||
92 | static struct plat_sci_port scif1_platform_data = { | |
93 | .mapbase = 0xe6c50000, | |
94 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
95 | .scscr = SCSCR_RE | SCSCR_TE, |
96 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
97 | .type = PORT_SCIFA, |
98 | .irqs = { gic_spi(73), gic_spi(73), | |
99 | gic_spi(73), gic_spi(73) }, | |
100 | }; | |
101 | ||
102 | static struct platform_device scif1_device = { | |
103 | .name = "sh-sci", | |
104 | .id = 1, | |
105 | .dev = { | |
106 | .platform_data = &scif1_platform_data, | |
107 | }, | |
108 | }; | |
109 | ||
110 | static struct plat_sci_port scif2_platform_data = { | |
111 | .mapbase = 0xe6c60000, | |
112 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
113 | .scscr = SCSCR_RE | SCSCR_TE, |
114 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
115 | .type = PORT_SCIFA, |
116 | .irqs = { gic_spi(74), gic_spi(74), | |
117 | gic_spi(74), gic_spi(74) }, | |
118 | }; | |
119 | ||
120 | static struct platform_device scif2_device = { | |
121 | .name = "sh-sci", | |
122 | .id = 2, | |
123 | .dev = { | |
124 | .platform_data = &scif2_platform_data, | |
125 | }, | |
126 | }; | |
127 | ||
128 | static struct plat_sci_port scif3_platform_data = { | |
129 | .mapbase = 0xe6c70000, | |
130 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
131 | .scscr = SCSCR_RE | SCSCR_TE, |
132 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
133 | .type = PORT_SCIFA, |
134 | .irqs = { gic_spi(75), gic_spi(75), | |
135 | gic_spi(75), gic_spi(75) }, | |
136 | }; | |
137 | ||
138 | static struct platform_device scif3_device = { | |
139 | .name = "sh-sci", | |
140 | .id = 3, | |
141 | .dev = { | |
142 | .platform_data = &scif3_platform_data, | |
143 | }, | |
144 | }; | |
145 | ||
146 | static struct plat_sci_port scif4_platform_data = { | |
147 | .mapbase = 0xe6c80000, | |
148 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
149 | .scscr = SCSCR_RE | SCSCR_TE, |
150 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
151 | .type = PORT_SCIFA, |
152 | .irqs = { gic_spi(78), gic_spi(78), | |
153 | gic_spi(78), gic_spi(78) }, | |
154 | }; | |
155 | ||
156 | static struct platform_device scif4_device = { | |
157 | .name = "sh-sci", | |
158 | .id = 4, | |
159 | .dev = { | |
160 | .platform_data = &scif4_platform_data, | |
161 | }, | |
162 | }; | |
163 | ||
164 | static struct plat_sci_port scif5_platform_data = { | |
165 | .mapbase = 0xe6cb0000, | |
166 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
167 | .scscr = SCSCR_RE | SCSCR_TE, |
168 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
169 | .type = PORT_SCIFA, |
170 | .irqs = { gic_spi(79), gic_spi(79), | |
171 | gic_spi(79), gic_spi(79) }, | |
172 | }; | |
173 | ||
174 | static struct platform_device scif5_device = { | |
175 | .name = "sh-sci", | |
176 | .id = 5, | |
177 | .dev = { | |
178 | .platform_data = &scif5_platform_data, | |
179 | }, | |
180 | }; | |
181 | ||
182 | static struct plat_sci_port scif6_platform_data = { | |
183 | .mapbase = 0xe6cc0000, | |
184 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
185 | .scscr = SCSCR_RE | SCSCR_TE, |
186 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
187 | .type = PORT_SCIFA, |
188 | .irqs = { gic_spi(156), gic_spi(156), | |
189 | gic_spi(156), gic_spi(156) }, | |
190 | }; | |
191 | ||
192 | static struct platform_device scif6_device = { | |
193 | .name = "sh-sci", | |
194 | .id = 6, | |
195 | .dev = { | |
196 | .platform_data = &scif6_platform_data, | |
197 | }, | |
198 | }; | |
199 | ||
200 | static struct plat_sci_port scif7_platform_data = { | |
201 | .mapbase = 0xe6cd0000, | |
202 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
203 | .scscr = SCSCR_RE | SCSCR_TE, |
204 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
205 | .type = PORT_SCIFA, |
206 | .irqs = { gic_spi(143), gic_spi(143), | |
207 | gic_spi(143), gic_spi(143) }, | |
208 | }; | |
209 | ||
210 | static struct platform_device scif7_device = { | |
211 | .name = "sh-sci", | |
212 | .id = 7, | |
213 | .dev = { | |
214 | .platform_data = &scif7_platform_data, | |
215 | }, | |
216 | }; | |
217 | ||
218 | static struct plat_sci_port scif8_platform_data = { | |
219 | .mapbase = 0xe6c30000, | |
220 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
221 | .scscr = SCSCR_RE | SCSCR_TE, |
222 | .scbrr_algo_id = SCBRR_ALGO_4, | |
6d9598e2 MD |
223 | .type = PORT_SCIFB, |
224 | .irqs = { gic_spi(80), gic_spi(80), | |
225 | gic_spi(80), gic_spi(80) }, | |
226 | }; | |
227 | ||
228 | static struct platform_device scif8_device = { | |
229 | .name = "sh-sci", | |
230 | .id = 8, | |
231 | .dev = { | |
232 | .platform_data = &scif8_platform_data, | |
233 | }, | |
234 | }; | |
235 | ||
236 | static struct sh_timer_config cmt10_platform_data = { | |
237 | .name = "CMT10", | |
238 | .channel_offset = 0x10, | |
239 | .timer_bit = 0, | |
5600a848 | 240 | .clockevent_rating = 80, |
6d9598e2 MD |
241 | .clocksource_rating = 125, |
242 | }; | |
243 | ||
244 | static struct resource cmt10_resources[] = { | |
245 | [0] = { | |
246 | .name = "CMT10", | |
247 | .start = 0xe6138010, | |
248 | .end = 0xe613801b, | |
249 | .flags = IORESOURCE_MEM, | |
250 | }, | |
251 | [1] = { | |
252 | .start = gic_spi(65), | |
253 | .flags = IORESOURCE_IRQ, | |
254 | }, | |
255 | }; | |
256 | ||
257 | static struct platform_device cmt10_device = { | |
258 | .name = "sh_cmt", | |
259 | .id = 10, | |
260 | .dev = { | |
261 | .platform_data = &cmt10_platform_data, | |
262 | }, | |
263 | .resource = cmt10_resources, | |
264 | .num_resources = ARRAY_SIZE(cmt10_resources), | |
265 | }; | |
266 | ||
5010f3db MD |
267 | /* TMU */ |
268 | static struct sh_timer_config tmu00_platform_data = { | |
269 | .name = "TMU00", | |
270 | .channel_offset = 0x4, | |
271 | .timer_bit = 0, | |
272 | .clockevent_rating = 200, | |
273 | }; | |
274 | ||
275 | static struct resource tmu00_resources[] = { | |
abbec5f4 | 276 | [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"), |
5010f3db MD |
277 | [1] = { |
278 | .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ | |
279 | .flags = IORESOURCE_IRQ, | |
280 | }, | |
281 | }; | |
282 | ||
283 | static struct platform_device tmu00_device = { | |
284 | .name = "sh_tmu", | |
285 | .id = 0, | |
286 | .dev = { | |
287 | .platform_data = &tmu00_platform_data, | |
288 | }, | |
289 | .resource = tmu00_resources, | |
290 | .num_resources = ARRAY_SIZE(tmu00_resources), | |
291 | }; | |
292 | ||
293 | static struct sh_timer_config tmu01_platform_data = { | |
294 | .name = "TMU01", | |
295 | .channel_offset = 0x10, | |
296 | .timer_bit = 1, | |
297 | .clocksource_rating = 200, | |
298 | }; | |
299 | ||
300 | static struct resource tmu01_resources[] = { | |
abbec5f4 | 301 | [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"), |
5010f3db MD |
302 | [1] = { |
303 | .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ | |
304 | .flags = IORESOURCE_IRQ, | |
305 | }, | |
306 | }; | |
307 | ||
308 | static struct platform_device tmu01_device = { | |
309 | .name = "sh_tmu", | |
310 | .id = 1, | |
311 | .dev = { | |
312 | .platform_data = &tmu01_platform_data, | |
313 | }, | |
314 | .resource = tmu01_resources, | |
315 | .num_resources = ARRAY_SIZE(tmu01_resources), | |
316 | }; | |
317 | ||
b028f94b | 318 | static struct resource i2c0_resources[] = { |
abbec5f4 | 319 | [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"), |
b028f94b YT |
320 | [1] = { |
321 | .start = gic_spi(167), | |
322 | .end = gic_spi(170), | |
323 | .flags = IORESOURCE_IRQ, | |
324 | }, | |
325 | }; | |
326 | ||
327 | static struct resource i2c1_resources[] = { | |
abbec5f4 | 328 | [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"), |
b028f94b YT |
329 | [1] = { |
330 | .start = gic_spi(51), | |
331 | .end = gic_spi(54), | |
332 | .flags = IORESOURCE_IRQ, | |
333 | }, | |
334 | }; | |
335 | ||
336 | static struct resource i2c2_resources[] = { | |
abbec5f4 | 337 | [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"), |
b028f94b YT |
338 | [1] = { |
339 | .start = gic_spi(171), | |
340 | .end = gic_spi(174), | |
341 | .flags = IORESOURCE_IRQ, | |
342 | }, | |
343 | }; | |
344 | ||
345 | static struct resource i2c3_resources[] = { | |
abbec5f4 | 346 | [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"), |
b028f94b YT |
347 | [1] = { |
348 | .start = gic_spi(183), | |
349 | .end = gic_spi(186), | |
350 | .flags = IORESOURCE_IRQ, | |
351 | }, | |
352 | }; | |
353 | ||
354 | static struct resource i2c4_resources[] = { | |
abbec5f4 | 355 | [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"), |
b028f94b YT |
356 | [1] = { |
357 | .start = gic_spi(187), | |
358 | .end = gic_spi(190), | |
359 | .flags = IORESOURCE_IRQ, | |
360 | }, | |
361 | }; | |
362 | ||
363 | static struct platform_device i2c0_device = { | |
364 | .name = "i2c-sh_mobile", | |
365 | .id = 0, | |
366 | .resource = i2c0_resources, | |
367 | .num_resources = ARRAY_SIZE(i2c0_resources), | |
368 | }; | |
369 | ||
370 | static struct platform_device i2c1_device = { | |
371 | .name = "i2c-sh_mobile", | |
372 | .id = 1, | |
373 | .resource = i2c1_resources, | |
374 | .num_resources = ARRAY_SIZE(i2c1_resources), | |
375 | }; | |
376 | ||
377 | static struct platform_device i2c2_device = { | |
378 | .name = "i2c-sh_mobile", | |
379 | .id = 2, | |
380 | .resource = i2c2_resources, | |
381 | .num_resources = ARRAY_SIZE(i2c2_resources), | |
382 | }; | |
383 | ||
384 | static struct platform_device i2c3_device = { | |
385 | .name = "i2c-sh_mobile", | |
386 | .id = 3, | |
387 | .resource = i2c3_resources, | |
388 | .num_resources = ARRAY_SIZE(i2c3_resources), | |
389 | }; | |
390 | ||
391 | static struct platform_device i2c4_device = { | |
392 | .name = "i2c-sh_mobile", | |
393 | .id = 4, | |
394 | .resource = i2c4_resources, | |
395 | .num_resources = ARRAY_SIZE(i2c4_resources), | |
396 | }; | |
397 | ||
681e1b3e MD |
398 | static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { |
399 | { | |
400 | .slave_id = SHDMA_SLAVE_SCIF0_TX, | |
401 | .addr = 0xe6c40020, | |
402 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
403 | .mid_rid = 0x21, | |
404 | }, { | |
405 | .slave_id = SHDMA_SLAVE_SCIF0_RX, | |
406 | .addr = 0xe6c40024, | |
407 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
408 | .mid_rid = 0x22, | |
409 | }, { | |
410 | .slave_id = SHDMA_SLAVE_SCIF1_TX, | |
411 | .addr = 0xe6c50020, | |
412 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
413 | .mid_rid = 0x25, | |
414 | }, { | |
415 | .slave_id = SHDMA_SLAVE_SCIF1_RX, | |
416 | .addr = 0xe6c50024, | |
417 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
418 | .mid_rid = 0x26, | |
419 | }, { | |
420 | .slave_id = SHDMA_SLAVE_SCIF2_TX, | |
421 | .addr = 0xe6c60020, | |
422 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
423 | .mid_rid = 0x29, | |
424 | }, { | |
425 | .slave_id = SHDMA_SLAVE_SCIF2_RX, | |
426 | .addr = 0xe6c60024, | |
427 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
428 | .mid_rid = 0x2a, | |
429 | }, { | |
430 | .slave_id = SHDMA_SLAVE_SCIF3_TX, | |
431 | .addr = 0xe6c70020, | |
432 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
433 | .mid_rid = 0x2d, | |
434 | }, { | |
435 | .slave_id = SHDMA_SLAVE_SCIF3_RX, | |
436 | .addr = 0xe6c70024, | |
437 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
438 | .mid_rid = 0x2e, | |
439 | }, { | |
440 | .slave_id = SHDMA_SLAVE_SCIF4_TX, | |
441 | .addr = 0xe6c80020, | |
442 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
443 | .mid_rid = 0x39, | |
444 | }, { | |
445 | .slave_id = SHDMA_SLAVE_SCIF4_RX, | |
446 | .addr = 0xe6c80024, | |
447 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
448 | .mid_rid = 0x3a, | |
449 | }, { | |
450 | .slave_id = SHDMA_SLAVE_SCIF5_TX, | |
451 | .addr = 0xe6cb0020, | |
452 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
453 | .mid_rid = 0x35, | |
454 | }, { | |
455 | .slave_id = SHDMA_SLAVE_SCIF5_RX, | |
456 | .addr = 0xe6cb0024, | |
457 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
458 | .mid_rid = 0x36, | |
459 | }, { | |
460 | .slave_id = SHDMA_SLAVE_SCIF6_TX, | |
461 | .addr = 0xe6cc0020, | |
462 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
463 | .mid_rid = 0x1d, | |
464 | }, { | |
465 | .slave_id = SHDMA_SLAVE_SCIF6_RX, | |
466 | .addr = 0xe6cc0024, | |
467 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
468 | .mid_rid = 0x1e, | |
469 | }, { | |
470 | .slave_id = SHDMA_SLAVE_SCIF7_TX, | |
471 | .addr = 0xe6cd0020, | |
472 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
473 | .mid_rid = 0x19, | |
474 | }, { | |
475 | .slave_id = SHDMA_SLAVE_SCIF7_RX, | |
476 | .addr = 0xe6cd0024, | |
477 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
478 | .mid_rid = 0x1a, | |
479 | }, { | |
480 | .slave_id = SHDMA_SLAVE_SCIF8_TX, | |
481 | .addr = 0xe6c30040, | |
482 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
483 | .mid_rid = 0x3d, | |
484 | }, { | |
485 | .slave_id = SHDMA_SLAVE_SCIF8_RX, | |
486 | .addr = 0xe6c30060, | |
487 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
488 | .mid_rid = 0x3e, | |
489 | }, { | |
490 | .slave_id = SHDMA_SLAVE_SDHI0_TX, | |
491 | .addr = 0xee100030, | |
492 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
493 | .mid_rid = 0xc1, | |
494 | }, { | |
495 | .slave_id = SHDMA_SLAVE_SDHI0_RX, | |
496 | .addr = 0xee100030, | |
497 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
498 | .mid_rid = 0xc2, | |
499 | }, { | |
500 | .slave_id = SHDMA_SLAVE_SDHI1_TX, | |
501 | .addr = 0xee120030, | |
502 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
503 | .mid_rid = 0xc9, | |
504 | }, { | |
505 | .slave_id = SHDMA_SLAVE_SDHI1_RX, | |
506 | .addr = 0xee120030, | |
507 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
508 | .mid_rid = 0xca, | |
509 | }, { | |
510 | .slave_id = SHDMA_SLAVE_SDHI2_TX, | |
511 | .addr = 0xee140030, | |
512 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
513 | .mid_rid = 0xcd, | |
514 | }, { | |
515 | .slave_id = SHDMA_SLAVE_SDHI2_RX, | |
516 | .addr = 0xee140030, | |
517 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
518 | .mid_rid = 0xce, | |
519 | }, { | |
520 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | |
521 | .addr = 0xe6bd0034, | |
522 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
523 | .mid_rid = 0xd1, | |
524 | }, { | |
525 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | |
526 | .addr = 0xe6bd0034, | |
527 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
528 | .mid_rid = 0xd2, | |
529 | }, | |
530 | }; | |
531 | ||
532 | #define DMAE_CHANNEL(_offset) \ | |
533 | { \ | |
534 | .offset = _offset - 0x20, \ | |
535 | .dmars = _offset - 0x20 + 0x40, \ | |
536 | } | |
537 | ||
538 | static const struct sh_dmae_channel sh73a0_dmae_channels[] = { | |
539 | DMAE_CHANNEL(0x8000), | |
540 | DMAE_CHANNEL(0x8080), | |
541 | DMAE_CHANNEL(0x8100), | |
542 | DMAE_CHANNEL(0x8180), | |
543 | DMAE_CHANNEL(0x8200), | |
544 | DMAE_CHANNEL(0x8280), | |
545 | DMAE_CHANNEL(0x8300), | |
546 | DMAE_CHANNEL(0x8380), | |
547 | DMAE_CHANNEL(0x8400), | |
548 | DMAE_CHANNEL(0x8480), | |
549 | DMAE_CHANNEL(0x8500), | |
550 | DMAE_CHANNEL(0x8580), | |
551 | DMAE_CHANNEL(0x8600), | |
552 | DMAE_CHANNEL(0x8680), | |
553 | DMAE_CHANNEL(0x8700), | |
554 | DMAE_CHANNEL(0x8780), | |
555 | DMAE_CHANNEL(0x8800), | |
556 | DMAE_CHANNEL(0x8880), | |
557 | DMAE_CHANNEL(0x8900), | |
558 | DMAE_CHANNEL(0x8980), | |
559 | }; | |
560 | ||
681e1b3e MD |
561 | static struct sh_dmae_pdata sh73a0_dmae_platform_data = { |
562 | .slave = sh73a0_dmae_slaves, | |
563 | .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), | |
564 | .channel = sh73a0_dmae_channels, | |
565 | .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), | |
6088b422 KM |
566 | .ts_low_shift = TS_LOW_SHIFT, |
567 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | |
568 | .ts_high_shift = TS_HI_SHIFT, | |
569 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | |
570 | .ts_shift = dma_ts_shift, | |
571 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | |
681e1b3e MD |
572 | .dmaor_init = DMAOR_DME, |
573 | }; | |
574 | ||
575 | static struct resource sh73a0_dmae_resources[] = { | |
abbec5f4 | 576 | DEFINE_RES_MEM(0xfe000020, 0x89e0), |
681e1b3e | 577 | { |
20052462 | 578 | .name = "error_irq", |
681e1b3e MD |
579 | .start = gic_spi(129), |
580 | .end = gic_spi(129), | |
581 | .flags = IORESOURCE_IRQ, | |
582 | }, | |
583 | { | |
584 | /* IRQ for channels 0-19 */ | |
585 | .start = gic_spi(109), | |
586 | .end = gic_spi(128), | |
587 | .flags = IORESOURCE_IRQ, | |
588 | }, | |
589 | }; | |
590 | ||
591 | static struct platform_device dma0_device = { | |
592 | .name = "sh-dma-engine", | |
593 | .id = 0, | |
594 | .resource = sh73a0_dmae_resources, | |
595 | .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), | |
596 | .dev = { | |
597 | .platform_data = &sh73a0_dmae_platform_data, | |
598 | }, | |
599 | }; | |
600 | ||
832290b2 KM |
601 | /* MPDMAC */ |
602 | static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { | |
603 | { | |
604 | .slave_id = SHDMA_SLAVE_FSI2A_RX, | |
605 | .addr = 0xec230020, | |
606 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
607 | .mid_rid = 0xd6, /* CHECK ME */ | |
608 | }, { | |
609 | .slave_id = SHDMA_SLAVE_FSI2A_TX, | |
610 | .addr = 0xec230024, | |
611 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
612 | .mid_rid = 0xd5, /* CHECK ME */ | |
613 | }, { | |
614 | .slave_id = SHDMA_SLAVE_FSI2C_RX, | |
615 | .addr = 0xec230060, | |
616 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
617 | .mid_rid = 0xda, /* CHECK ME */ | |
618 | }, { | |
619 | .slave_id = SHDMA_SLAVE_FSI2C_TX, | |
620 | .addr = 0xec230064, | |
621 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
622 | .mid_rid = 0xd9, /* CHECK ME */ | |
623 | }, { | |
624 | .slave_id = SHDMA_SLAVE_FSI2B_RX, | |
625 | .addr = 0xec240020, | |
626 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
627 | .mid_rid = 0x8e, /* CHECK ME */ | |
628 | }, { | |
629 | .slave_id = SHDMA_SLAVE_FSI2B_TX, | |
630 | .addr = 0xec240024, | |
631 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
632 | .mid_rid = 0x8d, /* CHECK ME */ | |
633 | }, { | |
634 | .slave_id = SHDMA_SLAVE_FSI2D_RX, | |
635 | .addr = 0xec240060, | |
636 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
637 | .mid_rid = 0x9a, /* CHECK ME */ | |
638 | }, | |
639 | }; | |
640 | ||
641 | #define MPDMA_CHANNEL(a, b, c) \ | |
642 | { \ | |
643 | .offset = a, \ | |
644 | .dmars = b, \ | |
645 | .dmars_bit = c, \ | |
646 | .chclr_offset = (0x220 - 0x20) + a \ | |
647 | } | |
648 | ||
649 | static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { | |
650 | MPDMA_CHANNEL(0x00, 0, 0), | |
651 | MPDMA_CHANNEL(0x10, 0, 8), | |
652 | MPDMA_CHANNEL(0x20, 4, 0), | |
653 | MPDMA_CHANNEL(0x30, 4, 8), | |
654 | MPDMA_CHANNEL(0x50, 8, 0), | |
655 | MPDMA_CHANNEL(0x70, 8, 8), | |
656 | }; | |
657 | ||
658 | static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { | |
659 | .slave = sh73a0_mpdma_slaves, | |
660 | .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), | |
661 | .channel = sh73a0_mpdma_channels, | |
662 | .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), | |
6088b422 KM |
663 | .ts_low_shift = TS_LOW_SHIFT, |
664 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | |
665 | .ts_high_shift = TS_HI_SHIFT, | |
666 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | |
667 | .ts_shift = dma_ts_shift, | |
668 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | |
832290b2 KM |
669 | .dmaor_init = DMAOR_DME, |
670 | .chclr_present = 1, | |
671 | }; | |
672 | ||
673 | /* Resource order important! */ | |
674 | static struct resource sh73a0_mpdma_resources[] = { | |
abbec5f4 SH |
675 | /* Channel registers and DMAOR */ |
676 | DEFINE_RES_MEM(0xec618020, 0x270), | |
677 | /* DMARSx */ | |
678 | DEFINE_RES_MEM(0xec619000, 0xc), | |
832290b2 KM |
679 | { |
680 | .name = "error_irq", | |
681 | .start = gic_spi(181), | |
682 | .end = gic_spi(181), | |
683 | .flags = IORESOURCE_IRQ, | |
684 | }, | |
685 | { | |
686 | /* IRQ for channels 0-5 */ | |
687 | .start = gic_spi(175), | |
688 | .end = gic_spi(180), | |
689 | .flags = IORESOURCE_IRQ, | |
690 | }, | |
691 | }; | |
692 | ||
693 | static struct platform_device mpdma0_device = { | |
694 | .name = "sh-dma-engine", | |
695 | .id = 1, | |
696 | .resource = sh73a0_mpdma_resources, | |
697 | .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), | |
698 | .dev = { | |
699 | .platform_data = &sh73a0_mpdma_platform_data, | |
700 | }, | |
701 | }; | |
702 | ||
f23f5be0 TK |
703 | static struct resource pmu_resources[] = { |
704 | [0] = { | |
705 | .start = gic_spi(55), | |
706 | .end = gic_spi(55), | |
707 | .flags = IORESOURCE_IRQ, | |
708 | }, | |
709 | [1] = { | |
710 | .start = gic_spi(56), | |
711 | .end = gic_spi(56), | |
712 | .flags = IORESOURCE_IRQ, | |
713 | }, | |
714 | }; | |
715 | ||
716 | static struct platform_device pmu_device = { | |
717 | .name = "arm-pmu", | |
718 | .id = -1, | |
719 | .num_resources = ARRAY_SIZE(pmu_resources), | |
720 | .resource = pmu_resources, | |
721 | }; | |
722 | ||
9a27dee7 HE |
723 | /* an IPMMU module for ICB */ |
724 | static struct resource ipmmu_resources[] = { | |
abbec5f4 | 725 | DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"), |
9a27dee7 HE |
726 | }; |
727 | ||
728 | static const char * const ipmmu_dev_names[] = { | |
729 | "sh_mobile_lcdc_fb.0", | |
730 | }; | |
731 | ||
732 | static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { | |
733 | .dev_names = ipmmu_dev_names, | |
734 | .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), | |
735 | }; | |
736 | ||
737 | static struct platform_device ipmmu_device = { | |
738 | .name = "ipmmu", | |
739 | .id = -1, | |
740 | .dev = { | |
741 | .platform_data = &ipmmu_platform_data, | |
742 | }, | |
743 | .resource = ipmmu_resources, | |
744 | .num_resources = ARRAY_SIZE(ipmmu_resources), | |
745 | }; | |
746 | ||
1461f8b6 | 747 | static struct renesas_intc_irqpin_config irqpin0_platform_data = { |
341eb546 MD |
748 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ |
749 | }; | |
750 | ||
751 | static struct resource irqpin0_resources[] = { | |
752 | DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ | |
753 | DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ | |
754 | DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ | |
755 | DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ | |
756 | DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ | |
757 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ | |
758 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ | |
759 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ | |
760 | DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ | |
761 | DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ | |
762 | DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ | |
763 | DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ | |
764 | DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ | |
765 | }; | |
766 | ||
767 | static struct platform_device irqpin0_device = { | |
768 | .name = "renesas_intc_irqpin", | |
769 | .id = 0, | |
770 | .resource = irqpin0_resources, | |
771 | .num_resources = ARRAY_SIZE(irqpin0_resources), | |
772 | .dev = { | |
773 | .platform_data = &irqpin0_platform_data, | |
774 | }, | |
775 | }; | |
776 | ||
1461f8b6 | 777 | static struct renesas_intc_irqpin_config irqpin1_platform_data = { |
341eb546 MD |
778 | .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ |
779 | .control_parent = true, /* Disable spurious IRQ10 */ | |
780 | }; | |
781 | ||
782 | static struct resource irqpin1_resources[] = { | |
783 | DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ | |
784 | DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ | |
785 | DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ | |
786 | DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ | |
787 | DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ | |
788 | DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ | |
789 | DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ | |
790 | DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ | |
791 | DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ | |
792 | DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ | |
793 | DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ | |
794 | DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ | |
795 | DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ | |
796 | }; | |
797 | ||
798 | static struct platform_device irqpin1_device = { | |
799 | .name = "renesas_intc_irqpin", | |
800 | .id = 1, | |
801 | .resource = irqpin1_resources, | |
802 | .num_resources = ARRAY_SIZE(irqpin1_resources), | |
803 | .dev = { | |
804 | .platform_data = &irqpin1_platform_data, | |
805 | }, | |
806 | }; | |
807 | ||
1461f8b6 | 808 | static struct renesas_intc_irqpin_config irqpin2_platform_data = { |
341eb546 MD |
809 | .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ |
810 | }; | |
811 | ||
812 | static struct resource irqpin2_resources[] = { | |
813 | DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ | |
814 | DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ | |
815 | DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ | |
816 | DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ | |
817 | DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ | |
818 | DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ | |
819 | DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ | |
820 | DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ | |
821 | DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ | |
822 | DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ | |
823 | DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ | |
824 | DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ | |
825 | DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ | |
826 | }; | |
827 | ||
828 | static struct platform_device irqpin2_device = { | |
829 | .name = "renesas_intc_irqpin", | |
830 | .id = 2, | |
831 | .resource = irqpin2_resources, | |
832 | .num_resources = ARRAY_SIZE(irqpin2_resources), | |
833 | .dev = { | |
834 | .platform_data = &irqpin2_platform_data, | |
835 | }, | |
836 | }; | |
837 | ||
1461f8b6 | 838 | static struct renesas_intc_irqpin_config irqpin3_platform_data = { |
341eb546 MD |
839 | .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ |
840 | }; | |
841 | ||
842 | static struct resource irqpin3_resources[] = { | |
843 | DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ | |
844 | DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ | |
845 | DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ | |
846 | DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ | |
847 | DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ | |
848 | DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ | |
849 | DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ | |
850 | DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ | |
851 | DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ | |
852 | DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ | |
853 | DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ | |
854 | DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ | |
855 | DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ | |
856 | }; | |
857 | ||
858 | static struct platform_device irqpin3_device = { | |
859 | .name = "renesas_intc_irqpin", | |
860 | .id = 3, | |
861 | .resource = irqpin3_resources, | |
862 | .num_resources = ARRAY_SIZE(irqpin3_resources), | |
863 | .dev = { | |
864 | .platform_data = &irqpin3_platform_data, | |
865 | }, | |
866 | }; | |
867 | ||
3b00f934 | 868 | static struct platform_device *sh73a0_devices_dt[] __initdata = { |
6d9598e2 MD |
869 | &scif0_device, |
870 | &scif1_device, | |
871 | &scif2_device, | |
872 | &scif3_device, | |
873 | &scif4_device, | |
874 | &scif5_device, | |
875 | &scif6_device, | |
876 | &scif7_device, | |
877 | &scif8_device, | |
878 | &cmt10_device, | |
48609533 SH |
879 | }; |
880 | ||
881 | static struct platform_device *sh73a0_early_devices[] __initdata = { | |
5010f3db MD |
882 | &tmu00_device, |
883 | &tmu01_device, | |
9a27dee7 | 884 | &ipmmu_device, |
6d9598e2 MD |
885 | }; |
886 | ||
b028f94b YT |
887 | static struct platform_device *sh73a0_late_devices[] __initdata = { |
888 | &i2c0_device, | |
889 | &i2c1_device, | |
890 | &i2c2_device, | |
891 | &i2c3_device, | |
892 | &i2c4_device, | |
681e1b3e | 893 | &dma0_device, |
832290b2 | 894 | &mpdma0_device, |
f23f5be0 | 895 | &pmu_device, |
341eb546 MD |
896 | &irqpin0_device, |
897 | &irqpin1_device, | |
898 | &irqpin2_device, | |
899 | &irqpin3_device, | |
b028f94b YT |
900 | }; |
901 | ||
0a4b04dc | 902 | #define SRCR2 IOMEM(0xe61580b0) |
681e1b3e | 903 | |
6d9598e2 MD |
904 | void __init sh73a0_add_standard_devices(void) |
905 | { | |
681e1b3e MD |
906 | /* Clear software reset bit on SY-DMAC module */ |
907 | __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); | |
908 | ||
3b00f934 SH |
909 | platform_add_devices(sh73a0_devices_dt, |
910 | ARRAY_SIZE(sh73a0_devices_dt)); | |
6d9598e2 MD |
911 | platform_add_devices(sh73a0_early_devices, |
912 | ARRAY_SIZE(sh73a0_early_devices)); | |
b028f94b YT |
913 | platform_add_devices(sh73a0_late_devices, |
914 | ARRAY_SIZE(sh73a0_late_devices)); | |
6d9598e2 MD |
915 | } |
916 | ||
43cb8cb7 MD |
917 | void __init sh73a0_init_delay(void) |
918 | { | |
919 | shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ | |
920 | } | |
921 | ||
d6720003 KM |
922 | /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ |
923 | void __init __weak sh73a0_register_twd(void) { } | |
924 | ||
6bb27d73 | 925 | void __init sh73a0_earlytimer_init(void) |
3be26fdb | 926 | { |
43cb8cb7 | 927 | sh73a0_init_delay(); |
3be26fdb MD |
928 | sh73a0_clock_init(); |
929 | shmobile_earlytimer_init(); | |
d6720003 | 930 | sh73a0_register_twd(); |
3be26fdb MD |
931 | } |
932 | ||
6d9598e2 MD |
933 | void __init sh73a0_add_early_devices(void) |
934 | { | |
3b00f934 SH |
935 | early_platform_add_devices(sh73a0_devices_dt, |
936 | ARRAY_SIZE(sh73a0_devices_dt)); | |
6d9598e2 MD |
937 | early_platform_add_devices(sh73a0_early_devices, |
938 | ARRAY_SIZE(sh73a0_early_devices)); | |
50e15c34 MD |
939 | |
940 | /* setup early console here as well */ | |
941 | shmobile_setup_console(); | |
6d9598e2 | 942 | } |
48609533 SH |
943 | |
944 | #ifdef CONFIG_USE_OF | |
945 | ||
48609533 SH |
946 | void __init sh73a0_add_standard_devices_dt(void) |
947 | { | |
d2347382 GL |
948 | struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; |
949 | ||
48609533 SH |
950 | /* clocks are setup late during boot in the case of DT */ |
951 | sh73a0_clock_init(); | |
952 | ||
3b00f934 SH |
953 | platform_add_devices(sh73a0_devices_dt, |
954 | ARRAY_SIZE(sh73a0_devices_dt)); | |
ea31597f | 955 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
d2347382 GL |
956 | |
957 | /* Instantiate cpufreq-cpu0 */ | |
958 | platform_device_register_full(&devinfo); | |
48609533 SH |
959 | } |
960 | ||
961 | static const char *sh73a0_boards_compat_dt[] __initdata = { | |
962 | "renesas,sh73a0", | |
963 | NULL, | |
964 | }; | |
965 | ||
966 | DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") | |
f9989507 | 967 | .smp = smp_ops(sh73a0_smp_ops), |
48609533 | 968 | .map_io = sh73a0_map_io, |
3b00f934 | 969 | .init_early = sh73a0_init_delay, |
48609533 | 970 | .nr_irqs = NR_IRQS_LEGACY, |
48609533 | 971 | .init_machine = sh73a0_add_standard_devices_dt, |
48609533 SH |
972 | .dt_compat = sh73a0_boards_compat_dt, |
973 | MACHINE_END | |
974 | #endif /* CONFIG_USE_OF */ |