projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 97991657 MD |
1 | /* |
| 2 | * sh7372 lowlevel sleep code for "Core Standby Mode" | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Magnus Damm | |
| 5 | * | |
| 6 | * In "Core Standby Mode" the ARM core is off, but L2 cache is still on | |
| 7 | * | |
| 8 | * Based on mach-omap2/sleep34xx.S | |
| 9 | * | |
| 10 | * (C) Copyright 2007 Texas Instruments | |
| 11 | * Karthik Dasu <karthik-dp@ti.com> | |
| 12 | * | |
| 13 | * (C) Copyright 2004 Texas Instruments, <www.ti.com> | |
| 14 | * Richard Woodruff <r-woodruff2@ti.com> | |
| 15 | * | |
| 16 | * This program is free software; you can redistribute it and/or | |
| 17 | * modify it under the terms of the GNU General Public License as | |
| 18 | * published by the Free Software Foundation; either version 2 of | |
| 19 | * the License, or (at your option) any later version. | |
| 20 | * | |
| 21 | * This program is distributed in the hope that it will be useful, | |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the | |
| 24 | * GNU General Public License for more details. | |
| 25 | * | |
| 26 | * You should have received a copy of the GNU General Public License | |
| 27 | * along with this program; if not, write to the Free Software | |
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 29 | * MA 02111-1307 USA | |
| 30 | */ | |
| 31 | ||
| 32 | #include <linux/linkage.h> | |
| 06b84166 MD |
33 | #include <linux/init.h> |
| 34 | #include <asm/memory.h> | |
| 97991657 MD |
35 | #include <asm/assembler.h> |
| 36 | ||
| a0089bd6 | 37 | #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) |
| 97991657 MD |
38 | .align 12 |
| 39 | .text | |
| f7dadb37 MD |
40 | .global sh7372_resume_core_standby_sysc |
| 41 | sh7372_resume_core_standby_sysc: | |
| 06b84166 | 42 | ldr pc, 1f |
| e26f4067 | 43 | |
| 0b933cb3 | 44 | .align 2 |
| e26f4067 MD |
45 | .globl sh7372_cpu_resume |
| 46 | sh7372_cpu_resume: | |
| 47 | 1: .space 4 | |
| cf33835c | 48 | |
| f7dadb37 MD |
49 | #define SPDCR 0xe6180008 |
| 50 | ||
| 51 | /* A3SM & A4S power down */ | |
| 52 | .global sh7372_do_idle_sysc | |
| 53 | sh7372_do_idle_sysc: | |
| 54 | mov r8, r0 /* sleep mode passed in r0 */ | |
| 55 | ||
| cf33835c MD |
56 | /* |
| 57 | * Clear the SCTLR.C bit to prevent further data cache | |
| 58 | * allocation. Clearing SCTLR.C would make all the data accesses | |
| 59 | * strongly ordered and would not hit the cache. | |
| 60 | */ | |
| 61 | mrc p15, 0, r0, c1, c0, 0 | |
| 62 | bic r0, r0, #(1 << 2) @ Disable the C bit | |
| 63 | mcr p15, 0, r0, c1, c0, 0 | |
| 64 | isb | |
| 65 | ||
| 99161524 GL |
66 | /* |
| 67 | * Clean and invalidate data cache again. | |
| 68 | */ | |
| 69 | ldr r1, kernel_flush | |
| 70 | blx r1 | |
| 71 | ||
| cf33835c MD |
72 | /* disable L2 cache in the aux control register */ |
| 73 | mrc p15, 0, r10, c1, c0, 1 | |
| 74 | bic r10, r10, #2 | |
| 75 | mcr p15, 0, r10, c1, c0, 1 | |
| 99161524 | 76 | isb |
| cf33835c | 77 | |
| cf33835c MD |
78 | /* |
| 79 | * The kernel doesn't interwork: v7_flush_dcache_all in particluar will | |
| 80 | * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. | |
| 81 | * This sequence switches back to ARM. Note that .align may insert a | |
| 82 | * nop: bx pc needs to be word-aligned in order to work. | |
| 83 | */ | |
| 84 | THUMB( .thumb ) | |
| 85 | THUMB( .align ) | |
| 86 | THUMB( bx pc ) | |
| 87 | THUMB( nop ) | |
| 88 | .arm | |
| 89 | ||
| 90 | /* Data memory barrier and Data sync barrier */ | |
| 91 | dsb | |
| 92 | dmb | |
| 93 | ||
| f7dadb37 | 94 | /* SYSC power down */ |
| cf33835c | 95 | ldr r0, =SPDCR |
| f7dadb37 | 96 | str r8, [r0] |
| cf33835c MD |
97 | 1: |
| 98 | b 1b | |
| 99 | ||
| 0b933cb3 | 100 | .align 2 |
| cf33835c MD |
101 | kernel_flush: |
| 102 | .word v7_flush_dcache_all | |
| a0089bd6 | 103 | #endif |