Commit | Line | Data |
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72f4d579 MD |
1 | /* |
2 | * SMP support for R-Mobile / SH-Mobile - sh73a0 portion | |
3 | * | |
4 | * Copyright (C) 2010 Magnus Damm | |
5 | * Copyright (C) 2010 Takashi Yoshii | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
72f4d579 MD |
15 | */ |
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/smp.h> | |
72f4d579 | 19 | #include <linux/io.h> |
a62580e5 | 20 | #include <linux/delay.h> |
ded59d6d | 21 | |
352e57a3 | 22 | #include <asm/smp_plat.h> |
72f4d579 | 23 | #include <asm/smp_twd.h> |
ded59d6d | 24 | |
fd44aa5e | 25 | #include "common.h" |
ded59d6d | 26 | #include "sh73a0.h" |
72f4d579 | 27 | |
a2a47ca3 RH |
28 | #define WUPCR IOMEM(0xe6151010) |
29 | #define SRESCR IOMEM(0xe6151018) | |
30 | #define PSTR IOMEM(0xe6151040) | |
31 | #define SBAR IOMEM(0xe6180020) | |
32 | #define APARMBAREA IOMEM(0xe6f10020) | |
72f4d579 | 33 | |
76853504 | 34 | #define SH73A0_SCU_BASE 0xf0000000 |
aa8d3bb1 | 35 | |
d6720003 | 36 | #ifdef CONFIG_HAVE_ARM_TWD |
aa8d3bb1 | 37 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); |
d6720003 KM |
38 | void __init sh73a0_register_twd(void) |
39 | { | |
40 | twd_local_timer_register(&twd_local_timer); | |
41 | } | |
42 | #endif | |
4200b16d | 43 | |
8bd26e3a | 44 | static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) |
72f4d579 | 45 | { |
12eb8474 | 46 | unsigned int lcpu = cpu_logical_map(cpu); |
12eb8474 MD |
47 | |
48 | if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3) | |
49 | __raw_writel(1 << lcpu, WUPCR); /* wake up */ | |
72f4d579 | 50 | else |
12eb8474 | 51 | __raw_writel(1 << lcpu, SRESCR); /* reset */ |
72f4d579 MD |
52 | |
53 | return 0; | |
54 | } | |
55 | ||
a62580e5 | 56 | static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) |
72f4d579 | 57 | { |
12eb8474 | 58 | /* Map the reset vector (in headsmp.S) */ |
a2a47ca3 | 59 | __raw_writel(0, APARMBAREA); /* 4k */ |
abfa04eb | 60 | __raw_writel(__pa(shmobile_boot_vector), SBAR); |
72f4d579 | 61 | |
12eb8474 MD |
62 | /* setup sh73a0 specific SCU bits */ |
63 | shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); | |
64 | shmobile_smp_scu_prepare_cpus(max_cpus); | |
72f4d579 | 65 | } |
a62580e5 | 66 | |
a62580e5 | 67 | struct smp_operations sh73a0_smp_ops __initdata = { |
a62580e5 | 68 | .smp_prepare_cpus = sh73a0_smp_prepare_cpus, |
a62580e5 MZ |
69 | .smp_boot_secondary = sh73a0_boot_secondary, |
70 | #ifdef CONFIG_HOTPLUG_CPU | |
a3b142a1 | 71 | .cpu_disable = shmobile_smp_cpu_disable, |
352e57a3 MD |
72 | .cpu_die = shmobile_smp_scu_cpu_die, |
73 | .cpu_kill = shmobile_smp_scu_cpu_kill, | |
a62580e5 MZ |
74 | #endif |
75 | }; |