Commit | Line | Data |
---|---|---|
72f4d579 MD |
1 | /* |
2 | * SMP support for R-Mobile / SH-Mobile - sh73a0 portion | |
3 | * | |
4 | * Copyright (C) 2010 Magnus Damm | |
5 | * Copyright (C) 2010 Takashi Yoshii | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | */ | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/smp.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/io.h> | |
a62580e5 | 25 | #include <linux/delay.h> |
520f7bd7 | 26 | #include <linux/irqchip/arm-gic.h> |
72f4d579 | 27 | #include <mach/common.h> |
20aa1135 | 28 | #include <asm/cacheflush.h> |
eb50439b | 29 | #include <asm/smp_plat.h> |
a62580e5 | 30 | #include <mach/sh73a0.h> |
72f4d579 MD |
31 | #include <asm/smp_scu.h> |
32 | #include <asm/smp_twd.h> | |
72f4d579 | 33 | |
a2a47ca3 RH |
34 | #define WUPCR IOMEM(0xe6151010) |
35 | #define SRESCR IOMEM(0xe6151018) | |
36 | #define PSTR IOMEM(0xe6151040) | |
37 | #define SBAR IOMEM(0xe6180020) | |
38 | #define APARMBAREA IOMEM(0xe6f10020) | |
72f4d579 | 39 | |
20aa1135 BH |
40 | #define PSTR_SHUTDOWN_MODE 3 |
41 | ||
72f4d579 MD |
42 | static void __iomem *scu_base_addr(void) |
43 | { | |
44 | return (void __iomem *)0xf0000000; | |
45 | } | |
46 | ||
d6720003 | 47 | #ifdef CONFIG_HAVE_ARM_TWD |
4200b16d | 48 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); |
d6720003 KM |
49 | void __init sh73a0_register_twd(void) |
50 | { | |
51 | twd_local_timer_register(&twd_local_timer); | |
52 | } | |
53 | #endif | |
4200b16d | 54 | |
a62580e5 | 55 | static void __cpuinit sh73a0_secondary_init(unsigned int cpu) |
72f4d579 | 56 | { |
c0312b33 | 57 | gic_secondary_init(0); |
72f4d579 MD |
58 | } |
59 | ||
a62580e5 | 60 | static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) |
72f4d579 | 61 | { |
f80ca52c WD |
62 | cpu = cpu_logical_map(cpu); |
63 | ||
820d41cf | 64 | if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3) |
a2a47ca3 | 65 | __raw_writel(1 << cpu, WUPCR); /* wake up */ |
72f4d579 | 66 | else |
a2a47ca3 | 67 | __raw_writel(1 << cpu, SRESCR); /* reset */ |
72f4d579 MD |
68 | |
69 | return 0; | |
70 | } | |
71 | ||
a62580e5 | 72 | static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) |
72f4d579 | 73 | { |
72f4d579 MD |
74 | scu_enable(scu_base_addr()); |
75 | ||
33419a69 | 76 | /* Map the reset vector (in headsmp-sh73a0.S) */ |
a2a47ca3 | 77 | __raw_writel(0, APARMBAREA); /* 4k */ |
33419a69 | 78 | __raw_writel(__pa(sh73a0_secondary_vector), SBAR); |
72f4d579 | 79 | |
33419a69 BH |
80 | /* enable cache coherency on booting CPU */ |
81 | scu_power_mode(scu_base_addr(), SCU_PM_NORMAL); | |
72f4d579 | 82 | } |
a62580e5 MZ |
83 | |
84 | static void __init sh73a0_smp_init_cpus(void) | |
85 | { | |
f313ae4e | 86 | unsigned int ncores = scu_get_core_count(scu_base_addr()); |
a62580e5 MZ |
87 | |
88 | shmobile_smp_init_cpus(ncores); | |
89 | } | |
90 | ||
20aa1135 BH |
91 | #ifdef CONFIG_HOTPLUG_CPU |
92 | static int sh73a0_cpu_kill(unsigned int cpu) | |
a62580e5 | 93 | { |
20aa1135 | 94 | |
a62580e5 | 95 | int k; |
20aa1135 | 96 | u32 pstr; |
a62580e5 | 97 | |
20aa1135 BH |
98 | /* |
99 | * wait until the power status register confirms the shutdown of the | |
100 | * offline target | |
a62580e5 MZ |
101 | */ |
102 | for (k = 0; k < 1000; k++) { | |
20aa1135 BH |
103 | pstr = (__raw_readl(PSTR) >> (4 * cpu)) & 3; |
104 | if (pstr == PSTR_SHUTDOWN_MODE) | |
a62580e5 MZ |
105 | return 1; |
106 | ||
107 | mdelay(1); | |
108 | } | |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
20aa1135 BH |
113 | static void sh73a0_cpu_die(unsigned int cpu) |
114 | { | |
115 | /* | |
116 | * The ARM MPcore does not issue a cache coherency request for the L1 | |
117 | * cache when powering off single CPUs. We must take care of this and | |
118 | * further caches. | |
119 | */ | |
120 | dsb(); | |
121 | flush_cache_all(); | |
122 | ||
123 | /* Set power off mode. This takes the CPU out of the MP cluster */ | |
124 | scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF); | |
125 | ||
126 | /* Enter shutdown mode */ | |
127 | cpu_do_idle(); | |
128 | } | |
129 | #endif /* CONFIG_HOTPLUG_CPU */ | |
a62580e5 MZ |
130 | |
131 | struct smp_operations sh73a0_smp_ops __initdata = { | |
132 | .smp_init_cpus = sh73a0_smp_init_cpus, | |
133 | .smp_prepare_cpus = sh73a0_smp_prepare_cpus, | |
134 | .smp_secondary_init = sh73a0_secondary_init, | |
135 | .smp_boot_secondary = sh73a0_boot_secondary, | |
136 | #ifdef CONFIG_HOTPLUG_CPU | |
137 | .cpu_kill = sh73a0_cpu_kill, | |
20aa1135 | 138 | .cpu_die = sh73a0_cpu_die, |
dc784e73 | 139 | .cpu_disable = shmobile_cpu_disable_any, |
a62580e5 MZ |
140 | #endif |
141 | }; |