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66314223 DN |
1 | /* |
2 | * Copyright (C) 2012 Altera Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
0529e315 | 17 | #include <linux/irqchip.h> |
9c4566a1 | 18 | #include <linux/of_address.h> |
66314223 DN |
19 | #include <linux/of_irq.h> |
20 | #include <linux/of_platform.h> | |
7b6d864b | 21 | #include <linux/reboot.h> |
66314223 DN |
22 | |
23 | #include <asm/hardware/cache-l2x0.h> | |
66314223 | 24 | #include <asm/mach/arch.h> |
9c4566a1 | 25 | #include <asm/mach/map.h> |
66314223 | 26 | |
9c4566a1 DN |
27 | #include "core.h" |
28 | ||
29 | void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); | |
30 | void __iomem *sys_manager_base_addr; | |
31 | void __iomem *rst_manager_base_addr; | |
56c5c13f | 32 | void __iomem *clk_mgr_base_addr; |
d6dd735f | 33 | unsigned long cpu1start_addr; |
9c4566a1 DN |
34 | |
35 | static struct map_desc scu_io_desc __initdata = { | |
36 | .virtual = SOCFPGA_SCU_VIRT_BASE, | |
37 | .pfn = 0, /* run-time */ | |
38 | .length = SZ_8K, | |
39 | .type = MT_DEVICE, | |
40 | }; | |
41 | ||
ef21b491 PM |
42 | static struct map_desc uart_io_desc __initdata = { |
43 | .virtual = 0xfec02000, | |
44 | .pfn = __phys_to_pfn(0xffc02000), | |
45 | .length = SZ_8K, | |
46 | .type = MT_DEVICE, | |
47 | }; | |
48 | ||
9c4566a1 DN |
49 | static void __init socfpga_scu_map_io(void) |
50 | { | |
51 | unsigned long base; | |
52 | ||
53 | /* Get SCU base */ | |
54 | asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); | |
55 | ||
56 | scu_io_desc.pfn = __phys_to_pfn(base); | |
57 | iotable_init(&scu_io_desc, 1); | |
58 | } | |
59 | ||
60 | static void __init socfpga_map_io(void) | |
61 | { | |
62 | socfpga_scu_map_io(); | |
ef21b491 PM |
63 | iotable_init(&uart_io_desc, 1); |
64 | early_printk("Early printk initialized\n"); | |
9c4566a1 | 65 | } |
66314223 | 66 | |
9c4566a1 DN |
67 | void __init socfpga_sysmgr_init(void) |
68 | { | |
69 | struct device_node *np; | |
70 | ||
71 | np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); | |
d6dd735f DN |
72 | |
73 | if (of_property_read_u32(np, "cpu1-start-addr", | |
74 | (u32 *) &cpu1start_addr)) | |
75 | pr_err("SMP: Need cpu1-start-addr in device tree.\n"); | |
76 | ||
9c4566a1 DN |
77 | sys_manager_base_addr = of_iomap(np, 0); |
78 | ||
79 | np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); | |
80 | rst_manager_base_addr = of_iomap(np, 0); | |
56c5c13f DN |
81 | |
82 | np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); | |
83 | clk_mgr_base_addr = of_iomap(np, 0); | |
9c4566a1 DN |
84 | } |
85 | ||
0529e315 | 86 | static void __init socfpga_init_irq(void) |
66314223 | 87 | { |
0529e315 | 88 | irqchip_init(); |
9c4566a1 | 89 | socfpga_sysmgr_init(); |
66314223 DN |
90 | } |
91 | ||
7b6d864b | 92 | static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) |
66314223 | 93 | { |
5c04b57f DN |
94 | u32 temp; |
95 | ||
96 | temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | |
97 | ||
7b6d864b | 98 | if (mode == REBOOT_HARD) |
5c04b57f DN |
99 | temp |= RSTMGR_CTRL_SWCOLDRSTREQ; |
100 | else | |
101 | temp |= RSTMGR_CTRL_SWWARMRSTREQ; | |
102 | writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); | |
66314223 DN |
103 | } |
104 | ||
105 | static void __init socfpga_cyclone5_init(void) | |
106 | { | |
107 | l2x0_of_init(0, ~0UL); | |
108 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | |
109 | socfpga_init_clocks(); | |
110 | } | |
111 | ||
112 | static const char *altera_dt_match[] = { | |
113 | "altr,socfpga", | |
66314223 DN |
114 | NULL |
115 | }; | |
116 | ||
117 | DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") | |
9c4566a1 DN |
118 | .smp = smp_ops(socfpga_smp_ops), |
119 | .map_io = socfpga_map_io, | |
0529e315 | 120 | .init_irq = socfpga_init_irq, |
66314223 DN |
121 | .init_machine = socfpga_cyclone5_init, |
122 | .restart = socfpga_cyclone5_restart, | |
123 | .dt_compat = altera_dt_match, | |
124 | MACHINE_END |